[SWDEV-528647/SWDEV-528450] Reduce API load times and libdrm/libdrm_amdgpu dynamic loading (#333)
Changes:
- Removed libdrm/libdrm_amdgpu dependencies
- Added/updated new internal libdrm/libdrm_amdgpu/xf86drm APIs
to allow our APIs to reference before dynamic loading
the libdrm/libdrm_amdgpu libraries:
1. amdgpu_drm.h to what's seen in mainline
2. Added xf86drm.h to whats seen in mainline
- Modified internal DRM capabilities:
1. Require each API to independently connect to libdrm/libdrm_amdgpu
+ validate API handles reponses accordingly
2. Initialization of AMD SMI no longer has as strong of a tie to
libdrm
- Updated internal implementations of several APIs which have
connections to libdrm/libdrm_amdgpu or APIs which have conflicts
with open libdrm/libdrm_amdgpu connections:
1. amdsmi_init()
2. amdsmi_get_gpu_vram_usage()
3. amdsmi_get_gpu_asic_info()
4. amdsmi_get_gpu_vram_info()
5. amdsmi_get_gpu_vbios_info()
6. amdsmi_get_gpu_driver_info()
7. amdsmi_get_gpu_virtualization_mode()
8. amdsmi_set_gpu_memory_partition()
9. amdsmi_set_gpu_memory_partition_mode()
- Cleaned up effected tests/APIs
Change-Id: I96e2cf1b06b0cfee1b01a5e991ccc6116c4245a8
This commit is contained in:
Poag, Charis authored and 
GitHub committed
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@@ -17,7 +17,7 @@
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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@@ -29,10 +29,15 @@
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* Keith Whitwell <keith@tungstengraphics.com>
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*/
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#ifndef __AMDGPU_DRM_H__
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#define __AMDGPU_DRM_H__
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#ifndef __LIBDRM_AMDGPU__
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#define __LIBDRM_AMDGPU__
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#include <libdrm/amdgpu.h>
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#endif
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#ifndef __LIBDRM__
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#define __LIBDRM__
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#include <libdrm/drm.h>
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#endif
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#if defined(__cplusplus)
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extern "C" {
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@@ -54,12 +59,6 @@ extern "C" {
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#define DRM_AMDGPU_VM 0x13
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#define DRM_AMDGPU_FENCE_TO_HANDLE 0x14
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#define DRM_AMDGPU_SCHED 0x15
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/* not upstream */
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#define DRM_AMDGPU_FREESYNC 0x5d
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#define DRM_AMDGPU_GEM_DGMA 0x5c
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/* hybrid specific ioctls */
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#define DRM_AMDGPU_SEM 0x5b
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#define DRM_IOCTL_AMDGPU_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_CREATE, union drm_amdgpu_gem_create)
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#define DRM_IOCTL_AMDGPU_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_MMAP, union drm_amdgpu_gem_mmap)
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@@ -77,9 +76,6 @@ extern "C" {
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#define DRM_IOCTL_AMDGPU_VM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_VM, union drm_amdgpu_vm)
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#define DRM_IOCTL_AMDGPU_FENCE_TO_HANDLE DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FENCE_TO_HANDLE, union drm_amdgpu_fence_to_handle)
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#define DRM_IOCTL_AMDGPU_SCHED DRM_IOW(DRM_COMMAND_BASE + DRM_AMDGPU_SCHED, union drm_amdgpu_sched)
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#define DRM_IOCTL_AMDGPU_FREESYNC DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_FREESYNC, struct drm_amdgpu_freesync)
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#define DRM_IOCTL_AMDGPU_GEM_DGMA DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_GEM_DGMA, struct drm_amdgpu_gem_dgma)
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/**
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* DOC: memory domains
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@@ -89,7 +85,7 @@ extern "C" {
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*
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* %AMDGPU_GEM_DOMAIN_GTT GPU accessible system memory, mapped into the
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* GPU's virtual address space via gart. Gart memory linearizes non-contiguous
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* pages of system memory, allows GPU access system memory in a linezrized
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* pages of system memory, allows GPU access system memory in a linearized
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* fashion.
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*
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* %AMDGPU_GEM_DOMAIN_VRAM Local video memory. For APUs, it is memory
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@@ -103,28 +99,24 @@ extern "C" {
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*
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* %AMDGPU_GEM_DOMAIN_OA Ordered append, used by 3D or Compute engines
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* for appending data.
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*
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* %AMDGPU_GEM_DOMAIN_DOORBELL Doorbell. It is an MMIO region for
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* signalling user mode queues.
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*/
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/* hybrid specific ioctls */
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#define DRM_IOCTL_AMDGPU_SEM DRM_IOWR(DRM_COMMAND_BASE + DRM_AMDGPU_SEM, union drm_amdgpu_sem)
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#define AMDGPU_GEM_DOMAIN_CPU 0x1
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#define AMDGPU_GEM_DOMAIN_GTT 0x2
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#define AMDGPU_GEM_DOMAIN_VRAM 0x4
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#define AMDGPU_GEM_DOMAIN_GDS 0x8
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#define AMDGPU_GEM_DOMAIN_GWS 0x10
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#define AMDGPU_GEM_DOMAIN_OA 0x20
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#define AMDGPU_GEM_DOMAIN_DGMA 0x40
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#define AMDGPU_GEM_DOMAIN_DGMA_IMPORT 0x80
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#define AMDGPU_GEM_DOMAIN_DGMA_PEER 0x100 /* verylike DGMA_IMPORT but it doesn't consume domain0 GART space */
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#define AMDGPU_GEM_DOMAIN_DOORBELL 0x40
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#define AMDGPU_GEM_DOMAIN_MASK (AMDGPU_GEM_DOMAIN_CPU | \
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AMDGPU_GEM_DOMAIN_GTT | \
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AMDGPU_GEM_DOMAIN_VRAM | \
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AMDGPU_GEM_DOMAIN_GDS | \
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AMDGPU_GEM_DOMAIN_GWS | \
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AMDGPU_GEM_DOMAIN_OA |\
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AMDGPU_GEM_DOMAIN_DGMA |\
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AMDGPU_GEM_DOMAIN_DGMA_IMPORT |\
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AMDGPU_GEM_DOMAIN_DGMA_PEER)
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AMDGPU_GEM_DOMAIN_OA | \
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AMDGPU_GEM_DOMAIN_DOORBELL)
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/* Flag that CPU access will be required for the case of VRAM domain */
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#define AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED (1 << 0)
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@@ -134,8 +126,6 @@ extern "C" {
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#define AMDGPU_GEM_CREATE_CPU_GTT_USWC (1 << 2)
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/* Flag that the memory should be in VRAM and cleared */
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#define AMDGPU_GEM_CREATE_VRAM_CLEARED (1 << 3)
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/* Flag that create shadow bo(GTT) while allocating vram bo */
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#define AMDGPU_GEM_CREATE_SHADOW (1 << 4)
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/* Flag that allocating the BO should use linear VRAM */
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#define AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS (1 << 5)
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/* Flag that BO is always valid in this VM */
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@@ -156,14 +146,38 @@ extern "C" {
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* accessing it with various hw blocks
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*/
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#define AMDGPU_GEM_CREATE_ENCRYPTED (1 << 10)
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/* hybrid specific */
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/* Flag that the memory should be in SPARSE resource */
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#define AMDGPU_GEM_CREATE_SPARSE (1ULL << 29)
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/* Flag that the memory allocation should be from top of domain */
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#define AMDGPU_GEM_CREATE_TOP_DOWN (1ULL << 30)
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/* Flag that the memory allocation should be pinned */
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#define AMDGPU_GEM_CREATE_NO_EVICT (1ULL << 31)
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/* Flag that BO will be used only in preemptible context, which does
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* not require GTT memory accounting
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*/
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#define AMDGPU_GEM_CREATE_PREEMPTIBLE (1 << 11)
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/* Flag that BO can be discarded under memory pressure without keeping the
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* content.
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*/
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#define AMDGPU_GEM_CREATE_DISCARDABLE (1 << 12)
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/* Flag that BO is shared coherently between multiple devices or CPU threads.
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* May depend on GPU instructions to flush caches to system scope explicitly.
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*
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* This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and
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* may override the MTYPE selected in AMDGPU_VA_OP_MAP.
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*/
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#define AMDGPU_GEM_CREATE_COHERENT (1 << 13)
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/* Flag that BO should not be cached by GPU. Coherent without having to flush
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* GPU caches explicitly
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*
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* This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and
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* may override the MTYPE selected in AMDGPU_VA_OP_MAP.
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*/
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#define AMDGPU_GEM_CREATE_UNCACHED (1 << 14)
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/* Flag that BO should be coherent across devices when using device-level
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* atomics. May depend on GPU instructions to flush caches to device scope
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* explicitly, promoting them to system scope automatically.
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*
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* This influences the choice of MTYPE in the PTEs on GFXv9 and later GPUs and
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* may override the MTYPE selected in AMDGPU_VA_OP_MAP.
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*/
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#define AMDGPU_GEM_CREATE_EXT_COHERENT (1 << 15)
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/* Set PTE.D and recompress during GTT->VRAM moves according to TILING flags. */
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#define AMDGPU_GEM_CREATE_GFX12_DCC (1 << 16)
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struct drm_amdgpu_gem_create_in {
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/** the requested memory size */
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@@ -230,6 +244,8 @@ union drm_amdgpu_bo_list {
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#define AMDGPU_CTX_OP_FREE_CTX 2
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#define AMDGPU_CTX_OP_QUERY_STATE 3
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#define AMDGPU_CTX_OP_QUERY_STATE2 4
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#define AMDGPU_CTX_OP_GET_STABLE_PSTATE 5
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#define AMDGPU_CTX_OP_SET_STABLE_PSTATE 6
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/* GPU reset status */
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#define AMDGPU_CTX_NO_RESET 0
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@@ -240,15 +256,17 @@ union drm_amdgpu_bo_list {
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/* unknown cause */
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#define AMDGPU_CTX_UNKNOWN_RESET 3
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/* indicate gpu reset occured after ctx created */
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/* indicate gpu reset occurred after ctx created */
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#define AMDGPU_CTX_QUERY2_FLAGS_RESET (1<<0)
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/* indicate vram lost occured after ctx created */
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/* indicate vram lost occurred after ctx created */
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#define AMDGPU_CTX_QUERY2_FLAGS_VRAMLOST (1<<1)
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/* indicate some job from this context once cause gpu hang */
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#define AMDGPU_CTX_QUERY2_FLAGS_GUILTY (1<<2)
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/* indicate some errors are detected by RAS */
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#define AMDGPU_CTX_QUERY2_FLAGS_RAS_CE (1<<3)
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#define AMDGPU_CTX_QUERY2_FLAGS_RAS_UE (1<<4)
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/* indicate that the reset hasn't completed yet */
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#define AMDGPU_CTX_QUERY2_FLAGS_RESET_IN_PROGRESS (1<<5)
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/* Context priority level */
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#define AMDGPU_CTX_PRIORITY_UNSET -2048
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@@ -262,10 +280,18 @@ union drm_amdgpu_bo_list {
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#define AMDGPU_CTX_PRIORITY_HIGH 512
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#define AMDGPU_CTX_PRIORITY_VERY_HIGH 1023
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/* select a stable profiling pstate for perfmon tools */
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#define AMDGPU_CTX_STABLE_PSTATE_FLAGS_MASK 0xf
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#define AMDGPU_CTX_STABLE_PSTATE_NONE 0
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#define AMDGPU_CTX_STABLE_PSTATE_STANDARD 1
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#define AMDGPU_CTX_STABLE_PSTATE_MIN_SCLK 2
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#define AMDGPU_CTX_STABLE_PSTATE_MIN_MCLK 3
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#define AMDGPU_CTX_STABLE_PSTATE_PEAK 4
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struct drm_amdgpu_ctx_in {
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/** AMDGPU_CTX_OP_* */
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__u32 op;
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/** For future use, no flags defined so far */
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/** Flags */
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__u32 flags;
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__u32 ctx_id;
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/** AMDGPU_CTX_PRIORITY_* */
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@@ -286,6 +312,11 @@ union drm_amdgpu_ctx_out {
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/** Reset status since the last call of the ioctl. */
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__u32 reset_status;
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} state;
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struct {
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__u32 flags;
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__u32 _pad;
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} pstate;
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};
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union drm_amdgpu_ctx {
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@@ -293,35 +324,6 @@ union drm_amdgpu_ctx {
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union drm_amdgpu_ctx_out out;
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};
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/* sem related */
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#define AMDGPU_SEM_OP_CREATE_SEM 1
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#define AMDGPU_SEM_OP_WAIT_SEM 2
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#define AMDGPU_SEM_OP_SIGNAL_SEM 3
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#define AMDGPU_SEM_OP_DESTROY_SEM 4
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#define AMDGPU_SEM_OP_IMPORT_SEM 5
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#define AMDGPU_SEM_OP_EXPORT_SEM 6
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struct drm_amdgpu_sem_in {
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/** AMDGPU_SEM_OP_* */
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uint32_t op;
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uint32_t handle;
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uint32_t ctx_id;
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uint32_t ip_type;
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uint32_t ip_instance;
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uint32_t ring;
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uint64_t seq;
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};
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union drm_amdgpu_sem_out {
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int32_t fd;
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uint32_t handle;
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};
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union drm_amdgpu_sem {
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struct drm_amdgpu_sem_in in;
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union drm_amdgpu_sem_out out;
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};
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/* vm ioctl */
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#define AMDGPU_VM_OP_RESERVE_VMID 1
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#define AMDGPU_VM_OP_UNRESERVE_VMID 2
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@@ -368,7 +370,6 @@ union drm_amdgpu_sched {
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#define AMDGPU_GEM_USERPTR_ANONONLY (1 << 1)
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#define AMDGPU_GEM_USERPTR_VALIDATE (1 << 2)
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#define AMDGPU_GEM_USERPTR_REGISTER (1 << 3)
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#define AMDGPU_GEM_USERPTR_PEERMEM (1 << 4)
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struct drm_amdgpu_gem_userptr {
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__u64 addr;
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@@ -379,15 +380,6 @@ struct drm_amdgpu_gem_userptr {
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__u32 handle;
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};
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#define AMDGPU_GEM_DGMA_IMPORT 0
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#define AMDGPU_GEM_DGMA_QUERY_PHYS_ADDR 1
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struct drm_amdgpu_gem_dgma {
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__u64 addr;
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__u64 size;
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__u32 op;
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__u32 handle;
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};
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/* SI-CI-VI: */
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/* same meaning as the GB_TILE_MODE and GL_MACRO_TILE_MODE fields */
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#define AMDGPU_TILING_ARRAY_MODE_SHIFT 0
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@@ -407,7 +399,7 @@ struct drm_amdgpu_gem_dgma {
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#define AMDGPU_TILING_NUM_BANKS_SHIFT 21
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#define AMDGPU_TILING_NUM_BANKS_MASK 0x3
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/* GFX9 and later: */
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/* GFX9 - GFX11: */
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#define AMDGPU_TILING_SWIZZLE_MODE_SHIFT 0
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#define AMDGPU_TILING_SWIZZLE_MODE_MASK 0x1f
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#define AMDGPU_TILING_DCC_OFFSET_256B_SHIFT 5
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@@ -416,6 +408,28 @@ struct drm_amdgpu_gem_dgma {
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#define AMDGPU_TILING_DCC_PITCH_MAX_MASK 0x3FFF
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#define AMDGPU_TILING_DCC_INDEPENDENT_64B_SHIFT 43
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#define AMDGPU_TILING_DCC_INDEPENDENT_64B_MASK 0x1
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#define AMDGPU_TILING_DCC_INDEPENDENT_128B_SHIFT 44
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#define AMDGPU_TILING_DCC_INDEPENDENT_128B_MASK 0x1
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#define AMDGPU_TILING_SCANOUT_SHIFT 63
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#define AMDGPU_TILING_SCANOUT_MASK 0x1
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/* GFX12 and later: */
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#define AMDGPU_TILING_GFX12_SWIZZLE_MODE_SHIFT 0
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#define AMDGPU_TILING_GFX12_SWIZZLE_MODE_MASK 0x7
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/* These are DCC recompression settings for memory management: */
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#define AMDGPU_TILING_GFX12_DCC_MAX_COMPRESSED_BLOCK_SHIFT 3
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#define AMDGPU_TILING_GFX12_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3 /* 0:64B, 1:128B, 2:256B */
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#define AMDGPU_TILING_GFX12_DCC_NUMBER_TYPE_SHIFT 5
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#define AMDGPU_TILING_GFX12_DCC_NUMBER_TYPE_MASK 0x7 /* CB_COLOR0_INFO.NUMBER_TYPE */
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#define AMDGPU_TILING_GFX12_DCC_DATA_FORMAT_SHIFT 8
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#define AMDGPU_TILING_GFX12_DCC_DATA_FORMAT_MASK 0x3f /* [0:4]:CB_COLOR0_INFO.FORMAT, [5]:MM */
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/* When clearing the buffer or moving it from VRAM to GTT, don't compress and set DCC metadata
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* to uncompressed. Set when parts of an allocation bypass DCC and read raw data. */
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#define AMDGPU_TILING_GFX12_DCC_WRITE_COMPRESS_DISABLE_SHIFT 14
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#define AMDGPU_TILING_GFX12_DCC_WRITE_COMPRESS_DISABLE_MASK 0x1
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/* bit gap */
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#define AMDGPU_TILING_GFX12_SCANOUT_SHIFT 63
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#define AMDGPU_TILING_GFX12_SCANOUT_MASK 0x1
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/* Set/Get helpers for tiling flags. */
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#define AMDGPU_TILING_SET(field, value) \
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@@ -563,16 +577,18 @@ struct drm_amdgpu_gem_op {
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#define AMDGPU_VM_MTYPE_MASK (0xf << 5)
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/* Default MTYPE. Pre-AI must use this. Recommended for newer ASICs. */
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#define AMDGPU_VM_MTYPE_DEFAULT (0 << 5)
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/* Use NC MTYPE instead of default MTYPE */
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/* Use Non Coherent MTYPE instead of default MTYPE */
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#define AMDGPU_VM_MTYPE_NC (1 << 5)
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/* Use WC MTYPE instead of default MTYPE */
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/* Use Write Combine MTYPE instead of default MTYPE */
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#define AMDGPU_VM_MTYPE_WC (2 << 5)
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/* Use CC MTYPE instead of default MTYPE */
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/* Use Cache Coherent MTYPE instead of default MTYPE */
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#define AMDGPU_VM_MTYPE_CC (3 << 5)
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/* Use UC MTYPE instead of default MTYPE */
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/* Use UnCached MTYPE instead of default MTYPE */
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#define AMDGPU_VM_MTYPE_UC (4 << 5)
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/* Use RW MTYPE instead of default MTYPE */
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/* Use Read Write MTYPE instead of default MTYPE */
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#define AMDGPU_VM_MTYPE_RW (5 << 5)
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/* don't allocate MALL */
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#define AMDGPU_VM_PAGE_NOALLOC (1 << 9)
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struct drm_amdgpu_gem_va {
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/** GEM object handle */
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@@ -597,9 +613,14 @@ struct drm_amdgpu_gem_va {
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#define AMDGPU_HW_IP_VCE 4
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#define AMDGPU_HW_IP_UVD_ENC 5
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#define AMDGPU_HW_IP_VCN_DEC 6
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/*
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* From VCN4, AMDGPU_HW_IP_VCN_ENC is re-used to support
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* both encoding and decoding jobs.
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*/
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#define AMDGPU_HW_IP_VCN_ENC 7
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#define AMDGPU_HW_IP_VCN_JPEG 8
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#define AMDGPU_HW_IP_NUM 9
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#define AMDGPU_HW_IP_VPE 9
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#define AMDGPU_HW_IP_NUM 10
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#define AMDGPU_HW_IP_INSTANCE_MAX_COUNT 1
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@@ -612,6 +633,7 @@ struct drm_amdgpu_gem_va {
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#define AMDGPU_CHUNK_ID_SCHEDULED_DEPENDENCIES 0x07
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||||
#define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_WAIT 0x08
|
||||
#define AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL 0x09
|
||||
#define AMDGPU_CHUNK_ID_CP_GFX_SHADOW 0x0a
|
||||
|
||||
struct drm_amdgpu_cs_chunk {
|
||||
__u32 chunk_id;
|
||||
@@ -663,6 +685,10 @@ union drm_amdgpu_cs {
|
||||
*/
|
||||
#define AMDGPU_IB_FLAGS_SECURE (1 << 5)
|
||||
|
||||
/* Tell KMD to flush and invalidate caches
|
||||
*/
|
||||
#define AMDGPU_IB_FLAG_EMIT_MEM_SYNC (1 << 6)
|
||||
|
||||
struct drm_amdgpu_cs_chunk_ib {
|
||||
__u32 _pad;
|
||||
/** AMDGPU_IB_FLAG_* */
|
||||
@@ -724,7 +750,16 @@ struct drm_amdgpu_cs_chunk_data {
|
||||
};
|
||||
};
|
||||
|
||||
/**
|
||||
#define AMDGPU_CS_CHUNK_CP_GFX_SHADOW_FLAGS_INIT_SHADOW 0x1
|
||||
|
||||
struct drm_amdgpu_cs_chunk_cp_gfx_shadow {
|
||||
__u64 shadow_va;
|
||||
__u64 csa_va;
|
||||
__u64 gds_va;
|
||||
__u64 flags;
|
||||
};
|
||||
|
||||
/*
|
||||
* Query h/w info: Flag that this is integrated (a.h.a. fusion) GPU
|
||||
*
|
||||
*/
|
||||
@@ -792,7 +827,22 @@ struct drm_amdgpu_cs_chunk_data {
|
||||
#define AMDGPU_INFO_FW_TA 0x13
|
||||
/* Subquery id: Query DMCUB firmware version */
|
||||
#define AMDGPU_INFO_FW_DMCUB 0x14
|
||||
#define AMDGPU_INFO_FW_CAP 0x15
|
||||
/* Subquery id: Query TOC firmware version */
|
||||
#define AMDGPU_INFO_FW_TOC 0x15
|
||||
/* Subquery id: Query CAP firmware version */
|
||||
#define AMDGPU_INFO_FW_CAP 0x16
|
||||
/* Subquery id: Query GFX RLCP firmware version */
|
||||
#define AMDGPU_INFO_FW_GFX_RLCP 0x17
|
||||
/* Subquery id: Query GFX RLCV firmware version */
|
||||
#define AMDGPU_INFO_FW_GFX_RLCV 0x18
|
||||
/* Subquery id: Query MES_KIQ firmware version */
|
||||
#define AMDGPU_INFO_FW_MES_KIQ 0x19
|
||||
/* Subquery id: Query MES firmware version */
|
||||
#define AMDGPU_INFO_FW_MES 0x1a
|
||||
/* Subquery id: Query IMU firmware version */
|
||||
#define AMDGPU_INFO_FW_IMU 0x1b
|
||||
/* Subquery id: Query VPE firmware version */
|
||||
#define AMDGPU_INFO_FW_VPE 0x1c
|
||||
|
||||
/* number of bytes moved for TTM migration */
|
||||
#define AMDGPU_INFO_NUM_BYTES_MOVED 0x0f
|
||||
@@ -846,12 +896,17 @@ struct drm_amdgpu_cs_chunk_data {
|
||||
#define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_SCLK 0x8
|
||||
/* Subquery id: Query GPU stable pstate memory clock */
|
||||
#define AMDGPU_INFO_SENSOR_STABLE_PSTATE_GFX_MCLK 0x9
|
||||
/* Subquery id: Query GPU peak pstate shader clock */
|
||||
#define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_SCLK 0xa
|
||||
/* Subquery id: Query GPU peak pstate memory clock */
|
||||
#define AMDGPU_INFO_SENSOR_PEAK_PSTATE_GFX_MCLK 0xb
|
||||
/* Subquery id: Query input GPU power */
|
||||
#define AMDGPU_INFO_SENSOR_GPU_INPUT_POWER 0xc
|
||||
/* Number of VRAM page faults on CPU access. */
|
||||
#define AMDGPU_INFO_NUM_VRAM_CPU_PAGE_FAULTS 0x1E
|
||||
#define AMDGPU_INFO_VRAM_LOST_COUNTER 0x1F
|
||||
/* query ras mask of enabled features*/
|
||||
#define AMDGPU_INFO_RAS_ENABLED_FEATURES 0x20
|
||||
|
||||
/* RAS MASK: UMC (VRAM) */
|
||||
#define AMDGPU_INFO_RAS_ENABLED_UMC (1 << 0)
|
||||
/* RAS MASK: SDMA */
|
||||
@@ -880,18 +935,16 @@ struct drm_amdgpu_cs_chunk_data {
|
||||
#define AMDGPU_INFO_RAS_ENABLED_MP1 (1 << 12)
|
||||
/* RAS MASK: FUSE */
|
||||
#define AMDGPU_INFO_RAS_ENABLED_FUSE (1 << 13)
|
||||
|
||||
/* Hybrid Stack Specific Defs*/
|
||||
/* gpu capability */
|
||||
#define AMDGPU_INFO_CAPABILITY 0x50
|
||||
/* virtual range */
|
||||
#define AMDGPU_INFO_VIRTUAL_RANGE 0x51
|
||||
/* query pin memory capability */
|
||||
#define AMDGPU_CAPABILITY_PIN_MEM_FLAG (1 << 0)
|
||||
/* query direct gma capability */
|
||||
#define AMDGPU_CAPABILITY_DIRECT_GMA_FLAG (1 << 1)
|
||||
/* query ssg capability */
|
||||
#define AMDGPU_CAPABILITY_SSG_FLAG (1 << 2)
|
||||
/* query video encode/decode caps */
|
||||
#define AMDGPU_INFO_VIDEO_CAPS 0x21
|
||||
/* Subquery id: Decode */
|
||||
#define AMDGPU_INFO_VIDEO_CAPS_DECODE 0
|
||||
/* Subquery id: Encode */
|
||||
#define AMDGPU_INFO_VIDEO_CAPS_ENCODE 1
|
||||
/* Query the max number of IBs per gang per submission */
|
||||
#define AMDGPU_INFO_MAX_IBS 0x22
|
||||
/* query last page fault info */
|
||||
#define AMDGPU_INFO_GPUVM_FAULT 0x23
|
||||
|
||||
#define AMDGPU_INFO_MMR_SE_INDEX_SHIFT 0
|
||||
#define AMDGPU_INFO_MMR_SE_INDEX_MASK 0xff
|
||||
@@ -949,11 +1002,6 @@ struct drm_amdgpu_info {
|
||||
__u32 flags;
|
||||
} read_mmr_reg;
|
||||
|
||||
struct {
|
||||
uint32_t aperture;
|
||||
uint32_t _pad;
|
||||
} virtual_range;
|
||||
|
||||
struct drm_amdgpu_query_fw query_fw;
|
||||
|
||||
struct {
|
||||
@@ -964,6 +1012,10 @@ struct drm_amdgpu_info {
|
||||
struct {
|
||||
__u32 type;
|
||||
} sensor_info;
|
||||
|
||||
struct {
|
||||
__u32 type;
|
||||
} video_cap;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -1043,8 +1095,9 @@ struct drm_amdgpu_info_vbios {
|
||||
#define AMDGPU_VRAM_TYPE_DDR3 7
|
||||
#define AMDGPU_VRAM_TYPE_DDR4 8
|
||||
#define AMDGPU_VRAM_TYPE_GDDR6 9
|
||||
|
||||
#define AMDGPU_VRAM_TYPE_HBM_WIDTH 4096
|
||||
#define AMDGPU_VRAM_TYPE_DDR5 10
|
||||
#define AMDGPU_VRAM_TYPE_LPDDR4 11
|
||||
#define AMDGPU_VRAM_TYPE_LPDDR5 12
|
||||
|
||||
struct drm_amdgpu_info_device {
|
||||
/** PCI Device ID */
|
||||
@@ -1070,8 +1123,9 @@ struct drm_amdgpu_info_device {
|
||||
__u32 enabled_rb_pipes_mask;
|
||||
__u32 num_rb_pipes;
|
||||
__u32 num_hw_gfx_contexts;
|
||||
__u32 _pad;
|
||||
__u64 ids_flags; // Relevant info here REMOVE LATER
|
||||
/* PCIe version (the smaller of the GPU and the CPU/motherboard) */
|
||||
__u32 pcie_gen;
|
||||
__u64 ids_flags;
|
||||
/** Starting virtual address for UMDs. */
|
||||
__u64 virtual_address_offset;
|
||||
/** The maximum virtual address */
|
||||
@@ -1117,7 +1171,8 @@ struct drm_amdgpu_info_device {
|
||||
__u32 gs_prim_buffer_depth;
|
||||
/* max gs wavefront per vgt*/
|
||||
__u32 max_gs_waves_per_vgt;
|
||||
__u32 _pad1;
|
||||
/* PCIe number of lanes (the smaller of the GPU and the CPU/motherboard) */
|
||||
__u32 pcie_num_lanes;
|
||||
/* always on cu bitmap */
|
||||
__u32 cu_ao_bitmap[4][4];
|
||||
/** Starting high virtual address for UMDs. */
|
||||
@@ -1128,6 +1183,26 @@ struct drm_amdgpu_info_device {
|
||||
__u32 pa_sc_tile_steering_override;
|
||||
/* disabled TCCs */
|
||||
__u64 tcc_disabled_mask;
|
||||
__u64 min_engine_clock;
|
||||
__u64 min_memory_clock;
|
||||
/* The following fields are only set on gfx11+, older chips set 0. */
|
||||
__u32 tcp_cache_size; /* AKA GL0, VMEM cache */
|
||||
__u32 num_sqc_per_wgp;
|
||||
__u32 sqc_data_cache_size; /* AKA SMEM cache */
|
||||
__u32 sqc_inst_cache_size;
|
||||
__u32 gl1c_cache_size;
|
||||
__u32 gl2c_cache_size;
|
||||
__u64 mall_size; /* AKA infinity cache */
|
||||
/* high 32 bits of the rb pipes mask */
|
||||
__u32 enabled_rb_pipes_mask_hi;
|
||||
/* shadow area size for gfx11 */
|
||||
__u32 shadow_size;
|
||||
/* shadow area base virtual alignment for gfx11 */
|
||||
__u32 shadow_alignment;
|
||||
/* context save area size for gfx11 */
|
||||
__u32 csa_size;
|
||||
/* context save area base virtual alignment for gfx11 */
|
||||
__u32 csa_alignment;
|
||||
};
|
||||
|
||||
struct drm_amdgpu_info_hw_ip {
|
||||
@@ -1142,7 +1217,8 @@ struct drm_amdgpu_info_hw_ip {
|
||||
__u32 ib_size_alignment;
|
||||
/** Bitmask of available rings. Bit 0 means ring 0, etc. */
|
||||
__u32 available_rings;
|
||||
__u32 _pad;
|
||||
/** version info: bits 23:16 major, 15:8 minor, 7:0 revision */
|
||||
__u32 ip_discovery_version;
|
||||
};
|
||||
|
||||
struct drm_amdgpu_info_num_handles {
|
||||
@@ -1170,6 +1246,44 @@ struct drm_amdgpu_info_vce_clock_table {
|
||||
__u32 pad;
|
||||
};
|
||||
|
||||
/* query video encode/decode caps */
|
||||
#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG2 0
|
||||
#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4 1
|
||||
#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VC1 2
|
||||
#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_MPEG4_AVC 3
|
||||
#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_HEVC 4
|
||||
#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_JPEG 5
|
||||
#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_VP9 6
|
||||
#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_AV1 7
|
||||
#define AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT 8
|
||||
|
||||
struct drm_amdgpu_info_video_codec_info {
|
||||
__u32 valid;
|
||||
__u32 max_width;
|
||||
__u32 max_height;
|
||||
__u32 max_pixels_per_frame;
|
||||
__u32 max_level;
|
||||
__u32 pad;
|
||||
};
|
||||
|
||||
struct drm_amdgpu_info_video_caps {
|
||||
struct drm_amdgpu_info_video_codec_info codec_info[AMDGPU_INFO_VIDEO_CAPS_CODEC_IDX_COUNT];
|
||||
};
|
||||
|
||||
#define AMDGPU_VMHUB_TYPE_MASK 0xff
|
||||
#define AMDGPU_VMHUB_TYPE_SHIFT 0
|
||||
#define AMDGPU_VMHUB_TYPE_GFX 0
|
||||
#define AMDGPU_VMHUB_TYPE_MM0 1
|
||||
#define AMDGPU_VMHUB_TYPE_MM1 2
|
||||
#define AMDGPU_VMHUB_IDX_MASK 0xff00
|
||||
#define AMDGPU_VMHUB_IDX_SHIFT 8
|
||||
|
||||
struct drm_amdgpu_info_gpuvm_fault {
|
||||
__u64 addr;
|
||||
__u32 status;
|
||||
__u32 vmhub;
|
||||
};
|
||||
|
||||
/*
|
||||
* Supported GPU families
|
||||
*/
|
||||
@@ -1182,37 +1296,24 @@ struct drm_amdgpu_info_vce_clock_table {
|
||||
#define AMDGPU_FAMILY_AI 141 /* Vega10 */
|
||||
#define AMDGPU_FAMILY_RV 142 /* Raven */
|
||||
#define AMDGPU_FAMILY_NV 143 /* Navi10 */
|
||||
#define AMDGPU_FAMILY_VGH 144 /* Van Gogh */
|
||||
#define AMDGPU_FAMILY_GC_11_0_0 145 /* GC 11.0.0 */
|
||||
#define AMDGPU_FAMILY_YC 146 /* Yellow Carp */
|
||||
#define AMDGPU_FAMILY_GC_11_0_1 148 /* GC 11.0.1 */
|
||||
#define AMDGPU_FAMILY_GC_10_3_6 149 /* GC 10.3.6 */
|
||||
#define AMDGPU_FAMILY_GC_10_3_7 151 /* GC 10.3.7 */
|
||||
#define AMDGPU_FAMILY_GC_11_5_0 150 /* GC 11.5.0 */
|
||||
#define AMDGPU_FAMILY_GC_12_0_0 152 /* GC 12.0.0 */
|
||||
|
||||
/**
|
||||
* Definition of System Unified Address (SUA) apertures
|
||||
*/
|
||||
#define AMDGPU_SUA_APERTURE_PRIVATE 1
|
||||
#define AMDGPU_SUA_APERTURE_SHARED 2
|
||||
struct drm_amdgpu_virtual_range {
|
||||
uint64_t start;
|
||||
uint64_t end;
|
||||
};
|
||||
|
||||
struct drm_amdgpu_capability {
|
||||
__u32 flag;
|
||||
__u32 direct_gma_size;
|
||||
};
|
||||
|
||||
/*
|
||||
* Definition of free sync enter and exit signals
|
||||
* We may have more options in the future
|
||||
*/
|
||||
#define AMDGPU_FREESYNC_FULLSCREEN_ENTER 1
|
||||
#define AMDGPU_FREESYNC_FULLSCREEN_EXIT 2
|
||||
|
||||
struct drm_amdgpu_freesync {
|
||||
__u32 op; /* AMDGPU_FREESYNC_FULLSCREEN_ENTER or */
|
||||
/* AMDGPU_FREESYNC_FULLSCREEN_ENTER */
|
||||
__u32 spare[7];
|
||||
/* FIXME wrong namespace! */
|
||||
struct drm_color_ctm_3x4 {
|
||||
/*
|
||||
* Conversion matrix with 3x4 dimensions in S31.32 sign-magnitude
|
||||
* (not two's complement!) format.
|
||||
*/
|
||||
__u64 matrix[12];
|
||||
};
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
Reference in new issue
Block a user