Add CI workloads for MI300A_A1 and MI300X_A1

Signed-off-by: coleramos425 <colramos@amd.com>
2024-05-31 16:09:58 -05:00
@@ -0,0 +1,4 @@
+Dispatch_ID,GPU_ID,Queue_ID,PID,TID,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,Wave_Size,Kernel_Name,Start_Timestamp,End_Timestamp,Correlation_ID,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES
+0,11995,1,148337,148337,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",73843971992178,73843971999909,0,218990.0,218990.0,16384.0,65536.0,28159.0,2249984.0
+1,11995,1,148337,148337,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",73843972017897,73843972024226,0,194419.0,194419.0,16384.0,65536.0,13100.0,1048608.0
+2,11995,1,148337,148337,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",73843972039650,73843972045859,0,166313.0,166313.0,16384.0,65536.0,13087.0,1048708.0
@@ -0,0 +1,4 @@
+Dispatch_ID,GPU_ID,Queue_ID,PID,TID,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,Wave_Size,Kernel_Name,Start_Timestamp,End_Timestamp,Correlation_ID,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES
+0,11995,1,148348,148348,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",73843971992178,73843971999909,0,0.0,0.0,0.0
+1,11995,1,148348,148348,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",73843972017897,73843972024226,0,0.0,0.0,0.0
+2,11995,1,148348,148348,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",73843972039650,73843972045859,0,0.0,0.0,0.0
@@ -0,0 +1,4 @@
+Dispatch_ID,GPU_ID,Queue_ID,PID,TID,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,Wave_Size,Kernel_Name,Start_Timestamp,End_Timestamp,Correlation_ID,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES
+0,11995,1,148359,148359,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",73843971992178,73843971999909,0,65536.0,359830.0,28775024.0
+1,11995,1,148359,148359,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",73843972017897,73843972024226,0,65536.0,279626.0,22368848.0
+2,11995,1,148359,148359,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",73843972039650,73843972045859,0,65536.0,212150.0,16965480.0
@@ -0,0 +1,4 @@
+Dispatch_ID,GPU_ID,Queue_ID,PID,TID,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,Wave_Size,Kernel_Name,Start_Timestamp,End_Timestamp,Correlation_ID,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES
+0,11995,1,148370,148370,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",73843971992178,73843971999909,0,32768.0,540654.0,43241432.0
+1,11995,1,148370,148370,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",73843972017897,73843972024226,0,32768.0,423717.0,33892596.0
+2,11995,1,148370,148370,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",73843972039650,73843972045859,0,32768.0,421757.0,33736452.0
@@ -0,0 +1,4 @@
+Dispatch_ID,GPU_ID,Queue_ID,PID,TID,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,Wave_Size,Kernel_Name,Start_Timestamp,End_Timestamp,Correlation_ID,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES
+0,11995,1,148381,148381,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",73843971992178,73843971999909,0,215077.0,215077.0,120524.0,860308.0,16384.0,14073357.0,258076.0,0.0,56727488.0
+1,11995,1,148381,148381,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",73843972017897,73843972024226,0,186817.0,186817.0,103332.0,747268.0,16384.0,10901162.0,200092.0,0.0,43996920.0
+2,11995,1,148381,148381,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",73843972039650,73843972045859,0,183393.0,183393.0,102287.0,733572.0,16384.0,10354964.0,192829.0,0.0,41809560.0
@@ -0,0 +1,247 @@
+Omniperf version: 2.0.0
+Profiler choice: rocprofv2
+Path: /home/colramos/omniperf/tests/workloads/device_filter/MI300A_A1
+Target: MI300A_A1
+Command: ./tests/vcopy -n 1048576 -b 256 -i 3
+Kernel Selection: None
+Dispatch Selection: None
+Hardware Blocks: All
+
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Collecting Performance Counters
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+[profiling] Current input file: tests/workloads/device_filter/MI300A_A1/perfmon/SQ_IFETCH_LEVEL.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - GRBM_COUNT
+   |-> [/opt/rocm/bin/rocprofv2] - GRBM_GUI_ACTIVE
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_WAVES
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_IFETCH
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_IFETCH_LEVEL
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_ACCUM_PREV_HIRES
+   |-> [/opt/rocm/bin/rocprofv2] Enabling Counter Collection
+   |-> [/opt/rocm/bin/rocprofv2] vcopy testing on GCD 0
+   |-> [/opt/rocm/bin/rocprofv2] Finished allocating vectors on the CPU
+   |-> [/opt/rocm/bin/rocprofv2] Finished allocating vectors on the GPU
+   |-> [/opt/rocm/bin/rocprofv2] Finished copying vectors to the GPU
+   |-> [/opt/rocm/bin/rocprofv2] sw thinks it moved 1.000000 KB per wave
+   |-> [/opt/rocm/bin/rocprofv2] Total threads: 1048576, Grid Size: 4096 block Size:256, Wavefronts:16384:
+   |-> [/opt/rocm/bin/rocprofv2] Launching the  kernel on the GPU
+   |-> [/opt/rocm/bin/rocprofv2] Finished executing kernel
+   |-> [/opt/rocm/bin/rocprofv2] Finished executing kernel
+[profiling] Current input file: tests/workloads/device_filter/MI300A_A1/perfmon/SQ_INST_LEVEL_LDS.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_LDS
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INST_LEVEL_LDS
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_ACCUM_PREV_HIRES
+   |-> [/opt/rocm/bin/rocprofv2] Enabling Counter Collection
+   |-> [/opt/rocm/bin/rocprofv2] vcopy testing on GCD 0
+   |-> [/opt/rocm/bin/rocprofv2] Finished allocating vectors on the CPU
+   |-> [/opt/rocm/bin/rocprofv2] Finished allocating vectors on the GPU
+   |-> [/opt/rocm/bin/rocprofv2] Finished copying vectors to the GPU
+   |-> [/opt/rocm/bin/rocprofv2] sw thinks it moved 1.000000 KB per wave
+   |-> [/opt/rocm/bin/rocprofv2] Total threads: 1048576, Grid Size: 4096 block Size:256, Wavefronts:16384:
+[profiling] Current input file: tests/workloads/device_filter/MI300A_A1/perfmon/SQ_INST_LEVEL_SMEM.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_SMEM
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INST_LEVEL_SMEM
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_ACCUM_PREV_HIRES
+   |-> [/opt/rocm/bin/rocprofv2] Enabling Counter Collection
+   |-> [/opt/rocm/bin/rocprofv2] vcopy testing on GCD 0
+   |-> [/opt/rocm/bin/rocprofv2] Finished allocating vectors on the CPU
+   |-> [/opt/rocm/bin/rocprofv2] Finished allocating vectors on the GPU
+   |-> [/opt/rocm/bin/rocprofv2] Finished copying vectors to the GPU
+   |-> [/opt/rocm/bin/rocprofv2] sw thinks it moved 1.000000 KB per wave
+   |-> [/opt/rocm/bin/rocprofv2] Total threads: 1048576, Grid Size: 4096 block Size:256, Wavefronts:16384:
+[profiling] Current input file: tests/workloads/device_filter/MI300A_A1/perfmon/SQ_INST_LEVEL_VMEM.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VMEM
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INST_LEVEL_VMEM
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_ACCUM_PREV_HIRES
+   |-> [/opt/rocm/bin/rocprofv2] Enabling Counter Collection
+   |-> [/opt/rocm/bin/rocprofv2] vcopy testing on GCD 0
+   |-> [/opt/rocm/bin/rocprofv2] Finished allocating vectors on the CPU
+   |-> [/opt/rocm/bin/rocprofv2] Finished allocating vectors on the GPU
+   |-> [/opt/rocm/bin/rocprofv2] Finished copying vectors to the GPU
+   |-> [/opt/rocm/bin/rocprofv2] sw thinks it moved 1.000000 KB per wave
+   |-> [/opt/rocm/bin/rocprofv2] Total threads: 1048576, Grid Size: 4096 block Size:256, Wavefronts:16384:
+   |-> [/opt/rocm/bin/rocprofv2] Launching the  kernel on the GPU
+   |-> [/opt/rocm/bin/rocprofv2] Finished executing kernel
+   |-> [/opt/rocm/bin/rocprofv2] Finished executing kernel
+   |-> [/opt/rocm/bin/rocprofv2] Finished executing kernel
+   |-> [/opt/rocm/bin/rocprofv2] Finished copying the output vector from the GPU to the CPU
+   |-> [/opt/rocm/bin/rocprofv2] Releasing GPU memory
+   |-> [/opt/rocm/bin/rocprofv2] Releasing CPU memory
+   |-> [/opt/rocm/bin/rocprofv2] Results File: "tests/workloads/device_filter/MI300A_A1/out/pmc_1/results_SQ_INST_LEVEL_VMEM.csv"
+   |-> [/opt/rocm/bin/rocprofv2] 
+   |-> [/opt/rocm/bin/rocprofv2] The output path for the following counters: tests/workloads/device_filter/MI300A_A1/out/pmc_1
+[profiling] Current input file: tests/workloads/device_filter/MI300A_A1/perfmon/SQ_LEVEL_WAVES.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - GRBM_COUNT
+   |-> [/opt/rocm/bin/rocprofv2] - GRBM_GUI_ACTIVE
+   |-> [/opt/rocm/bin/rocprofv2] - CPC_ME1_BUSY_FOR_PACKET_DECODE
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_CYCLES
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_WAVES
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_WAVE_CYCLES
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_BUSY_CYCLES
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_LEVEL_WAVES
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_ACCUM_PREV_HIRES
+[profiling] Current input file: tests/workloads/device_filter/MI300A_A1/perfmon/pmc_perf_0.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_CYCLES
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_BUSY_CYCLES
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_BUSY_CU_CYCLES
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_WAVES
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_WAVE_CYCLES
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_CVT
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VMEM_WR
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VMEM_RD
+[profiling] Current input file: tests/workloads/device_filter/MI300A_A1/perfmon/pmc_perf_1.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VMEM
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_SALU
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VSKIPPED
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_ADD_F16
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_MUL_F16
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_FMA_F16
+   |-> [/opt/rocm/bin/rocprofv2] - GRBM_SPI_BUSY
+[profiling] Current input file: tests/workloads/device_filter/MI300A_A1/perfmon/pmc_perf_10.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQC_TC_DATA_ATOMIC_REQ
+   |-> [/opt/rocm/bin/rocprofv2] - SQC_TC_STALL
+   |-> [/opt/rocm/bin/rocprofv2] - SQC_TC_REQ
+[profiling] Current input file: tests/workloads/device_filter/MI300A_A1/perfmon/pmc_perf_11.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQC_DCACHE_INPUT_VALID_READYB
+   |-> [/opt/rocm/bin/rocprofv2] - SQC_DCACHE_ATOMIC
+   |-> [/opt/rocm/bin/rocprofv2] - SQC_DCACHE_REQ_READ_8
+[profiling] Current input file: tests/workloads/device_filter/MI300A_A1/perfmon/pmc_perf_12.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQC_DCACHE_REQ_READ_2
+   |-> [/opt/rocm/bin/rocprofv2] - SQC_DCACHE_REQ_READ_4
+   |-> [/opt/rocm/bin/rocprofv2] Enabling Counter Collection
+[profiling] Current input file: tests/workloads/device_filter/MI300A_A1/perfmon/pmc_perf_13.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_ATOMIC[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_BUBBLE[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_CYCLE[0]
+[profiling] Current input file: tests/workloads/device_filter/MI300A_A1/perfmon/pmc_perf_14.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_EA0_ATOMIC_LEVEL[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_EA0_RDREQ[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_EA0_RDREQ_32B[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_EA0_RDREQ_LEVEL[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_EA0_ATOMIC_LEVEL[1]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_EA0_RDREQ[1]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_EA0_RDREQ_32B[1]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_EA0_RDREQ_LEVEL[1]
+[profiling] Current input file: tests/workloads/device_filter/MI300A_A1/perfmon/pmc_perf_15.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_EA0_WRREQ[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_EA0_WRREQ_64B[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_EA0_WRREQ_LEVEL[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_HIT[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_EA0_WRREQ[1]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_EA0_WRREQ_64B[1]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_EA0_WRREQ_LEVEL[1]
+[profiling] Current input file: tests/workloads/device_filter/MI300A_A1/perfmon/pmc_perf_16.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_MISS[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_READ[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_REQ[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_RW_REQ[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_MISS[1]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_READ[1]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_REQ[1]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_RW_REQ[1]
+[profiling] Current input file: tests/workloads/device_filter/MI300A_A1/perfmon/pmc_perf_17.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_TAG_STALL[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_TOO_MANY_EA_WRREQS_STALL[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_WRITE[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_TAG_STALL[1]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_TOO_MANY_EA_WRREQS_STALL[1]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_WRITE[1]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_TAG_STALL[2]
+[profiling] Current input file: tests/workloads/device_filter/MI300A_A1/perfmon/pmc_perf_2.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_TRANS_F16
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_ADD_F32
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_MUL_F32
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_FMA_F32
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_TRANS_F32
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_ADD_F64
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_MUL_F64
+[profiling] Current input file: tests/workloads/device_filter/MI300A_A1/perfmon/pmc_perf_3.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_TRANS_F64
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_INT32
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_INT64
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_SMEM
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_FLAT
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_LDS
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_GDS
+[profiling] Current input file: tests/workloads/device_filter/MI300A_A1/perfmon/pmc_perf_4.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_BRANCH
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_SENDMSG
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_WAIT_ANY
+[profiling] Current input file: tests/workloads/device_filter/MI300A_A1/perfmon/pmc_perf_5.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_ACTIVE_INST_SCA
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_ACTIVE_INST_EXP_GDS
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_ACTIVE_INST_MISC
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_ACTIVE_INST_FLAT
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INST_CYCLES_VMEM_WR
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INST_CYCLES_VMEM_RD
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INST_CYCLES_SMEM
+[profiling] Current input file: tests/workloads/device_filter/MI300A_A1/perfmon/pmc_perf_6.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_THREAD_CYCLES_VALU
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_IFETCH
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_LDS_BANK_CONFLICT
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_LDS_ADDR_CONFLICT
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_LDS_UNALIGNED_STALL
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_WAVES_EQ_64
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_WAVES_LT_64
+[profiling] Current input file: tests/workloads/device_filter/MI300A_A1/perfmon/pmc_perf_7.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_WAVES_LT_32
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_WAVES_LT_16
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_ITEMS
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_LDS_MEM_VIOLATIONS
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_LDS_ATOMIC_RETURN
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_LDS_IDX_ACTIVE
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_WAVES_RESTORED
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_WAVES_SAVED
+[profiling] Current input file: tests/workloads/device_filter/MI300A_A1/perfmon/pmc_perf_8.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_SMEM_NORM
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_MFMA
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_MFMA_I8
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_MFMA_F16
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_MFMA_BF16
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_MFMA_F32
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_MFMA_F64
+[profiling] Current input file: tests/workloads/device_filter/MI300A_A1/perfmon/pmc_perf_9.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_MFMA_MOPS_I8
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_MFMA_MOPS_F16
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_MFMA_MOPS_BF16
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_MFMA_MOPS_F32
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_MFMA_MOPS_F64
+   |-> [/opt/rocm/bin/rocprofv2] - SQC_TC_INST_REQ
+   |-> [/opt/rocm/bin/rocprofv2] - SQC_TC_DATA_READ_REQ
+   |-> [/opt/rocm/bin/rocprofv2] - SQC_TC_DATA_WRITE_REQ
+[profiling] Current input file: tests/workloads/device_filter/MI300A_A1/perfmon/timestamps.txt
+   |-> [/opt/rocm/bin/rocprofv2] vcopy testing on GCD 0
+   |-> [/opt/rocm/bin/rocprofv2] Finished allocating vectors on the CPU
+   |-> [/opt/rocm/bin/rocprofv2] Finished allocating vectors on the GPU
+   |-> [/opt/rocm/bin/rocprofv2] Finished copying vectors to the GPU
+   |-> [/opt/rocm/bin/rocprofv2] sw thinks it moved 1.000000 KB per wave
+   |-> [/opt/rocm/bin/rocprofv2] Total threads: 1048576, Grid Size: 4096 block Size:256, Wavefronts:16384:
+   |-> [/opt/rocm/bin/rocprofv2] Launching the  kernel on the GPU
+   |-> [/opt/rocm/bin/rocprofv2] Finished executing kernel
+[roofline] Roofline temporarily disabled in MI300
@@ -0,0 +1,5 @@
+pmc: GRBM_COUNT GRBM_GUI_ACTIVE SQ_WAVES SQ_IFETCH SQ_IFETCH_LEVEL  SQ_ACCUM_PREV_HIRES
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc: SQ_INSTS_LDS SQ_INST_LEVEL_LDS  SQ_ACCUM_PREV_HIRES
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc: SQ_INSTS_SMEM  SQ_INST_LEVEL_SMEM SQ_ACCUM_PREV_HIRES
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc: SQ_INSTS_VMEM  SQ_INST_LEVEL_VMEM SQ_ACCUM_PREV_HIRES
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc: GRBM_COUNT GRBM_GUI_ACTIVE CPC_ME1_BUSY_FOR_PACKET_DECODE SQ_CYCLES SQ_WAVES SQ_WAVE_CYCLES SQ_BUSY_CYCLES SQ_LEVEL_WAVES  SQ_ACCUM_PREV_HIRES
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQ_CYCLES SQ_BUSY_CYCLES SQ_BUSY_CU_CYCLES SQ_WAVES SQ_WAVE_CYCLES SQ_INSTS_VALU_CVT SQ_INSTS_VMEM_WR SQ_INSTS_VMEM_RD GRBM_COUNT GRBM_GUI_ACTIVE TCP_GATE_EN1_sum TCP_GATE_EN2_sum TCP_TD_TCP_STALL_CYCLES_sum TCP_TCR_TCP_STALL_CYCLES_sum TA_TA_BUSY_sum TA_BUFFER_WAVEFRONTS_sum TD_TD_BUSY_sum TD_TC_STALL_sum SPI_CSN_WINDOW_VALID SPI_CSN_BUSY CPC_CPC_STAT_BUSY CPC_CPC_STAT_IDLE CPF_CPF_STAT_BUSY CPF_CPF_STAT_STALL TCC_CYCLE_sum TCC_BUSY_sum TCC_PROBE_sum TCC_PROBE_ALL_sum
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQ_INSTS_VMEM SQ_INSTS_SALU SQ_INSTS_VSKIPPED SQ_INSTS SQ_INSTS_VALU SQ_INSTS_VALU_ADD_F16 SQ_INSTS_VALU_MUL_F16 SQ_INSTS_VALU_FMA_F16 GRBM_SPI_BUSY TCP_READ_TAGCONFLICT_STALL_CYCLES_sum TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum TCP_TA_TCP_STATE_READ_sum TA_BUFFER_READ_WAVEFRONTS_sum TA_BUFFER_WRITE_WAVEFRONTS_sum TD_SPI_STALL_sum TD_LOAD_WAVEFRONT_sum SPI_CSN_NUM_THREADGROUPS SPI_CSN_WAVE CPC_CPC_TCIU_BUSY CPC_CPC_TCIU_IDLE CPF_CPF_TCIU_BUSY CPF_CPF_TCIU_STALL TCC_NC_REQ_sum TCC_UC_REQ_sum TCC_CC_REQ_sum TCC_RW_REQ_sum
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQC_TC_DATA_ATOMIC_REQ SQC_TC_STALL SQC_TC_REQ SQC_DCACHE_REQ_READ_16 SQC_ICACHE_REQ SQC_ICACHE_HITS SQC_ICACHE_MISSES SQC_ICACHE_MISSES_DUPLICATE
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQC_DCACHE_INPUT_VALID_READYB SQC_DCACHE_ATOMIC SQC_DCACHE_REQ_READ_8 SQC_DCACHE_REQ SQC_DCACHE_HITS SQC_DCACHE_MISSES SQC_DCACHE_MISSES_DUPLICATE SQC_DCACHE_REQ_READ_1
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQC_DCACHE_REQ_READ_2 SQC_DCACHE_REQ_READ_4
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  TCC_ATOMIC[0] TCC_BUBBLE[0] TCC_CYCLE[0] TCC_EA0_ATOMIC[0] TCC_ATOMIC[1] TCC_BUBBLE[1] TCC_CYCLE[1] TCC_EA0_ATOMIC[1] TCC_ATOMIC[2] TCC_BUBBLE[2] TCC_CYCLE[2] TCC_EA0_ATOMIC[2] TCC_ATOMIC[3] TCC_BUBBLE[3] TCC_CYCLE[3] TCC_EA0_ATOMIC[3] TCC_ATOMIC[4] TCC_BUBBLE[4] TCC_CYCLE[4] TCC_EA0_ATOMIC[4] TCC_ATOMIC[5] TCC_BUBBLE[5] TCC_CYCLE[5] TCC_EA0_ATOMIC[5] TCC_ATOMIC[6] TCC_BUBBLE[6] TCC_CYCLE[6] TCC_EA0_ATOMIC[6] TCC_ATOMIC[7] TCC_BUBBLE[7] TCC_CYCLE[7] TCC_EA0_ATOMIC[7] TCC_ATOMIC[8] TCC_BUBBLE[8] TCC_CYCLE[8] TCC_EA0_ATOMIC[8] TCC_ATOMIC[9] TCC_BUBBLE[9] TCC_CYCLE[9] TCC_EA0_ATOMIC[9] TCC_ATOMIC[10] TCC_BUBBLE[10] TCC_CYCLE[10] TCC_EA0_ATOMIC[10] TCC_ATOMIC[11] TCC_BUBBLE[11] TCC_CYCLE[11] TCC_EA0_ATOMIC[11] TCC_ATOMIC[12] TCC_BUBBLE[12] TCC_CYCLE[12] TCC_EA0_ATOMIC[12] TCC_ATOMIC[13] TCC_BUBBLE[13] TCC_CYCLE[13] TCC_EA0_ATOMIC[13] TCC_ATOMIC[14] TCC_BUBBLE[14] TCC_CYCLE[14] TCC_EA0_ATOMIC[14] TCC_ATOMIC[15] TCC_BUBBLE[15] TCC_CYCLE[15] TCC_EA0_ATOMIC[15]
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  TCC_EA0_ATOMIC_LEVEL[0] TCC_EA0_RDREQ[0] TCC_EA0_RDREQ_32B[0] TCC_EA0_RDREQ_LEVEL[0] TCC_EA0_ATOMIC_LEVEL[1] TCC_EA0_RDREQ[1] TCC_EA0_RDREQ_32B[1] TCC_EA0_RDREQ_LEVEL[1] TCC_EA0_ATOMIC_LEVEL[2] TCC_EA0_RDREQ[2] TCC_EA0_RDREQ_32B[2] TCC_EA0_RDREQ_LEVEL[2] TCC_EA0_ATOMIC_LEVEL[3] TCC_EA0_RDREQ[3] TCC_EA0_RDREQ_32B[3] TCC_EA0_RDREQ_LEVEL[3] TCC_EA0_ATOMIC_LEVEL[4] TCC_EA0_RDREQ[4] TCC_EA0_RDREQ_32B[4] TCC_EA0_RDREQ_LEVEL[4] TCC_EA0_ATOMIC_LEVEL[5] TCC_EA0_RDREQ[5] TCC_EA0_RDREQ_32B[5] TCC_EA0_RDREQ_LEVEL[5] TCC_EA0_ATOMIC_LEVEL[6] TCC_EA0_RDREQ[6] TCC_EA0_RDREQ_32B[6] TCC_EA0_RDREQ_LEVEL[6] TCC_EA0_ATOMIC_LEVEL[7] TCC_EA0_RDREQ[7] TCC_EA0_RDREQ_32B[7] TCC_EA0_RDREQ_LEVEL[7] TCC_EA0_ATOMIC_LEVEL[8] TCC_EA0_RDREQ[8] TCC_EA0_RDREQ_32B[8] TCC_EA0_RDREQ_LEVEL[8] TCC_EA0_ATOMIC_LEVEL[9] TCC_EA0_RDREQ[9] TCC_EA0_RDREQ_32B[9] TCC_EA0_RDREQ_LEVEL[9] TCC_EA0_ATOMIC_LEVEL[10] TCC_EA0_RDREQ[10] TCC_EA0_RDREQ_32B[10] TCC_EA0_RDREQ_LEVEL[10] TCC_EA0_ATOMIC_LEVEL[11] TCC_EA0_RDREQ[11] TCC_EA0_RDREQ_32B[11] TCC_EA0_RDREQ_LEVEL[11] TCC_EA0_ATOMIC_LEVEL[12] TCC_EA0_RDREQ[12] TCC_EA0_RDREQ_32B[12] TCC_EA0_RDREQ_LEVEL[12] TCC_EA0_ATOMIC_LEVEL[13] TCC_EA0_RDREQ[13] TCC_EA0_RDREQ_32B[13] TCC_EA0_RDREQ_LEVEL[13] TCC_EA0_ATOMIC_LEVEL[14] TCC_EA0_RDREQ[14] TCC_EA0_RDREQ_32B[14] TCC_EA0_RDREQ_LEVEL[14] TCC_EA0_ATOMIC_LEVEL[15] TCC_EA0_RDREQ[15] TCC_EA0_RDREQ_32B[15] TCC_EA0_RDREQ_LEVEL[15]
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  TCC_EA0_WRREQ[0] TCC_EA0_WRREQ_64B[0] TCC_EA0_WRREQ_LEVEL[0] TCC_HIT[0] TCC_EA0_WRREQ[1] TCC_EA0_WRREQ_64B[1] TCC_EA0_WRREQ_LEVEL[1] TCC_HIT[1] TCC_EA0_WRREQ[2] TCC_EA0_WRREQ_64B[2] TCC_EA0_WRREQ_LEVEL[2] TCC_HIT[2] TCC_EA0_WRREQ[3] TCC_EA0_WRREQ_64B[3] TCC_EA0_WRREQ_LEVEL[3] TCC_HIT[3] TCC_EA0_WRREQ[4] TCC_EA0_WRREQ_64B[4] TCC_EA0_WRREQ_LEVEL[4] TCC_HIT[4] TCC_EA0_WRREQ[5] TCC_EA0_WRREQ_64B[5] TCC_EA0_WRREQ_LEVEL[5] TCC_HIT[5] TCC_EA0_WRREQ[6] TCC_EA0_WRREQ_64B[6] TCC_EA0_WRREQ_LEVEL[6] TCC_HIT[6] TCC_EA0_WRREQ[7] TCC_EA0_WRREQ_64B[7] TCC_EA0_WRREQ_LEVEL[7] TCC_HIT[7] TCC_EA0_WRREQ[8] TCC_EA0_WRREQ_64B[8] TCC_EA0_WRREQ_LEVEL[8] TCC_HIT[8] TCC_EA0_WRREQ[9] TCC_EA0_WRREQ_64B[9] TCC_EA0_WRREQ_LEVEL[9] TCC_HIT[9] TCC_EA0_WRREQ[10] TCC_EA0_WRREQ_64B[10] TCC_EA0_WRREQ_LEVEL[10] TCC_HIT[10] TCC_EA0_WRREQ[11] TCC_EA0_WRREQ_64B[11] TCC_EA0_WRREQ_LEVEL[11] TCC_HIT[11] TCC_EA0_WRREQ[12] TCC_EA0_WRREQ_64B[12] TCC_EA0_WRREQ_LEVEL[12] TCC_HIT[12] TCC_EA0_WRREQ[13] TCC_EA0_WRREQ_64B[13] TCC_EA0_WRREQ_LEVEL[13] TCC_HIT[13] TCC_EA0_WRREQ[14] TCC_EA0_WRREQ_64B[14] TCC_EA0_WRREQ_LEVEL[14] TCC_HIT[14] TCC_EA0_WRREQ[15] TCC_EA0_WRREQ_64B[15] TCC_EA0_WRREQ_LEVEL[15] TCC_HIT[15]
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  TCC_MISS[0] TCC_READ[0] TCC_REQ[0] TCC_RW_REQ[0] TCC_MISS[1] TCC_READ[1] TCC_REQ[1] TCC_RW_REQ[1] TCC_MISS[2] TCC_READ[2] TCC_REQ[2] TCC_RW_REQ[2] TCC_MISS[3] TCC_READ[3] TCC_REQ[3] TCC_RW_REQ[3] TCC_MISS[4] TCC_READ[4] TCC_REQ[4] TCC_RW_REQ[4] TCC_MISS[5] TCC_READ[5] TCC_REQ[5] TCC_RW_REQ[5] TCC_MISS[6] TCC_READ[6] TCC_REQ[6] TCC_RW_REQ[6] TCC_MISS[7] TCC_READ[7] TCC_REQ[7] TCC_RW_REQ[7] TCC_MISS[8] TCC_READ[8] TCC_REQ[8] TCC_RW_REQ[8] TCC_MISS[9] TCC_READ[9] TCC_REQ[9] TCC_RW_REQ[9] TCC_MISS[10] TCC_READ[10] TCC_REQ[10] TCC_RW_REQ[10] TCC_MISS[11] TCC_READ[11] TCC_REQ[11] TCC_RW_REQ[11] TCC_MISS[12] TCC_READ[12] TCC_REQ[12] TCC_RW_REQ[12] TCC_MISS[13] TCC_READ[13] TCC_REQ[13] TCC_RW_REQ[13] TCC_MISS[14] TCC_READ[14] TCC_REQ[14] TCC_RW_REQ[14] TCC_MISS[15] TCC_READ[15] TCC_REQ[15] TCC_RW_REQ[15]
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  TCC_TAG_STALL[0] TCC_TOO_MANY_EA_WRREQS_STALL[0] TCC_WRITE[0] TCC_TAG_STALL[1] TCC_TOO_MANY_EA_WRREQS_STALL[1] TCC_WRITE[1] TCC_TAG_STALL[2] TCC_TOO_MANY_EA_WRREQS_STALL[2] TCC_WRITE[2] TCC_TAG_STALL[3] TCC_TOO_MANY_EA_WRREQS_STALL[3] TCC_WRITE[3] TCC_TAG_STALL[4] TCC_TOO_MANY_EA_WRREQS_STALL[4] TCC_WRITE[4] TCC_TAG_STALL[5] TCC_TOO_MANY_EA_WRREQS_STALL[5] TCC_WRITE[5] TCC_TAG_STALL[6] TCC_TOO_MANY_EA_WRREQS_STALL[6] TCC_WRITE[6] TCC_TAG_STALL[7] TCC_TOO_MANY_EA_WRREQS_STALL[7] TCC_WRITE[7] TCC_TAG_STALL[8] TCC_TOO_MANY_EA_WRREQS_STALL[8] TCC_WRITE[8] TCC_TAG_STALL[9] TCC_TOO_MANY_EA_WRREQS_STALL[9] TCC_WRITE[9] TCC_TAG_STALL[10] TCC_TOO_MANY_EA_WRREQS_STALL[10] TCC_WRITE[10] TCC_TAG_STALL[11] TCC_TOO_MANY_EA_WRREQS_STALL[11] TCC_WRITE[11] TCC_TAG_STALL[12] TCC_TOO_MANY_EA_WRREQS_STALL[12] TCC_WRITE[12] TCC_TAG_STALL[13] TCC_TOO_MANY_EA_WRREQS_STALL[13] TCC_WRITE[13] TCC_TAG_STALL[14] TCC_TOO_MANY_EA_WRREQS_STALL[14] TCC_WRITE[14] TCC_TAG_STALL[15] TCC_TOO_MANY_EA_WRREQS_STALL[15] TCC_WRITE[15]
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQ_INSTS_VALU_TRANS_F16 SQ_INSTS_VALU_ADD_F32 SQ_INSTS_VALU_MUL_F32 SQ_INSTS_VALU_FMA_F32 SQ_INSTS_VALU_TRANS_F32 SQ_INSTS_VALU_ADD_F64 SQ_INSTS_VALU_MUL_F64 SQ_INSTS_VALU_FMA_F64 TCP_VOLATILE_sum TCP_TOTAL_ACCESSES_sum TCP_TOTAL_READ_sum TCP_TOTAL_WRITE_sum TA_BUFFER_ATOMIC_WAVEFRONTS_sum TA_BUFFER_TOTAL_CYCLES_sum TD_ATOMIC_WAVEFRONT_sum TD_STORE_WAVEFRONT_sum SPI_RA_REQ_NO_ALLOC SPI_RA_REQ_NO_ALLOC_CSN CPC_CPC_STAT_STALL CPC_UTCL1_STALL_ON_TRANSLATION CPF_CPF_STAT_IDLE CPF_CPF_TCIU_IDLE TCC_REQ_sum TCC_STREAMING_REQ_sum TCC_HIT_sum TCC_MISS_sum
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQ_INSTS_VALU_TRANS_F64 SQ_INSTS_VALU_INT32 SQ_INSTS_VALU_INT64 SQ_INSTS_SMEM SQ_INSTS_FLAT SQ_INSTS_LDS SQ_INSTS_GDS SQ_INSTS_EXP_GDS TCP_TOTAL_ATOMIC_WITH_RET_sum TCP_TOTAL_ATOMIC_WITHOUT_RET_sum TCP_TOTAL_WRITEBACK_INVALIDATES_sum TCP_TOTAL_CACHE_ACCESSES_sum TA_BUFFER_COALESCED_READ_CYCLES_sum TA_BUFFER_COALESCED_WRITE_CYCLES_sum TD_COALESCABLE_WAVEFRONT_sum SPI_RA_RES_STALL_CSN SPI_RA_TMP_STALL_CSN CPC_CPC_UTCL2IU_BUSY CPC_CPC_UTCL2IU_IDLE CPF_CMP_UTCL1_STALL_ON_TRANSLATION TCC_READ_sum TCC_WRITE_sum TCC_ATOMIC_sum TCC_WRITEBACK_sum
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQ_INSTS_BRANCH SQ_INSTS_SENDMSG SQ_WAIT_ANY SQ_WAIT_INST_ANY SQ_ACTIVE_INST_ANY SQ_ACTIVE_INST_VMEM SQ_ACTIVE_INST_LDS SQ_ACTIVE_INST_VALU TCP_UTCL1_TRANSLATION_MISS_sum TCP_UTCL1_TRANSLATION_HIT_sum TCP_UTCL1_PERMISSION_MISS_sum TCP_UTCL1_REQUEST_sum TA_ADDR_STALLED_BY_TC_CYCLES_sum TA_TOTAL_WAVEFRONTS_sum SPI_RA_WAVE_SIMD_FULL_CSN SPI_RA_VGPR_SIMD_FULL_CSN CPC_CPC_UTCL2IU_STALL CPC_ME1_BUSY_FOR_PACKET_DECODE TCC_EA0_WRREQ_sum TCC_EA0_WRREQ_64B_sum TCC_EA0_WR_UNCACHED_32B_sum TCC_EA0_WRREQ_DRAM_sum
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQ_ACTIVE_INST_SCA SQ_ACTIVE_INST_EXP_GDS SQ_ACTIVE_INST_MISC SQ_ACTIVE_INST_FLAT SQ_INST_CYCLES_VMEM_WR SQ_INST_CYCLES_VMEM_RD SQ_INST_CYCLES_SMEM SQ_INST_CYCLES_SALU TCP_TCC_READ_REQ_sum TCP_TCC_WRITE_REQ_sum TCP_TCC_ATOMIC_WITH_RET_REQ_sum TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum TA_ADDR_STALLED_BY_TD_CYCLES_sum TA_DATA_STALLED_BY_TC_CYCLES_sum SPI_RA_SGPR_SIMD_FULL_CSN SPI_RA_LDS_CU_FULL_CSN CPC_ME1_DC0_SPI_BUSY TCC_EA0_RDREQ_sum TCC_EA0_RDREQ_32B_sum TCC_BUBBLE_sum TCC_EA0_RD_UNCACHED_32B_sum
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQ_THREAD_CYCLES_VALU SQ_IFETCH SQ_LDS_BANK_CONFLICT SQ_LDS_ADDR_CONFLICT SQ_LDS_UNALIGNED_STALL SQ_WAVES_EQ_64 SQ_WAVES_LT_64 SQ_WAVES_LT_48 TCP_TCC_NC_READ_REQ_sum TCP_TCC_NC_WRITE_REQ_sum TCP_TCC_NC_ATOMIC_REQ_sum TCP_TCC_UC_READ_REQ_sum TA_FLAT_WAVEFRONTS_sum TA_FLAT_READ_WAVEFRONTS_sum SPI_RA_BAR_CU_FULL_CSN SPI_RA_TGLIM_CU_FULL_CSN TCC_EA0_RDREQ_DRAM_sum TCC_TAG_STALL_sum TCC_NORMAL_WRITEBACK_sum TCC_ALL_TC_OP_WB_WRITEBACK_sum
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQ_WAVES_LT_32 SQ_WAVES_LT_16 SQ_ITEMS SQ_LDS_MEM_VIOLATIONS SQ_LDS_ATOMIC_RETURN SQ_LDS_IDX_ACTIVE SQ_WAVES_RESTORED SQ_WAVES_SAVED TCP_TCC_UC_WRITE_REQ_sum TCP_TCC_UC_ATOMIC_REQ_sum TCP_TCC_CC_READ_REQ_sum TCP_TCC_CC_WRITE_REQ_sum TA_FLAT_WRITE_WAVEFRONTS_sum TA_FLAT_ATOMIC_WAVEFRONTS_sum SPI_RA_WVLIM_STALL_CSN SPI_SWC_CSC_WR TCC_NORMAL_EVICT_sum TCC_ALL_TC_OP_INV_EVICT_sum TCC_TOO_MANY_EA_WRREQS_STALL_sum TCC_EA0_ATOMIC_sum
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQ_INSTS_SMEM_NORM SQ_INSTS_MFMA SQ_INSTS_VALU_MFMA_I8 SQ_INSTS_VALU_MFMA_F16 SQ_INSTS_VALU_MFMA_BF16 SQ_INSTS_VALU_MFMA_F32 SQ_INSTS_VALU_MFMA_F64 SQ_VALU_MFMA_BUSY_CYCLES TCP_TCC_CC_ATOMIC_REQ_sum TCP_TCC_RW_READ_REQ_sum TCP_TCC_RW_WRITE_REQ_sum TCP_TCC_RW_ATOMIC_REQ_sum SPI_VWC_CSC_WR SPI_RA_BULKY_CU_FULL_CSN TCC_EA0_RDREQ_LEVEL_sum TCC_EA0_WRREQ_LEVEL_sum TCC_EA0_ATOMIC_LEVEL_sum TCC_EA0_WRREQ_STALL_sum
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQ_INSTS_VALU_MFMA_MOPS_I8 SQ_INSTS_VALU_MFMA_MOPS_F16 SQ_INSTS_VALU_MFMA_MOPS_BF16 SQ_INSTS_VALU_MFMA_MOPS_F32 SQ_INSTS_VALU_MFMA_MOPS_F64 SQC_TC_INST_REQ SQC_TC_DATA_READ_REQ SQC_TC_DATA_WRITE_REQ TCP_PENDING_STALL_CYCLES_sum
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,4 @@
+Dispatch_ID,GPU_ID,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,Wave_Size,Kernel_Name,Correlation_ID,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_EA0_WRREQ_64B_sum,TCC_EA0_WRREQ_DRAM_sum,TCC_EA0_WRREQ_sum,TCC_EA0_WR_UNCACHED_32B_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_TRANSLATION_MISS_sum,Wave_Size_1,Correlation_ID_1,XCC_Index,TCC_EA0_WRREQ[0],TCC_EA0_WRREQ_64B[0],TCC_EA0_WRREQ_LEVEL[0],TCC_HIT[0],TCC_EA0_WRREQ[1],TCC_EA0_WRREQ_64B[1],TCC_EA0_WRREQ_LEVEL[1],TCC_HIT[1],TCC_EA0_WRREQ[2],TCC_EA0_WRREQ_64B[2],TCC_EA0_WRREQ_LEVEL[2],TCC_HIT[2],TCC_EA0_WRREQ[3],TCC_EA0_WRREQ_64B[3],TCC_EA0_WRREQ_LEVEL[3],TCC_HIT[3],TCC_EA0_WRREQ[4],TCC_EA0_WRREQ_64B[4],TCC_EA0_WRREQ_LEVEL[4],TCC_HIT[4],TCC_EA0_WRREQ[5],TCC_EA0_WRREQ_64B[5],TCC_EA0_WRREQ_LEVEL[5],TCC_HIT[5],TCC_EA0_WRREQ[6],TCC_EA0_WRREQ_64B[6],TCC_EA0_WRREQ_LEVEL[6],TCC_HIT[6],TCC_EA0_WRREQ[7],TCC_EA0_WRREQ_64B[7],TCC_EA0_WRREQ_LEVEL[7],TCC_HIT[7],TCC_EA0_WRREQ[8],TCC_EA0_WRREQ_64B[8],TCC_EA0_WRREQ_LEVEL[8],TCC_HIT[8],TCC_EA0_WRREQ[9],TCC_EA0_WRREQ_64B[9],TCC_EA0_WRREQ_LEVEL[9],TCC_HIT[9],TCC_EA0_WRREQ[10],TCC_EA0_WRREQ_64B[10],TCC_EA0_WRREQ_LEVEL[10],TCC_HIT[10],TCC_EA0_WRREQ[11],TCC_EA0_WRREQ_64B[11],TCC_EA0_WRREQ_LEVEL[11],TCC_HIT[11],TCC_EA0_WRREQ[12],TCC_EA0_WRREQ_64B[12],TCC_EA0_WRREQ_LEVEL[12],TCC_HIT[12],TCC_EA0_WRREQ[13],TCC_EA0_WRREQ_64B[13],TCC_EA0_WRREQ_LEVEL[13],TCC_HIT[13],TCC_EA0_WRREQ[14],TCC_EA0_WRREQ_64B[14],TCC_EA0_WRREQ_LEVEL[14],TCC_HIT[14],TCC_EA0_WRREQ[15],TCC_EA0_WRREQ_64B[15],TCC_EA0_WRREQ_LEVEL[15],TCC_HIT[15],TCC_EA0_WRREQ[16],TCC_EA0_WRREQ_64B[16],TCC_EA0_WRREQ_LEVEL[16],TCC_HIT[16],TCC_EA0_WRREQ[17],TCC_EA0_WRREQ_64B[17],TCC_EA0_WRREQ_LEVEL[17],TCC_HIT[17],TCC_EA0_WRREQ[18],TCC_EA0_WRREQ_64B[18],TCC_EA0_WRREQ_LEVEL[18],TCC_HIT[18],TCC_EA0_WRREQ[19],TCC_EA0_WRREQ_64B[19],TCC_EA0_WRREQ_LEVEL[19],TCC_HIT[19],TCC_EA0_WRREQ[20],TCC_EA0_WRREQ_64B[20],TCC_EA0_WRREQ_LEVEL[20],TCC_HIT[20],TCC_EA0_WRREQ[21],TCC_EA0_WRREQ_64B[21],TCC_EA0_WRREQ_LEVEL[21],TCC_HIT[21],TCC_EA0_WRREQ[22],TCC_EA0_WRREQ_64B[22],TCC_EA0_WRREQ_LEVEL[22],TCC_HIT[22],TCC_EA0_WRREQ[23],TCC_EA0_WRREQ_64B[23],TCC_EA0_WRREQ_LEVEL[23],TCC_HIT[23],TCC_EA0_WRREQ[24],TCC_EA0_WRREQ_64B[24],TCC_EA0_WRREQ_LEVEL[24],TCC_HIT[24],TCC_EA0_WRREQ[25],TCC_EA0_WRREQ_64B[25],TCC_EA0_WRREQ_LEVEL[25],TCC_HIT[25],TCC_EA0_WRREQ[26],TCC_EA0_WRREQ_64B[26],TCC_EA0_WRREQ_LEVEL[26],TCC_HIT[26],TCC_EA0_WRREQ[27],TCC_EA0_WRREQ_64B[27],TCC_EA0_WRREQ_LEVEL[27],TCC_HIT[27],TCC_EA0_WRREQ[28],TCC_EA0_WRREQ_64B[28],TCC_EA0_WRREQ_LEVEL[28],TCC_HIT[28],TCC_EA0_WRREQ[29],TCC_EA0_WRREQ_64B[29],TCC_EA0_WRREQ_LEVEL[29],TCC_HIT[29],TCC_EA0_WRREQ[30],TCC_EA0_WRREQ_64B[30],TCC_EA0_WRREQ_LEVEL[30],TCC_HIT[30],TCC_EA0_WRREQ[31],TCC_EA0_WRREQ_64B[31],TCC_EA0_WRREQ_LEVEL[31],TCC_HIT[31],TCC_EA0_WRREQ[32],TCC_EA0_WRREQ_64B[32],TCC_EA0_WRREQ_LEVEL[32],TCC_HIT[32],TCC_EA0_WRREQ[33],TCC_EA0_WRREQ_64B[33],TCC_EA0_WRREQ_LEVEL[33],TCC_HIT[33],TCC_EA0_WRREQ[34],TCC_EA0_WRREQ_64B[34],TCC_EA0_WRREQ_LEVEL[34],TCC_HIT[34],TCC_EA0_WRREQ[35],TCC_EA0_WRREQ_64B[35],TCC_EA0_WRREQ_LEVEL[35],TCC_HIT[35],TCC_EA0_WRREQ[36],TCC_EA0_WRREQ_64B[36],TCC_EA0_WRREQ_LEVEL[36],TCC_HIT[36],TCC_EA0_WRREQ[37],TCC_EA0_WRREQ_64B[37],TCC_EA0_WRREQ_LEVEL[37],TCC_HIT[37],TCC_EA0_WRREQ[38],TCC_EA0_WRREQ_64B[38],TCC_EA0_WRREQ_LEVEL[38],TCC_HIT[38],TCC_EA0_WRREQ[39],TCC_EA0_WRREQ_64B[39],TCC_EA0_WRREQ_LEVEL[39],TCC_HIT[39],TCC_EA0_WRREQ[40],TCC_EA0_WRREQ_64B[40],TCC_EA0_WRREQ_LEVEL[40],TCC_HIT[40],TCC_EA0_WRREQ[41],TCC_EA0_WRREQ_64B[41],TCC_EA0_WRREQ_LEVEL[41],TCC_HIT[41],TCC_EA0_WRREQ[42],TCC_EA0_WRREQ_64B[42],TCC_EA0_WRREQ_LEVEL[42],TCC_HIT[42],TCC_EA0_WRREQ[43],TCC_EA0_WRREQ_64B[43],TCC_EA0_WRREQ_LEVEL[43],TCC_HIT[43],TCC_EA0_WRREQ[44],TCC_EA0_WRREQ_64B[44],TCC_EA0_WRREQ_LEVEL[44],TCC_HIT[44],TCC_EA0_WRREQ[45],TCC_EA0_WRREQ_64B[45],TCC_EA0_WRREQ_LEVEL[45],TCC_HIT[45],TCC_EA0_WRREQ[46],TCC_EA0_WRREQ_64B[46],TCC_EA0_WRREQ_LEVEL[46],TCC_HIT[46],TCC_EA0_WRREQ[47],TCC_EA0_WRREQ_64B[47],TCC_EA0_WRREQ_LEVEL[47],TCC_HIT[47],TCC_EA0_WRREQ[48],TCC_EA0_WRREQ_64B[48],TCC_EA0_WRREQ_LEVEL[48],TCC_HIT[48],TCC_EA0_WRREQ[49],TCC_EA0_WRREQ_64B[49],TCC_EA0_WRREQ_LEVEL[49],TCC_HIT[49],TCC_EA0_WRREQ[50],TCC_EA0_WRREQ_64B[50],TCC_EA0_WRREQ_LEVEL[50],TCC_HIT[50],TCC_EA0_WRREQ[51],TCC_EA0_WRREQ_64B[51],TCC_EA0_WRREQ_LEVEL[51],TCC_HIT[51],TCC_EA0_WRREQ[52],TCC_EA0_WRREQ_64B[52],TCC_EA0_WRREQ_LEVEL[52],TCC_HIT[52],TCC_EA0_WRREQ[53],TCC_EA0_WRREQ_64B[53],TCC_EA0_WRREQ_LEVEL[53],TCC_HIT[53],TCC_EA0_WRREQ[54],TCC_EA0_WRREQ_64B[54],TCC_EA0_WRREQ_LEVEL[54],TCC_HIT[54],TCC_EA0_WRREQ[55],TCC_EA0_WRREQ_64B[55],TCC_EA0_WRREQ_LEVEL[55],TCC_HIT[55],TCC_EA0_WRREQ[56],TCC_EA0_WRREQ_64B[56],TCC_EA0_WRREQ_LEVEL[56],TCC_HIT[56],TCC_EA0_WRREQ[57Linha truncada
+0,11995,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",0,16384.0,16384.0,12334507.0,1067434.0,278528.0,0.0,0.0,98304.0,381995.0,0.0,0.0,437520.0,125868.0,32768.0,131072.0,131072.0,131072.0,0.0,0.0,524288.0,453233.0,1820.0,64,0,0,1368.0,1368.0,546411.0,684.0,1368.0,1368.0,565023.0,742.0,1368.0,1368.0,549661.0,684.0,1368.0,1368.0,561715.0,684.0,1368.0,1368.0,551798.0,684.0,1368.0,1368.0,555107.0,684.0,1368.0,1368.0,564643.0,684.0,1368.0,1368.0,558600.0,684.0,1364.0,1364.0,546949.0,682.0,1364.0,1364.0,554556.0,682.0,1364.0,1364.0,560534.0,682.0,1364.0,1364.0,561856.0,701.0,1364.0,1364.0,555849.0,682.0,1364.0,1364.0,559714.0,682.0,1364.0,1364.0,571523.0,682.0,1364.0,1364.0,567575.0,682.0,1368.0,1368.0,537981.0,684.0,1368.0,1368.0,548436.0,684.0,1368.0,1368.0,559503.0,684.0,1368.0,1368.0,557232.0,703.0,1368.0,1368.0,551999.0,684.0,1368.0,1368.0,553807.0,684.0,1368.0,1368.0,565949.0,684.0,1368.0,1368.0,559748.0,684.0,1364.0,1364.0,548720.0,682.0,1364.0,1364.0,560367.0,740.0,1364.0,1364.0,557628.0,682.0,1364.0,1364.0,568507.0,682.0,1364.0,1364.0,558472.0,682.0,1364.0,1364.0,560630.0,682.0,1364.0,1364.0,570028.0,682.0,1364.0,1364.0,562090.0,682.0,1364.0,1364.0,556285.0,682.0,1364.0,1364.0,565792.0,682.0,1364.0,1364.0,575044.0,682.0,1364.0,1364.0,572799.0,701.0,1364.0,1364.0,568191.0,682.0,1364.0,1364.0,573080.0,682.0,1364.0,1364.0,583848.0,682.0,1364.0,1364.0,580923.0,682.0,1368.0,1368.0,544729.0,684.0,1368.0,1368.0,557050.0,742.0,1368.0,1368.0,557036.0,684.0,1368.0,1368.0,564447.0,684.0,1368.0,1368.0,559356.0,684.0,1368.0,1368.0,564086.0,684.0,1368.0,1368.0,567295.0,684.0,1368.0,1368.0,563169.0,684.0,1364.0,1364.0,550477.0,682.0,1364.0,1364.0,562645.0,740.0,1364.0,1364.0,559547.0,682.0,1364.0,1364.0,567003.0,682.0,1364.0,1364.0,560377.0,682.0,1364.0,1364.0,562802.0,682.0,1364.0,1364.0,571882.0,682.0,1364.0,1364.0,567060.0,682.0,1368.0,1368.0,548612.0,684.0,1368.0,1368.0,556374.0,684.0,1368.0,1368.0,561216.0,684.0,1368.0,1368.0,560870.0,703.0,1368.0,1368.0,558265.0,684.0,1368.0,1368.0,562714.0,684.0,1368.0,1368.0,570020.0,684.0,1368.0,1368.0,566027.0,684.0,1368.0,1368.0,550134.0,684.0,1368.0,1368.0,563310.0,684.0,1368.0,1368.0,559008.0,684.0,1368.0,1368.0,565849.0,703.0,1368.0,1368.0,558385.0,684.0,1368.0,1368.0,563287.0,684.0,1368.0,1368.0,570210.0,684.0,1368.0,1368.0,565153.0,684.0,1360.0,1360.0,544448.0,680.0,1360.0,1360.0,551888.0,738.0,1360.0,1360.0,566336.0,680.0,1360.0,1360.0,564671.0,680.0,1360.0,1360.0,555074.0,680.0,1360.0,1360.0,559253.0,680.0,1360.0,1360.0,574939.0,680.0,1360.0,1360.0,571252.0,680.0,1368.0,1368.0,552807.0,684.0,1368.0,1368.0,559337.0,742.0,1368.0,1368.0,567423.0,684.0,1368.0,1368.0,567409.0,684.0,1368.0,1368.0,559366.0,684.0,1368.0,1368.0,564285.0,684.0,1368.0,1368.0,578677.0,684.0,1368.0,1368.0,573115.0,684.0,1360.0,1360.0,545268.0,680.0,1360.0,1360.0,558534.0,680.0,1360.0,1360.0,552590.0,680.0,1360.0,1360.0,560550.0,699.0,1360.0,1360.0,550226.0,680.0,1360.0,1360.0,555836.0,680.0,1360.0,1360.0,561624.0,680.0,1360.0,1360.0,557000.0,680.0,64,0,6291456.0,65536.0,0.0,0.0,0.0,16384.0,0.0,0.0,0.0,0.0,16384.0,32768.0,49332.0,65596.0,16204.0,83742.0,0.0,0.0,0.0,0.0,64,0,0,783.0,0.0,1360.0,403.0,0.0,1360.0,945.0,0.0,1360.0,217.0,0.0,1360.0,347.0,0.0,1360.0,352.0,0.0,1360.0,265.0,0.0,1360.0,246.0,0.0,1360.0,493.0,0.0,1368.0,608.0,0.0,1368.0,810.0,0.0,1368.0,272.0,0.0,1368.0,224.0,0.0,1368.0,534.0,0.0,1368.0,659.0,0.0,1368.0,614.0,0.0,1368.0,540.0,0.0,1360.0,602.0,0.0,1360.0,625.0,0.0,1360.0,478.0,0.0,1360.0,192.0,0.0,1360.0,561.0,0.0,1360.0,562.0,0.0,1360.0,514.0,0.0,1360.0,506.0,0.0,1368.0,316.0,0.0,1368.0,598.0,0.0,1368.0,213.0,0.0,1368.0,129.0,0.0,1368.0,120.0,0.0,1368.0,102.0,0.0,1368.0,92.0,0.0,1368.0,961.0,0.0,1364.0,462.0,0.0,1364.0,876.0,0.0,1364.0,281.0,0.0,1364.0,175.0,0.0,1364.0,724.0,0.0,1364.0,600.0,0.0,1364.0,606.0,0.0,1364.0,905.0,0.0,1368.0,465.0,0.0,1368.0,959.0,0.0,1368.0,244.0,0.0,1368.0,218.0,0.0,1368.0,212.0,0.0,1368.0,288.0,0.0,1368.0,290.0,0.0,1368.0,774.0,0.0,1364.0,361.0,0.0,1364.0,856.0,0.0,1364.0,133.0,0.0,1364.0,134.0,0.0,1364.0,125.0,0.0,1364.0,99.0,0.0,1364.0,94.0,0.0,1364.0,999.0,0.0,1368.0,647.0,0.0,1368.0,851.0,0.0,1368.0,438.0,0.0,1368.0,228.0,0.0,1368.0,908.0,0.0,1368.0,646.0,0.0,1368.0,657.0,0.0,1368.0,564.0,0.0,1364.0,589.0,0.0,1364.0,530.0,0.0,1364.0,290.0,0.0,1364.0,129.0,0.0,1364.0,627.0,0.0,1364.0,425.0,0.0,1364.0,371.0,0.0,1364.0,682.0,0.0,1368.0,457.0,0.0,1368.0,659.0,0.0,1368.0,197.0,0.0,1368.0,152.0,0.0,1368.0,149.0,0.0,1368.0,242.0,0.0,1368.0,229.0,0.0,1368.0,728.0,0.0,1364.0,411.0,0.0,1364.0,736.0,0.0,1364.0,208.0,0.0,1364.0,152.0,0.0,1364.0,142.0,0.0,1364.0,84.0,0.0,1364.0,75.0,0.0,1364.0,736.0,0.0,1368.0,732.0,0.0,1368.0,714.0,0.0,1368.0,400.0,0.0,1368.0,158.0,0.0,1368.0,667.0,0.0,1368.0,570.0,0.0,1368.0,539.0,0.0,1368.0,64,0,0.0,49152.0,32768.0,65536.0,32768.0,0.0,0.0,0.0,13436.0,0.0,510.0,593975.0,78.0,0.0,0.0,0.0,66066.0,65536.0,131072.0,0.0,0.0,524288.0,228.0,0.0,64,0,0.0,0.0,1048576.0,0.0,0.0,0.0,0.0,0.0,0.0,3Linha truncada
+1,11995,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",0,16384.0,16384.0,9891523.0,854215.0,278528.0,0.0,0.0,98304.0,241392.0,0.0,0.0,494319.0,113802.0,32768.0,131072.0,131072.0,131072.0,0.0,0.0,524288.0,453517.0,1824.0,64,0,0,1364.0,1364.0,559058.0,682.0,1364.0,1364.0,570584.0,682.0,1364.0,1364.0,575819.0,682.0,1364.0,1364.0,579888.0,682.0,1364.0,1364.0,569649.0,682.0,1364.0,1364.0,574582.0,682.0,1364.0,1364.0,589472.0,682.0,1364.0,1364.0,580098.0,682.0,1368.0,1368.0,594267.0,684.0,1368.0,1368.0,587697.0,684.0,1368.0,1368.0,595652.0,684.0,1368.0,1368.0,603662.0,703.0,1368.0,1368.0,591710.0,684.0,1368.0,1368.0,594223.0,684.0,1368.0,1368.0,611007.0,684.0,1368.0,1368.0,606938.0,684.0,1364.0,1364.0,572451.0,682.0,1364.0,1364.0,576891.0,682.0,1364.0,1364.0,589652.0,682.0,1364.0,1364.0,585999.0,701.0,1364.0,1364.0,577921.0,682.0,1364.0,1364.0,580875.0,682.0,1364.0,1364.0,598312.0,682.0,1364.0,1364.0,597061.0,682.0,1368.0,1368.0,568602.0,684.0,1368.0,1368.0,580399.0,684.0,1368.0,1368.0,577413.0,684.0,1368.0,1368.0,586002.0,684.0,1368.0,1368.0,574290.0,684.0,1368.0,1368.0,578080.0,684.0,1368.0,1368.0,582392.0,684.0,1368.0,1368.0,576673.0,684.0,1368.0,1368.0,563564.0,684.0,1368.0,1368.0,583022.0,684.0,1368.0,1368.0,591235.0,684.0,1368.0,1368.0,583196.0,703.0,1368.0,1368.0,566974.0,684.0,1368.0,1368.0,570573.0,684.0,1368.0,1368.0,581883.0,684.0,1368.0,1368.0,576232.0,684.0,1364.0,1364.0,565589.0,682.0,1364.0,1364.0,579378.0,682.0,1364.0,1364.0,579627.0,682.0,1364.0,1364.0,590073.0,682.0,1364.0,1364.0,567227.0,682.0,1364.0,1364.0,575899.0,682.0,1364.0,1364.0,578746.0,682.0,1364.0,1364.0,572859.0,682.0,1360.0,1360.0,565273.0,680.0,1360.0,1360.0,576284.0,680.0,1360.0,1360.0,573126.0,680.0,1360.0,1360.0,582623.0,680.0,1360.0,1360.0,567814.0,680.0,1360.0,1360.0,572221.0,680.0,1360.0,1360.0,585459.0,680.0,1360.0,1360.0,579973.0,680.0,1368.0,1368.0,573007.0,684.0,1368.0,1368.0,584104.0,684.0,1368.0,1368.0,595109.0,684.0,1368.0,1368.0,587685.0,703.0,1368.0,1368.0,580520.0,684.0,1368.0,1368.0,592767.0,684.0,1368.0,1368.0,593901.0,684.0,1368.0,1368.0,591567.0,684.0,1360.0,1360.0,554972.0,680.0,1360.0,1360.0,568012.0,680.0,1360.0,1360.0,565630.0,680.0,1360.0,1360.0,571039.0,699.0,1360.0,1360.0,567990.0,680.0,1360.0,1360.0,570194.0,680.0,1360.0,1360.0,584357.0,680.0,1360.0,1360.0,577352.0,680.0,1368.0,1368.0,574343.0,684.0,1368.0,1368.0,586682.0,684.0,1368.0,1368.0,594030.0,684.0,1368.0,1368.0,590040.0,684.0,1368.0,1368.0,581848.0,684.0,1368.0,1368.0,586105.0,684.0,1368.0,1368.0,597918.0,684.0,1368.0,1368.0,587677.0,684.0,1368.0,1368.0,582109.0,684.0,1368.0,1368.0,590535.0,684.0,1368.0,1368.0,606860.0,684.0,1368.0,1368.0,605048.0,684.0,1368.0,1368.0,591644.0,684.0,1368.0,1368.0,595070.0,684.0,1368.0,1368.0,609617.0,684.0,1368.0,1368.0,606026.0,684.0,1364.0,1364.0,553271.0,682.0,1364.0,1364.0,565845.0,682.0,1364.0,1364.0,564011.0,682.0,1364.0,1364.0,568726.0,701.0,1364.0,1364.0,562808.0,682.0,1364.0,1364.0,567413.0,682.0,1364.0,1364.0,570808.0,682.0,1364.0,1364.0,565649.0,682.0,64,0,6291456.0,65536.0,0.0,0.0,0.0,16384.0,0.0,0.0,0.0,0.0,16384.0,32768.0,48701.0,65608.0,16835.0,106904.0,0.0,0.0,0.0,0.0,64,0,0,480.0,0.0,1368.0,450.0,0.0,1368.0,471.0,0.0,1368.0,513.0,0.0,1368.0,524.0,0.0,1368.0,443.0,0.0,1368.0,437.0,0.0,1368.0,475.0,0.0,1368.0,426.0,0.0,1360.0,435.0,0.0,1360.0,457.0,0.0,1360.0,396.0,0.0,1360.0,354.0,0.0,1360.0,356.0,0.0,1360.0,417.0,0.0,1360.0,393.0,0.0,1360.0,179.0,0.0,1364.0,190.0,0.0,1364.0,301.0,0.0,1364.0,235.0,0.0,1364.0,170.0,0.0,1364.0,156.0,0.0,1364.0,171.0,0.0,1364.0,175.0,0.0,1364.0,641.0,0.0,1368.0,665.0,0.0,1368.0,607.0,0.0,1368.0,636.0,0.0,1368.0,640.0,0.0,1368.0,689.0,0.0,1368.0,636.0,0.0,1368.0,679.0,0.0,1368.0,562.0,0.0,1368.0,521.0,0.0,1368.0,575.0,0.0,1368.0,520.0,0.0,1368.0,389.0,0.0,1368.0,470.0,0.0,1368.0,516.0,0.0,1368.0,494.0,0.0,1368.0,369.0,0.0,1364.0,386.0,0.0,1364.0,308.0,0.0,1364.0,335.0,0.0,1364.0,166.0,0.0,1364.0,253.0,0.0,1364.0,274.0,0.0,1364.0,205.0,0.0,1364.0,514.0,0.0,1368.0,523.0,0.0,1368.0,517.0,0.0,1368.0,519.0,0.0,1368.0,456.0,0.0,1368.0,353.0,0.0,1368.0,412.0,0.0,1368.0,499.0,0.0,1368.0,682.0,0.0,1364.0,662.0,0.0,1364.0,658.0,0.0,1364.0,614.0,0.0,1364.0,605.0,0.0,1364.0,608.0,0.0,1364.0,724.0,0.0,1364.0,732.0,0.0,1364.0,523.0,0.0,1368.0,506.0,0.0,1368.0,488.0,0.0,1368.0,439.0,0.0,1368.0,470.0,0.0,1368.0,425.0,0.0,1368.0,537.0,0.0,1368.0,501.0,0.0,1368.0,753.0,0.0,1364.0,749.0,0.0,1364.0,711.0,0.0,1364.0,661.0,0.0,1364.0,635.0,0.0,1364.0,597.0,0.0,1364.0,727.0,0.0,1364.0,648.0,0.0,1364.0,523.0,0.0,1360.0,547.0,0.0,1360.0,523.0,0.0,1360.0,502.0,0.0,1360.0,391.0,0.0,1360.0,375.0,0.0,1360.0,319.0,0.0,1360.0,405.0,0.0,1360.0,399.0,0.0,1368.0,367.0,0.0,1368.0,440.0,0.0,1368.0,317.0,0.0,1368.0,395.0,0.0,1368.0,351.0,0.0,1368.0,470.0,0.0,1368.0,427.0,0.0,1368.0,64,0,0.0,49152.0,32768.0,65536.0,32768.0,0.0,0.0,0.0,8414.0,0.0,7557.0,575460.0,944.0,0.0,0.0,0.0,65730.0,65536.0,131072.0,0.0,0.0,524288.0,228.0,0.0,64,0,0.0,0.0,1048576.0,0.0,0.0,0.0,0.0,0.0,Linha truncada
+2,11995,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",0,16384.0,16384.0,9912781.0,854942.0,278528.0,0.0,0.0,98304.0,245973.0,0.0,0.0,448559.0,112225.0,32768.0,131072.0,131072.0,131072.0,0.0,0.0,524288.0,453372.0,1824.0,64,0,0,1368.0,1368.0,555436.0,684.0,1368.0,1368.0,567265.0,684.0,1368.0,1368.0,560386.0,684.0,1368.0,1368.0,561284.0,684.0,1368.0,1368.0,556189.0,684.0,1368.0,1368.0,561173.0,684.0,1368.0,1368.0,570363.0,684.0,1368.0,1368.0,565070.0,684.0,1364.0,1364.0,560646.0,682.0,1364.0,1364.0,561590.0,682.0,1364.0,1364.0,576921.0,682.0,1364.0,1364.0,573932.0,701.0,1364.0,1364.0,569721.0,682.0,1364.0,1364.0,576293.0,682.0,1364.0,1364.0,583554.0,682.0,1364.0,1364.0,577868.0,682.0,1368.0,1368.0,551001.0,684.0,1368.0,1368.0,558312.0,684.0,1368.0,1368.0,570733.0,684.0,1368.0,1368.0,570395.0,703.0,1368.0,1368.0,560372.0,684.0,1368.0,1368.0,562201.0,684.0,1368.0,1368.0,576549.0,684.0,1368.0,1368.0,573576.0,684.0,1364.0,1364.0,570584.0,682.0,1364.0,1364.0,572518.0,682.0,1364.0,1364.0,569085.0,682.0,1364.0,1364.0,578140.0,682.0,1364.0,1364.0,572034.0,682.0,1364.0,1364.0,578785.0,682.0,1364.0,1364.0,583424.0,682.0,1364.0,1364.0,570500.0,682.0,1368.0,1368.0,572641.0,684.0,1368.0,1368.0,592140.0,684.0,1368.0,1368.0,599966.0,684.0,1368.0,1368.0,594696.0,703.0,1368.0,1368.0,582409.0,684.0,1368.0,1368.0,584849.0,684.0,1368.0,1368.0,599403.0,684.0,1368.0,1368.0,600204.0,684.0,1360.0,1360.0,561415.0,680.0,1360.0,1360.0,575437.0,680.0,1360.0,1360.0,572141.0,680.0,1360.0,1360.0,579496.0,680.0,1360.0,1360.0,571584.0,680.0,1360.0,1360.0,574839.0,680.0,1360.0,1360.0,584565.0,680.0,1360.0,1360.0,578145.0,680.0,1368.0,1368.0,569424.0,684.0,1368.0,1368.0,579030.0,684.0,1368.0,1368.0,582260.0,684.0,1368.0,1368.0,591055.0,684.0,1368.0,1368.0,577424.0,684.0,1368.0,1368.0,581982.0,684.0,1368.0,1368.0,585477.0,684.0,1368.0,1368.0,585117.0,684.0,1360.0,1360.0,563411.0,680.0,1360.0,1360.0,575068.0,680.0,1360.0,1360.0,588677.0,680.0,1360.0,1360.0,589490.0,699.0,1360.0,1360.0,576967.0,680.0,1360.0,1360.0,579296.0,680.0,1360.0,1360.0,589264.0,680.0,1360.0,1360.0,586166.0,680.0,1364.0,1364.0,546921.0,682.0,1364.0,1364.0,562589.0,682.0,1364.0,1364.0,556266.0,682.0,1364.0,1364.0,563258.0,701.0,1364.0,1364.0,545480.0,682.0,1364.0,1364.0,552008.0,682.0,1364.0,1364.0,565392.0,682.0,1364.0,1364.0,563276.0,682.0,1368.0,1368.0,571498.0,684.0,1368.0,1368.0,580987.0,684.0,1368.0,1368.0,590187.0,684.0,1368.0,1368.0,591029.0,684.0,1368.0,1368.0,592817.0,684.0,1368.0,1368.0,593497.0,684.0,1368.0,1368.0,604396.0,684.0,1368.0,1368.0,597966.0,684.0,1364.0,1364.0,552394.0,682.0,1364.0,1364.0,559422.0,682.0,1364.0,1364.0,558820.0,682.0,1364.0,1364.0,572744.0,682.0,1364.0,1364.0,560948.0,682.0,1364.0,1364.0,562010.0,682.0,1364.0,1364.0,570358.0,682.0,1364.0,1364.0,569899.0,682.0,1368.0,1368.0,574271.0,684.0,1368.0,1368.0,587681.0,684.0,1368.0,1368.0,585280.0,684.0,1368.0,1368.0,592150.0,703.0,1368.0,1368.0,584394.0,684.0,1368.0,1368.0,589888.0,684.0,1368.0,1368.0,593778.0,684.0,1368.0,1368.0,591259.0,684.0,64,0,6291456.0,65536.0,0.0,0.0,0.0,16384.0,0.0,0.0,0.0,0.0,16384.0,32768.0,48740.0,65618.0,16796.0,109209.0,0.0,0.0,0.0,0.0,64,0,0,591.0,0.0,1368.0,544.0,0.0,1368.0,651.0,0.0,1368.0,649.0,0.0,1368.0,558.0,0.0,1368.0,522.0,0.0,1368.0,605.0,0.0,1368.0,555.0,0.0,1368.0,133.0,0.0,1364.0,153.0,0.0,1364.0,248.0,0.0,1364.0,216.0,0.0,1364.0,247.0,0.0,1364.0,235.0,0.0,1364.0,211.0,0.0,1364.0,197.0,0.0,1364.0,931.0,0.0,1368.0,957.0,0.0,1368.0,899.0,0.0,1368.0,949.0,0.0,1368.0,1090.0,0.0,1368.0,1062.0,0.0,1368.0,890.0,0.0,1368.0,968.0,0.0,1368.0,763.0,0.0,1364.0,756.0,0.0,1364.0,735.0,0.0,1364.0,735.0,0.0,1364.0,674.0,0.0,1364.0,653.0,0.0,1364.0,757.0,0.0,1364.0,743.0,0.0,1364.0,1220.0,0.0,1364.0,1214.0,0.0,1364.0,1307.0,0.0,1364.0,1277.0,0.0,1364.0,1386.0,0.0,1364.0,1402.0,0.0,1364.0,1260.0,0.0,1364.0,1240.0,0.0,1364.0,937.0,0.0,1368.0,951.0,0.0,1368.0,1014.0,0.0,1368.0,942.0,0.0,1368.0,850.0,0.0,1368.0,857.0,0.0,1368.0,917.0,0.0,1368.0,908.0,0.0,1368.0,1221.0,0.0,1364.0,1223.0,0.0,1364.0,1190.0,0.0,1364.0,1253.0,0.0,1364.0,1217.0,0.0,1364.0,1201.0,0.0,1364.0,1302.0,0.0,1364.0,1340.0,0.0,1364.0,931.0,0.0,1368.0,917.0,0.0,1368.0,973.0,0.0,1368.0,939.0,0.0,1368.0,971.0,0.0,1368.0,918.0,0.0,1368.0,965.0,0.0,1368.0,985.0,0.0,1368.0,655.0,0.0,1368.0,604.0,0.0,1368.0,636.0,0.0,1368.0,516.0,0.0,1368.0,537.0,0.0,1368.0,526.0,0.0,1368.0,542.0,0.0,1368.0,540.0,0.0,1368.0,592.0,0.0,1360.0,606.0,0.0,1360.0,594.0,0.0,1360.0,595.0,0.0,1360.0,616.0,0.0,1360.0,605.0,0.0,1360.0,509.0,0.0,1360.0,498.0,0.0,1360.0,527.0,0.0,1368.0,524.0,0.0,1368.0,456.0,0.0,1368.0,462.0,0.0,1368.0,438.0,0.0,1368.0,405.0,0.0,1368.0,398.0,0.0,1368.0,456.0,0.0,1368.0,401.0,0.0,1360.0,268.0,0.0,1360.0,434.0,0.0,1360.0,272.0,0.0,1360.0,267.0,0.0,1360.0,264.0,0.0,1360.0,295.0,0.0,1360.0,294.0,0.0,1360.0,64,0,0.0,49152.0,32768.0,65536.0,32768.0,0.0,0.0,0.0,8237.0,0.0,5411.0,601250.0,0.0,0.0,0.0,0.0,65733.0,65536.0,131072.0,0.0,0.0,524288.0,228.0,0.0,64,0,0.0,0.0,1048576.0,0.0Linha truncada
@@ -0,0 +1,2 @@
+workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd
+device_filter,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Wed 29 May 2024 01:39:25 PM  (CDT),2,sh5-1w300-rg3-3,AMD Instinct MI300A Accelerator,"American Megatrends International, LLC.RMO1002DS",Ubuntu 22.04.2 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,131174852,,6.1.2-110,N/A,SPX,NPS1,MI300A_A1,gfx942,32,24576,228,4,24,64,1024,32,2100,1300,2100,1300,96,32,120,4,5324.8,6
@@ -0,0 +1,4 @@
+Dispatch_ID,GPU_ID,Queue_ID,PID,TID,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,Wave_Size,Kernel_Name,Start_Timestamp,End_Timestamp,Correlation_ID
+1,11995,1,148592,148592,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",73843971992178,73843971999909,0
+2,11995,1,148592,148592,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",73843972017897,73843972024226,0
+3,11995,1,148592,148592,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",73843972039650,73843972045859,0
@@ -0,0 +1,4 @@
+Dispatch_ID,GPU_ID,Queue_ID,PID,TID,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,Wave_Size,Kernel_Name,Start_Timestamp,End_Timestamp,Correlation_ID,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES
+0,60633,1,966829,966829,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",716380685145736,716380685161855,0,423448.0,423448.0,16384.0,65536.0,35074.0,2819140.0
+1,60633,1,966829,966829,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",716380685184013,716380685197573,0,431311.0,431311.0,16384.0,65536.0,13102.0,1048576.0
+2,60633,1,966829,966829,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",716380685217852,716380685231332,0,381273.0,381273.0,16384.0,65536.0,13173.0,1048580.0
@@ -0,0 +1,4 @@
+Dispatch_ID,GPU_ID,Queue_ID,PID,TID,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,Wave_Size,Kernel_Name,Start_Timestamp,End_Timestamp,Correlation_ID,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES
+0,60633,1,966840,966840,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",716380685145736,716380685161855,0,0.0,0.0,0.0
+1,60633,1,966840,966840,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",716380685184013,716380685197573,0,0.0,0.0,0.0
+2,60633,1,966840,966840,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",716380685217852,716380685231332,0,0.0,0.0,0.0
@@ -0,0 +1,4 @@
+Dispatch_ID,GPU_ID,Queue_ID,PID,TID,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,Wave_Size,Kernel_Name,Start_Timestamp,End_Timestamp,Correlation_ID,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES
+0,60633,1,966851,966851,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",716380685145736,716380685161855,0,65536.0,3552914.0,284244392.0
+1,60633,1,966851,966851,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",716380685184013,716380685197573,0,65536.0,3754770.0,300333168.0
+2,60633,1,966851,966851,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",716380685217852,716380685231332,0,65536.0,3553382.0,284188504.0
@@ -0,0 +1,4 @@
+Dispatch_ID,GPU_ID,Queue_ID,PID,TID,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,Wave_Size,Kernel_Name,Start_Timestamp,End_Timestamp,Correlation_ID,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES
+0,60633,1,966862,966862,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",716380685145736,716380685161855,0,32768.0,514988.0,41193032.0
+1,60633,1,966862,966862,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",716380685184013,716380685197573,0,32768.0,388588.0,31078292.0
+2,60633,1,966862,966862,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",716380685217852,716380685231332,0,32768.0,387452.0,30980248.0
@@ -0,0 +1,4 @@
+Dispatch_ID,GPU_ID,Queue_ID,PID,TID,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,Wave_Size,Kernel_Name,Start_Timestamp,End_Timestamp,Correlation_ID,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES
+0,60633,1,966874,966874,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",716380685145736,716380685161855,0,453185.0,453185.0,261839.0,1812740.0,16384.0,35223316.0,578033.0,0.0,141236700.0
+1,60633,1,966874,966874,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",716380685184013,716380685197573,0,353470.0,353470.0,174815.0,1413880.0,16384.0,31712257.0,507967.0,0.0,127205848.0
+2,60633,1,966874,966874,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",716380685217852,716380685231332,0,374628.0,374628.0,200237.0,1498512.0,16384.0,30945661.0,514530.0,0.0,124133364.0
@@ -0,0 +1,157 @@
+Omniperf version: 2.0.0
+Profiler choice: rocprofv2
+Path: /home/colramos/omniperf/tests/workloads/device_filter/MI300X_A1
+Target: MI300X_A1
+Command: ./tests/vcopy -n 1048576 -b 256 -i 3
+Kernel Selection: None
+Dispatch Selection: None
+Hardware Blocks: All
+
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Collecting Performance Counters
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+[profiling] Current input file: tests/workloads/device_filter/MI300X_A1/perfmon/SQ_IFETCH_LEVEL.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - GRBM_COUNT
+   |-> [/opt/rocm/bin/rocprofv2] - GRBM_GUI_ACTIVE
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_WAVES
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_IFETCH
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_IFETCH_LEVEL
+[profiling] Current input file: tests/workloads/device_filter/MI300X_A1/perfmon/SQ_INST_LEVEL_LDS.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_LDS
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INST_LEVEL_LDS
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_ACCUM_PREV_HIRES
+   |-> [/opt/rocm/bin/rocprofv2] Enabling Counter Collection
+[profiling] Current input file: tests/workloads/device_filter/MI300X_A1/perfmon/SQ_INST_LEVEL_SMEM.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_SMEM
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INST_LEVEL_SMEM
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_ACCUM_PREV_HIRES
+   |-> [/opt/rocm/bin/rocprofv2] Enabling Counter Collection
+[profiling] Current input file: tests/workloads/device_filter/MI300X_A1/perfmon/SQ_INST_LEVEL_VMEM.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VMEM
+[profiling] Current input file: tests/workloads/device_filter/MI300X_A1/perfmon/SQ_LEVEL_WAVES.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - GRBM_COUNT
+   |-> [/opt/rocm/bin/rocprofv2] - GRBM_GUI_ACTIVE
+   |-> [/opt/rocm/bin/rocprofv2] - CPC_ME1_BUSY_FOR_PACKET_DECODE
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_CYCLES
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_WAVES
+[profiling] Current input file: tests/workloads/device_filter/MI300X_A1/perfmon/pmc_perf_0.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_CYCLES
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_BUSY_CYCLES
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_BUSY_CU_CYCLES
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_WAVES
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_WAVE_CYCLES
+[profiling] Current input file: tests/workloads/device_filter/MI300X_A1/perfmon/pmc_perf_1.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VMEM
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_SALU
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VSKIPPED
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS
+[profiling] Current input file: tests/workloads/device_filter/MI300X_A1/perfmon/pmc_perf_10.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQC_TC_DATA_ATOMIC_REQ
+   |-> [/opt/rocm/bin/rocprofv2] - SQC_TC_STALL
+   |-> [/opt/rocm/bin/rocprofv2] - SQC_TC_REQ
+   |-> [/opt/rocm/bin/rocprofv2] - SQC_DCACHE_REQ_READ_16
+   |-> [/opt/rocm/bin/rocprofv2] - SQC_ICACHE_REQ
+[profiling] Current input file: tests/workloads/device_filter/MI300X_A1/perfmon/pmc_perf_11.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQC_DCACHE_INPUT_VALID_READYB
+   |-> [/opt/rocm/bin/rocprofv2] - SQC_DCACHE_ATOMIC
+   |-> [/opt/rocm/bin/rocprofv2] - SQC_DCACHE_REQ_READ_8
+   |-> [/opt/rocm/bin/rocprofv2] - SQC_DCACHE_REQ
+[profiling] Current input file: tests/workloads/device_filter/MI300X_A1/perfmon/pmc_perf_12.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQC_DCACHE_REQ_READ_2
+   |-> [/opt/rocm/bin/rocprofv2] - SQC_DCACHE_REQ_READ_4
+   |-> [/opt/rocm/bin/rocprofv2] Enabling Counter Collection
+   |-> [/opt/rocm/bin/rocprofv2] vcopy testing on GCD 0
+[profiling] Current input file: tests/workloads/device_filter/MI300X_A1/perfmon/pmc_perf_13.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_ATOMIC[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_BUBBLE[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_CYCLE[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_EA0_ATOMIC[0]
+[profiling] Current input file: tests/workloads/device_filter/MI300X_A1/perfmon/pmc_perf_14.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_EA0_ATOMIC_LEVEL[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_EA0_RDREQ[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_EA0_RDREQ_32B[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_EA0_RDREQ_LEVEL[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_EA0_ATOMIC_LEVEL[1]
+[profiling] Current input file: tests/workloads/device_filter/MI300X_A1/perfmon/pmc_perf_15.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_EA0_WRREQ[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_EA0_WRREQ_64B[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_EA0_WRREQ_LEVEL[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_HIT[0]
+[profiling] Current input file: tests/workloads/device_filter/MI300X_A1/perfmon/pmc_perf_16.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_MISS[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_READ[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_REQ[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_RW_REQ[0]
+[profiling] Current input file: tests/workloads/device_filter/MI300X_A1/perfmon/pmc_perf_17.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_TAG_STALL[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_TOO_MANY_EA_WRREQS_STALL[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_WRITE[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_TAG_STALL[1]
+[profiling] Current input file: tests/workloads/device_filter/MI300X_A1/perfmon/pmc_perf_2.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_TRANS_F16
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_ADD_F32
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_MUL_F32
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_FMA_F32
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_TRANS_F32
+[profiling] Current input file: tests/workloads/device_filter/MI300X_A1/perfmon/pmc_perf_3.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_TRANS_F64
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_INT32
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_INT64
+[profiling] Current input file: tests/workloads/device_filter/MI300X_A1/perfmon/pmc_perf_4.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_BRANCH
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_SENDMSG
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_WAIT_ANY
+[profiling] Current input file: tests/workloads/device_filter/MI300X_A1/perfmon/pmc_perf_5.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_ACTIVE_INST_SCA
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_ACTIVE_INST_EXP_GDS
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_ACTIVE_INST_MISC
+[profiling] Current input file: tests/workloads/device_filter/MI300X_A1/perfmon/pmc_perf_6.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_THREAD_CYCLES_VALU
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_IFETCH
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_LDS_BANK_CONFLICT
+[profiling] Current input file: tests/workloads/device_filter/MI300X_A1/perfmon/pmc_perf_7.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_WAVES_LT_32
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_WAVES_LT_16
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_ITEMS
+[profiling] Current input file: tests/workloads/device_filter/MI300X_A1/perfmon/pmc_perf_8.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_SMEM_NORM
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_MFMA
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_MFMA_I8
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_MFMA_F16
+[profiling] Current input file: tests/workloads/device_filter/MI300X_A1/perfmon/pmc_perf_9.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_MFMA_MOPS_I8
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_MFMA_MOPS_F16
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_MFMA_MOPS_BF16
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_MFMA_MOPS_F32
+[profiling] Current input file: tests/workloads/device_filter/MI300X_A1/perfmon/timestamps.txt
+   |-> [/opt/rocm/bin/rocprofv2] vcopy testing on GCD 0
+   |-> [/opt/rocm/bin/rocprofv2] Finished allocating vectors on the CPU
+   |-> [/opt/rocm/bin/rocprofv2] Finished allocating vectors on the GPU
+   |-> [/opt/rocm/bin/rocprofv2] Finished copying vectors to the GPU
+   |-> [/opt/rocm/bin/rocprofv2] sw thinks it moved 1.000000 KB per wave
+   |-> [/opt/rocm/bin/rocprofv2] Total threads: 1048576, Grid Size: 4096 block Size:256, Wavefronts:16384:
+[roofline] Roofline temporarily disabled in MI300
@@ -0,0 +1,5 @@
+pmc: GRBM_COUNT GRBM_GUI_ACTIVE SQ_WAVES SQ_IFETCH SQ_IFETCH_LEVEL  SQ_ACCUM_PREV_HIRES
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc: SQ_INSTS_LDS SQ_INST_LEVEL_LDS  SQ_ACCUM_PREV_HIRES
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc: SQ_INSTS_SMEM  SQ_INST_LEVEL_SMEM SQ_ACCUM_PREV_HIRES
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc: SQ_INSTS_VMEM  SQ_INST_LEVEL_VMEM SQ_ACCUM_PREV_HIRES
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc: GRBM_COUNT GRBM_GUI_ACTIVE CPC_ME1_BUSY_FOR_PACKET_DECODE SQ_CYCLES SQ_WAVES SQ_WAVE_CYCLES SQ_BUSY_CYCLES SQ_LEVEL_WAVES  SQ_ACCUM_PREV_HIRES
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQ_CYCLES SQ_BUSY_CYCLES SQ_BUSY_CU_CYCLES SQ_WAVES SQ_WAVE_CYCLES SQ_INSTS_VALU_CVT SQ_INSTS_VMEM_WR SQ_INSTS_VMEM_RD GRBM_COUNT GRBM_GUI_ACTIVE TCP_GATE_EN1_sum TCP_GATE_EN2_sum TCP_TD_TCP_STALL_CYCLES_sum TCP_TCR_TCP_STALL_CYCLES_sum TA_TA_BUSY_sum TA_BUFFER_WAVEFRONTS_sum TD_TD_BUSY_sum TD_TC_STALL_sum SPI_CSN_WINDOW_VALID SPI_CSN_BUSY CPC_CPC_STAT_BUSY CPC_CPC_STAT_IDLE CPF_CPF_STAT_BUSY CPF_CPF_STAT_STALL TCC_CYCLE_sum TCC_BUSY_sum TCC_PROBE_sum TCC_PROBE_ALL_sum
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQ_INSTS_VMEM SQ_INSTS_SALU SQ_INSTS_VSKIPPED SQ_INSTS SQ_INSTS_VALU SQ_INSTS_VALU_ADD_F16 SQ_INSTS_VALU_MUL_F16 SQ_INSTS_VALU_FMA_F16 GRBM_SPI_BUSY TCP_READ_TAGCONFLICT_STALL_CYCLES_sum TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum TCP_TA_TCP_STATE_READ_sum TA_BUFFER_READ_WAVEFRONTS_sum TA_BUFFER_WRITE_WAVEFRONTS_sum TD_SPI_STALL_sum TD_LOAD_WAVEFRONT_sum SPI_CSN_NUM_THREADGROUPS SPI_CSN_WAVE CPC_CPC_TCIU_BUSY CPC_CPC_TCIU_IDLE CPF_CPF_TCIU_BUSY CPF_CPF_TCIU_STALL TCC_NC_REQ_sum TCC_UC_REQ_sum TCC_CC_REQ_sum TCC_RW_REQ_sum
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQC_TC_DATA_ATOMIC_REQ SQC_TC_STALL SQC_TC_REQ SQC_DCACHE_REQ_READ_16 SQC_ICACHE_REQ SQC_ICACHE_HITS SQC_ICACHE_MISSES SQC_ICACHE_MISSES_DUPLICATE
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQC_DCACHE_INPUT_VALID_READYB SQC_DCACHE_ATOMIC SQC_DCACHE_REQ_READ_8 SQC_DCACHE_REQ SQC_DCACHE_HITS SQC_DCACHE_MISSES SQC_DCACHE_MISSES_DUPLICATE SQC_DCACHE_REQ_READ_1
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQC_DCACHE_REQ_READ_2 SQC_DCACHE_REQ_READ_4
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  TCC_ATOMIC[0] TCC_BUBBLE[0] TCC_CYCLE[0] TCC_EA0_ATOMIC[0] TCC_ATOMIC[1] TCC_BUBBLE[1] TCC_CYCLE[1] TCC_EA0_ATOMIC[1] TCC_ATOMIC[2] TCC_BUBBLE[2] TCC_CYCLE[2] TCC_EA0_ATOMIC[2] TCC_ATOMIC[3] TCC_BUBBLE[3] TCC_CYCLE[3] TCC_EA0_ATOMIC[3] TCC_ATOMIC[4] TCC_BUBBLE[4] TCC_CYCLE[4] TCC_EA0_ATOMIC[4] TCC_ATOMIC[5] TCC_BUBBLE[5] TCC_CYCLE[5] TCC_EA0_ATOMIC[5] TCC_ATOMIC[6] TCC_BUBBLE[6] TCC_CYCLE[6] TCC_EA0_ATOMIC[6] TCC_ATOMIC[7] TCC_BUBBLE[7] TCC_CYCLE[7] TCC_EA0_ATOMIC[7] TCC_ATOMIC[8] TCC_BUBBLE[8] TCC_CYCLE[8] TCC_EA0_ATOMIC[8] TCC_ATOMIC[9] TCC_BUBBLE[9] TCC_CYCLE[9] TCC_EA0_ATOMIC[9] TCC_ATOMIC[10] TCC_BUBBLE[10] TCC_CYCLE[10] TCC_EA0_ATOMIC[10] TCC_ATOMIC[11] TCC_BUBBLE[11] TCC_CYCLE[11] TCC_EA0_ATOMIC[11] TCC_ATOMIC[12] TCC_BUBBLE[12] TCC_CYCLE[12] TCC_EA0_ATOMIC[12] TCC_ATOMIC[13] TCC_BUBBLE[13] TCC_CYCLE[13] TCC_EA0_ATOMIC[13] TCC_ATOMIC[14] TCC_BUBBLE[14] TCC_CYCLE[14] TCC_EA0_ATOMIC[14] TCC_ATOMIC[15] TCC_BUBBLE[15] TCC_CYCLE[15] TCC_EA0_ATOMIC[15]
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  TCC_EA0_ATOMIC_LEVEL[0] TCC_EA0_RDREQ[0] TCC_EA0_RDREQ_32B[0] TCC_EA0_RDREQ_LEVEL[0] TCC_EA0_ATOMIC_LEVEL[1] TCC_EA0_RDREQ[1] TCC_EA0_RDREQ_32B[1] TCC_EA0_RDREQ_LEVEL[1] TCC_EA0_ATOMIC_LEVEL[2] TCC_EA0_RDREQ[2] TCC_EA0_RDREQ_32B[2] TCC_EA0_RDREQ_LEVEL[2] TCC_EA0_ATOMIC_LEVEL[3] TCC_EA0_RDREQ[3] TCC_EA0_RDREQ_32B[3] TCC_EA0_RDREQ_LEVEL[3] TCC_EA0_ATOMIC_LEVEL[4] TCC_EA0_RDREQ[4] TCC_EA0_RDREQ_32B[4] TCC_EA0_RDREQ_LEVEL[4] TCC_EA0_ATOMIC_LEVEL[5] TCC_EA0_RDREQ[5] TCC_EA0_RDREQ_32B[5] TCC_EA0_RDREQ_LEVEL[5] TCC_EA0_ATOMIC_LEVEL[6] TCC_EA0_RDREQ[6] TCC_EA0_RDREQ_32B[6] TCC_EA0_RDREQ_LEVEL[6] TCC_EA0_ATOMIC_LEVEL[7] TCC_EA0_RDREQ[7] TCC_EA0_RDREQ_32B[7] TCC_EA0_RDREQ_LEVEL[7] TCC_EA0_ATOMIC_LEVEL[8] TCC_EA0_RDREQ[8] TCC_EA0_RDREQ_32B[8] TCC_EA0_RDREQ_LEVEL[8] TCC_EA0_ATOMIC_LEVEL[9] TCC_EA0_RDREQ[9] TCC_EA0_RDREQ_32B[9] TCC_EA0_RDREQ_LEVEL[9] TCC_EA0_ATOMIC_LEVEL[10] TCC_EA0_RDREQ[10] TCC_EA0_RDREQ_32B[10] TCC_EA0_RDREQ_LEVEL[10] TCC_EA0_ATOMIC_LEVEL[11] TCC_EA0_RDREQ[11] TCC_EA0_RDREQ_32B[11] TCC_EA0_RDREQ_LEVEL[11] TCC_EA0_ATOMIC_LEVEL[12] TCC_EA0_RDREQ[12] TCC_EA0_RDREQ_32B[12] TCC_EA0_RDREQ_LEVEL[12] TCC_EA0_ATOMIC_LEVEL[13] TCC_EA0_RDREQ[13] TCC_EA0_RDREQ_32B[13] TCC_EA0_RDREQ_LEVEL[13] TCC_EA0_ATOMIC_LEVEL[14] TCC_EA0_RDREQ[14] TCC_EA0_RDREQ_32B[14] TCC_EA0_RDREQ_LEVEL[14] TCC_EA0_ATOMIC_LEVEL[15] TCC_EA0_RDREQ[15] TCC_EA0_RDREQ_32B[15] TCC_EA0_RDREQ_LEVEL[15]
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  TCC_EA0_WRREQ[0] TCC_EA0_WRREQ_64B[0] TCC_EA0_WRREQ_LEVEL[0] TCC_HIT[0] TCC_EA0_WRREQ[1] TCC_EA0_WRREQ_64B[1] TCC_EA0_WRREQ_LEVEL[1] TCC_HIT[1] TCC_EA0_WRREQ[2] TCC_EA0_WRREQ_64B[2] TCC_EA0_WRREQ_LEVEL[2] TCC_HIT[2] TCC_EA0_WRREQ[3] TCC_EA0_WRREQ_64B[3] TCC_EA0_WRREQ_LEVEL[3] TCC_HIT[3] TCC_EA0_WRREQ[4] TCC_EA0_WRREQ_64B[4] TCC_EA0_WRREQ_LEVEL[4] TCC_HIT[4] TCC_EA0_WRREQ[5] TCC_EA0_WRREQ_64B[5] TCC_EA0_WRREQ_LEVEL[5] TCC_HIT[5] TCC_EA0_WRREQ[6] TCC_EA0_WRREQ_64B[6] TCC_EA0_WRREQ_LEVEL[6] TCC_HIT[6] TCC_EA0_WRREQ[7] TCC_EA0_WRREQ_64B[7] TCC_EA0_WRREQ_LEVEL[7] TCC_HIT[7] TCC_EA0_WRREQ[8] TCC_EA0_WRREQ_64B[8] TCC_EA0_WRREQ_LEVEL[8] TCC_HIT[8] TCC_EA0_WRREQ[9] TCC_EA0_WRREQ_64B[9] TCC_EA0_WRREQ_LEVEL[9] TCC_HIT[9] TCC_EA0_WRREQ[10] TCC_EA0_WRREQ_64B[10] TCC_EA0_WRREQ_LEVEL[10] TCC_HIT[10] TCC_EA0_WRREQ[11] TCC_EA0_WRREQ_64B[11] TCC_EA0_WRREQ_LEVEL[11] TCC_HIT[11] TCC_EA0_WRREQ[12] TCC_EA0_WRREQ_64B[12] TCC_EA0_WRREQ_LEVEL[12] TCC_HIT[12] TCC_EA0_WRREQ[13] TCC_EA0_WRREQ_64B[13] TCC_EA0_WRREQ_LEVEL[13] TCC_HIT[13] TCC_EA0_WRREQ[14] TCC_EA0_WRREQ_64B[14] TCC_EA0_WRREQ_LEVEL[14] TCC_HIT[14] TCC_EA0_WRREQ[15] TCC_EA0_WRREQ_64B[15] TCC_EA0_WRREQ_LEVEL[15] TCC_HIT[15]
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  TCC_MISS[0] TCC_READ[0] TCC_REQ[0] TCC_RW_REQ[0] TCC_MISS[1] TCC_READ[1] TCC_REQ[1] TCC_RW_REQ[1] TCC_MISS[2] TCC_READ[2] TCC_REQ[2] TCC_RW_REQ[2] TCC_MISS[3] TCC_READ[3] TCC_REQ[3] TCC_RW_REQ[3] TCC_MISS[4] TCC_READ[4] TCC_REQ[4] TCC_RW_REQ[4] TCC_MISS[5] TCC_READ[5] TCC_REQ[5] TCC_RW_REQ[5] TCC_MISS[6] TCC_READ[6] TCC_REQ[6] TCC_RW_REQ[6] TCC_MISS[7] TCC_READ[7] TCC_REQ[7] TCC_RW_REQ[7] TCC_MISS[8] TCC_READ[8] TCC_REQ[8] TCC_RW_REQ[8] TCC_MISS[9] TCC_READ[9] TCC_REQ[9] TCC_RW_REQ[9] TCC_MISS[10] TCC_READ[10] TCC_REQ[10] TCC_RW_REQ[10] TCC_MISS[11] TCC_READ[11] TCC_REQ[11] TCC_RW_REQ[11] TCC_MISS[12] TCC_READ[12] TCC_REQ[12] TCC_RW_REQ[12] TCC_MISS[13] TCC_READ[13] TCC_REQ[13] TCC_RW_REQ[13] TCC_MISS[14] TCC_READ[14] TCC_REQ[14] TCC_RW_REQ[14] TCC_MISS[15] TCC_READ[15] TCC_REQ[15] TCC_RW_REQ[15]
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  TCC_TAG_STALL[0] TCC_TOO_MANY_EA_WRREQS_STALL[0] TCC_WRITE[0] TCC_TAG_STALL[1] TCC_TOO_MANY_EA_WRREQS_STALL[1] TCC_WRITE[1] TCC_TAG_STALL[2] TCC_TOO_MANY_EA_WRREQS_STALL[2] TCC_WRITE[2] TCC_TAG_STALL[3] TCC_TOO_MANY_EA_WRREQS_STALL[3] TCC_WRITE[3] TCC_TAG_STALL[4] TCC_TOO_MANY_EA_WRREQS_STALL[4] TCC_WRITE[4] TCC_TAG_STALL[5] TCC_TOO_MANY_EA_WRREQS_STALL[5] TCC_WRITE[5] TCC_TAG_STALL[6] TCC_TOO_MANY_EA_WRREQS_STALL[6] TCC_WRITE[6] TCC_TAG_STALL[7] TCC_TOO_MANY_EA_WRREQS_STALL[7] TCC_WRITE[7] TCC_TAG_STALL[8] TCC_TOO_MANY_EA_WRREQS_STALL[8] TCC_WRITE[8] TCC_TAG_STALL[9] TCC_TOO_MANY_EA_WRREQS_STALL[9] TCC_WRITE[9] TCC_TAG_STALL[10] TCC_TOO_MANY_EA_WRREQS_STALL[10] TCC_WRITE[10] TCC_TAG_STALL[11] TCC_TOO_MANY_EA_WRREQS_STALL[11] TCC_WRITE[11] TCC_TAG_STALL[12] TCC_TOO_MANY_EA_WRREQS_STALL[12] TCC_WRITE[12] TCC_TAG_STALL[13] TCC_TOO_MANY_EA_WRREQS_STALL[13] TCC_WRITE[13] TCC_TAG_STALL[14] TCC_TOO_MANY_EA_WRREQS_STALL[14] TCC_WRITE[14] TCC_TAG_STALL[15] TCC_TOO_MANY_EA_WRREQS_STALL[15] TCC_WRITE[15]
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQ_INSTS_VALU_TRANS_F16 SQ_INSTS_VALU_ADD_F32 SQ_INSTS_VALU_MUL_F32 SQ_INSTS_VALU_FMA_F32 SQ_INSTS_VALU_TRANS_F32 SQ_INSTS_VALU_ADD_F64 SQ_INSTS_VALU_MUL_F64 SQ_INSTS_VALU_FMA_F64 TCP_VOLATILE_sum TCP_TOTAL_ACCESSES_sum TCP_TOTAL_READ_sum TCP_TOTAL_WRITE_sum TA_BUFFER_ATOMIC_WAVEFRONTS_sum TA_BUFFER_TOTAL_CYCLES_sum TD_ATOMIC_WAVEFRONT_sum TD_STORE_WAVEFRONT_sum SPI_RA_REQ_NO_ALLOC SPI_RA_REQ_NO_ALLOC_CSN CPC_CPC_STAT_STALL CPC_UTCL1_STALL_ON_TRANSLATION CPF_CPF_STAT_IDLE CPF_CPF_TCIU_IDLE TCC_REQ_sum TCC_STREAMING_REQ_sum TCC_HIT_sum TCC_MISS_sum
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQ_INSTS_VALU_TRANS_F64 SQ_INSTS_VALU_INT32 SQ_INSTS_VALU_INT64 SQ_INSTS_SMEM SQ_INSTS_FLAT SQ_INSTS_LDS SQ_INSTS_GDS SQ_INSTS_EXP_GDS TCP_TOTAL_ATOMIC_WITH_RET_sum TCP_TOTAL_ATOMIC_WITHOUT_RET_sum TCP_TOTAL_WRITEBACK_INVALIDATES_sum TCP_TOTAL_CACHE_ACCESSES_sum TA_BUFFER_COALESCED_READ_CYCLES_sum TA_BUFFER_COALESCED_WRITE_CYCLES_sum TD_COALESCABLE_WAVEFRONT_sum SPI_RA_RES_STALL_CSN SPI_RA_TMP_STALL_CSN CPC_CPC_UTCL2IU_BUSY CPC_CPC_UTCL2IU_IDLE CPF_CMP_UTCL1_STALL_ON_TRANSLATION TCC_READ_sum TCC_WRITE_sum TCC_ATOMIC_sum TCC_WRITEBACK_sum
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQ_INSTS_BRANCH SQ_INSTS_SENDMSG SQ_WAIT_ANY SQ_WAIT_INST_ANY SQ_ACTIVE_INST_ANY SQ_ACTIVE_INST_VMEM SQ_ACTIVE_INST_LDS SQ_ACTIVE_INST_VALU TCP_UTCL1_TRANSLATION_MISS_sum TCP_UTCL1_TRANSLATION_HIT_sum TCP_UTCL1_PERMISSION_MISS_sum TCP_UTCL1_REQUEST_sum TA_ADDR_STALLED_BY_TC_CYCLES_sum TA_TOTAL_WAVEFRONTS_sum SPI_RA_WAVE_SIMD_FULL_CSN SPI_RA_VGPR_SIMD_FULL_CSN CPC_CPC_UTCL2IU_STALL CPC_ME1_BUSY_FOR_PACKET_DECODE TCC_EA0_WRREQ_sum TCC_EA0_WRREQ_64B_sum TCC_EA0_WR_UNCACHED_32B_sum TCC_EA0_WRREQ_DRAM_sum
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQ_ACTIVE_INST_SCA SQ_ACTIVE_INST_EXP_GDS SQ_ACTIVE_INST_MISC SQ_ACTIVE_INST_FLAT SQ_INST_CYCLES_VMEM_WR SQ_INST_CYCLES_VMEM_RD SQ_INST_CYCLES_SMEM SQ_INST_CYCLES_SALU TCP_TCC_READ_REQ_sum TCP_TCC_WRITE_REQ_sum TCP_TCC_ATOMIC_WITH_RET_REQ_sum TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum TA_ADDR_STALLED_BY_TD_CYCLES_sum TA_DATA_STALLED_BY_TC_CYCLES_sum SPI_RA_SGPR_SIMD_FULL_CSN SPI_RA_LDS_CU_FULL_CSN CPC_ME1_DC0_SPI_BUSY TCC_EA0_RDREQ_sum TCC_EA0_RDREQ_32B_sum TCC_BUBBLE_sum TCC_EA0_RD_UNCACHED_32B_sum
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQ_THREAD_CYCLES_VALU SQ_IFETCH SQ_LDS_BANK_CONFLICT SQ_LDS_ADDR_CONFLICT SQ_LDS_UNALIGNED_STALL SQ_WAVES_EQ_64 SQ_WAVES_LT_64 SQ_WAVES_LT_48 TCP_TCC_NC_READ_REQ_sum TCP_TCC_NC_WRITE_REQ_sum TCP_TCC_NC_ATOMIC_REQ_sum TCP_TCC_UC_READ_REQ_sum TA_FLAT_WAVEFRONTS_sum TA_FLAT_READ_WAVEFRONTS_sum SPI_RA_BAR_CU_FULL_CSN SPI_RA_TGLIM_CU_FULL_CSN TCC_EA0_RDREQ_DRAM_sum TCC_TAG_STALL_sum TCC_NORMAL_WRITEBACK_sum TCC_ALL_TC_OP_WB_WRITEBACK_sum
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQ_WAVES_LT_32 SQ_WAVES_LT_16 SQ_ITEMS SQ_LDS_MEM_VIOLATIONS SQ_LDS_ATOMIC_RETURN SQ_LDS_IDX_ACTIVE SQ_WAVES_RESTORED SQ_WAVES_SAVED TCP_TCC_UC_WRITE_REQ_sum TCP_TCC_UC_ATOMIC_REQ_sum TCP_TCC_CC_READ_REQ_sum TCP_TCC_CC_WRITE_REQ_sum TA_FLAT_WRITE_WAVEFRONTS_sum TA_FLAT_ATOMIC_WAVEFRONTS_sum SPI_RA_WVLIM_STALL_CSN SPI_SWC_CSC_WR TCC_NORMAL_EVICT_sum TCC_ALL_TC_OP_INV_EVICT_sum TCC_TOO_MANY_EA_WRREQS_STALL_sum TCC_EA0_ATOMIC_sum
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQ_INSTS_SMEM_NORM SQ_INSTS_MFMA SQ_INSTS_VALU_MFMA_I8 SQ_INSTS_VALU_MFMA_F16 SQ_INSTS_VALU_MFMA_BF16 SQ_INSTS_VALU_MFMA_F32 SQ_INSTS_VALU_MFMA_F64 SQ_VALU_MFMA_BUSY_CYCLES TCP_TCC_CC_ATOMIC_REQ_sum TCP_TCC_RW_READ_REQ_sum TCP_TCC_RW_WRITE_REQ_sum TCP_TCC_RW_ATOMIC_REQ_sum SPI_VWC_CSC_WR SPI_RA_BULKY_CU_FULL_CSN TCC_EA0_RDREQ_LEVEL_sum TCC_EA0_WRREQ_LEVEL_sum TCC_EA0_ATOMIC_LEVEL_sum TCC_EA0_WRREQ_STALL_sum
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQ_INSTS_VALU_MFMA_MOPS_I8 SQ_INSTS_VALU_MFMA_MOPS_F16 SQ_INSTS_VALU_MFMA_MOPS_BF16 SQ_INSTS_VALU_MFMA_MOPS_F32 SQ_INSTS_VALU_MFMA_MOPS_F64 SQC_TC_INST_REQ SQC_TC_DATA_READ_REQ SQC_TC_DATA_WRITE_REQ TCP_PENDING_STALL_CYCLES_sum
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,4 @@
+Dispatch_ID,GPU_ID,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,Wave_Size,Kernel_Name,Correlation_ID,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,Wave_Size_1,Correlation_ID_1,XCC_Index,TCC_ATOMIC[0],TCC_BUBBLE[0],TCC_CYCLE[0],TCC_EA0_ATOMIC[0],TCC_ATOMIC[1],TCC_BUBBLE[1],TCC_CYCLE[1],TCC_EA0_ATOMIC[1],TCC_ATOMIC[2],TCC_BUBBLE[2],TCC_CYCLE[2],TCC_EA0_ATOMIC[2],TCC_ATOMIC[3],TCC_BUBBLE[3],TCC_CYCLE[3],TCC_EA0_ATOMIC[3],TCC_ATOMIC[4],TCC_BUBBLE[4],TCC_CYCLE[4],TCC_EA0_ATOMIC[4],TCC_ATOMIC[5],TCC_BUBBLE[5],TCC_CYCLE[5],TCC_EA0_ATOMIC[5],TCC_ATOMIC[6],TCC_BUBBLE[6],TCC_CYCLE[6],TCC_EA0_ATOMIC[6],TCC_ATOMIC[7],TCC_BUBBLE[7],TCC_CYCLE[7],TCC_EA0_ATOMIC[7],TCC_ATOMIC[8],TCC_BUBBLE[8],TCC_CYCLE[8],TCC_EA0_ATOMIC[8],TCC_ATOMIC[9],TCC_BUBBLE[9],TCC_CYCLE[9],TCC_EA0_ATOMIC[9],TCC_ATOMIC[10],TCC_BUBBLE[10],TCC_CYCLE[10],TCC_EA0_ATOMIC[10],TCC_ATOMIC[11],TCC_BUBBLE[11],TCC_CYCLE[11],TCC_EA0_ATOMIC[11],TCC_ATOMIC[12],TCC_BUBBLE[12],TCC_CYCLE[12],TCC_EA0_ATOMIC[12],TCC_ATOMIC[13],TCC_BUBBLE[13],TCC_CYCLE[13],TCC_EA0_ATOMIC[13],TCC_ATOMIC[14],TCC_BUBBLE[14],TCC_CYCLE[14],TCC_EA0_ATOMIC[14],TCC_ATOMIC[15],TCC_BUBBLE[15],TCC_CYCLE[15],TCC_EA0_ATOMIC[15],TCC_ATOMIC[16],TCC_BUBBLE[16],TCC_CYCLE[16],TCC_EA0_ATOMIC[16],TCC_ATOMIC[17],TCC_BUBBLE[17],TCC_CYCLE[17],TCC_EA0_ATOMIC[17],TCC_ATOMIC[18],TCC_BUBBLE[18],TCC_CYCLE[18],TCC_EA0_ATOMIC[18],TCC_ATOMIC[19],TCC_BUBBLE[19],TCC_CYCLE[19],TCC_EA0_ATOMIC[19],TCC_ATOMIC[20],TCC_BUBBLE[20],TCC_CYCLE[20],TCC_EA0_ATOMIC[20],TCC_ATOMIC[21],TCC_BUBBLE[21],TCC_CYCLE[21],TCC_EA0_ATOMIC[21],TCC_ATOMIC[22],TCC_BUBBLE[22],TCC_CYCLE[22],TCC_EA0_ATOMIC[22],TCC_ATOMIC[23],TCC_BUBBLE[23],TCC_CYCLE[23],TCC_EA0_ATOMIC[23],TCC_ATOMIC[24],TCC_BUBBLE[24],TCC_CYCLE[24],TCC_EA0_ATOMIC[24],TCC_ATOMIC[25],TCC_BUBBLE[25],TCC_CYCLE[25],TCC_EA0_ATOMIC[25],TCC_ATOMIC[26],TCC_BUBBLE[26],TCC_CYCLE[26],TCC_EA0_ATOMIC[26],TCC_ATOMIC[27],TCC_BUBBLE[27],TCC_CYCLE[27],TCC_EA0_ATOMIC[27],TCC_ATOMIC[28],TCC_BUBBLE[28],TCC_CYCLE[28],TCC_EA0_ATOMIC[28],TCC_ATOMIC[29],TCC_BUBBLE[29],TCC_CYCLE[29],TCC_EA0_ATOMIC[29],TCC_ATOMIC[30],TCC_BUBBLE[30],TCC_CYCLE[30],TCC_EA0_ATOMIC[30],TCC_ATOMIC[31],TCC_BUBBLE[31],TCC_CYCLE[31],TCC_EA0_ATOMIC[31],TCC_ATOMIC[32],TCC_BUBBLE[32],TCC_CYCLE[32],TCC_EA0_ATOMIC[32],TCC_ATOMIC[33],TCC_BUBBLE[33],TCC_CYCLE[33],TCC_EA0_ATOMIC[33],TCC_ATOMIC[34],TCC_BUBBLE[34],TCC_CYCLE[34],TCC_EA0_ATOMIC[34],TCC_ATOMIC[35],TCC_BUBBLE[35],TCC_CYCLE[35],TCC_EA0_ATOMIC[35],TCC_ATOMIC[36],TCC_BUBBLE[36],TCC_CYCLE[36],TCC_EA0_ATOMIC[36],TCC_ATOMIC[37],TCC_BUBBLE[37],TCC_CYCLE[37],TCC_EA0_ATOMIC[37],TCC_ATOMIC[38],TCC_BUBBLE[38],TCC_CYCLE[38],TCC_EA0_ATOMIC[38],TCC_ATOMIC[39],TCC_BUBBLE[39],TCC_CYCLE[39],TCC_EA0_ATOMIC[39],TCC_ATOMIC[40],TCC_BUBBLE[40],TCC_CYCLE[40],TCC_EA0_ATOMIC[40],TCC_ATOMIC[41],TCC_BUBBLE[41],TCC_CYCLE[41],TCC_EA0_ATOMIC[41],TCC_ATOMIC[42],TCC_BUBBLE[42],TCC_CYCLE[42],TCC_EA0_ATOMIC[42],TCC_ATOMIC[43],TCC_BUBBLE[43],TCC_CYCLE[43],TCC_EA0_ATOMIC[43],TCC_ATOMIC[44],TCC_BUBBLE[44],TCC_CYCLE[44],TCC_EA0_ATOMIC[44],TCC_ATOMIC[45],TCC_BUBBLE[45],TCC_CYCLE[45],TCC_EA0_ATOMIC[45],TCC_ATOMIC[46],TCC_BUBBLE[46],TCC_CYCLE[46],TCC_EA0_ATOMIC[46],TCC_ATOMIC[47],TCC_BUBBLE[47],TCC_CYCLE[47],TCC_EA0_ATOMIC[47],TCC_ATOMIC[48],TCC_BUBBLE[48],TCC_CYCLE[48],TCC_EA0_ATOMIC[48],TCC_ATOMIC[49],TCC_BUBBLE[49],TCC_CYCLE[49],TCC_EA0_ATOMIC[49],TCC_ATOMIC[50],TCC_BUBBLE[50],TCC_CYCLE[50],TCC_EA0_ATOMIC[50],TCC_ATOMIC[51],TCC_BUBBLE[51],TCC_CYCLE[51],TCC_EA0_ATOMIC[51],TCC_ATOMIC[52],TCC_BUBBLE[52],TCC_CYCLE[52],TCC_EA0_ATOMIC[52],TCC_ATOMIC[53],TCC_BUBBLE[53],TCC_CYCLE[53],TCC_EA0_ATOMIC[53],TCC_ATOMIC[54],TCC_BUBBLE[54],TCC_CYCLE[54],TCC_EA0_ATOMIC[54],TCC_ATOMIC[55],TCC_BUBBLE[55],TCC_CYCLE[55],TCC_EA0_ATOMIC[55],TCC_ATOMIC[56],TCC_BUBBLE[56],TCC_CYCLE[56],TCC_EA0_ATOMIC[56],TCC_ATOMIC[57],TCC_BUBBLE[57],TCC_CYCLE[57],TCC_EA0_ATOMIC[57],TCC_ATOMIC[58],TCC_BUBBLE[58],TCC_CYCLE[58],TCC_EA0_ATOMIC[58],TCC_ATOMIC[59],TCC_BUBBLE[59],TCC_CYCLE[59],TCC_EA0_ATOMIC[59],TCC_ATOMIC[60],TCC_BUBBLE[60],TCC_CYCLE[60],TCC_EA0_ATOMIC[60],TCC_ATOMIC[61],TCC_BUBBLE[61],TCC_CYCLE[61],TCC_EA0_ATOMIC[61],TCC_ATOMIC[62],TCC_BUBBLE[62],TCC_CYCLE[62],TCC_EA0_ATOMIC[62],TCC_ATOMIC[63],TCC_BUBBLE[63],TCC_CYCLE[63],TCC_EA0_ATOMIC[63],TCC_ATOMIC[64],TCC_BUBBLE[64],TCC_CYCLE[64],TCC_EA0_ATOMIC[64],TCC_ATOMIC[65],TCC_BUBBLE[65],TCC_CYCLE[65],TCC_EA0_ATOMIC[65],TCC_ATOMIC[66],TCC_BUBBLE[66],TCC_CYCLE[66],TCC_EA0_ATOMIC[66],TCC_ATOMIC[67],TCC_BUBBLE[67],TCC_CYCLE[67],TCC_EA0_ATOMIC[67],TCC_ATOMIC[68],TCC_BUBBLE[68],TCC_CYCLE[68],TCC_EA0_ATOMIC[68],TCC_ATOMIC[69],TCC_BUBBLE[69],TCC_CYCLE[69],TCC_EA0_ATOMIC[69],TCC_ATOMIC[70],TCC_BUBBLE[70],TCC_CYCLE[70],TCC_EA0_ATOMIC[70],TCC_ATOMIC[71],TCC_BUBBLE[71],TCC_CYCLE[71],TCC_EA0_ATOMIC[71],TCC_ATOMIC[72],TCC_BUBBLE[72],TCC_CYCLE[72],TCC_EA0_ATOMIC[72],TCC_ATOMIC[73],TCC_BUBBLE[73],TCC_CYCLE[73],TCC_EA0_ATOMIC[73],TCC_ATOMIC[74],TCC_BUBBLinha truncada
+0,60633,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",0,2579507.0,0.0,0.0,65536.0,60576.0,160.0,4800.0,32768.0,64,0,0,0.0,512.0,47833.0,0.0,0.0,512.0,47833.0,0.0,0.0,512.0,47833.0,0.0,0.0,512.0,47833.0,0.0,0.0,512.0,47833.0,0.0,0.0,512.0,47833.0,0.0,0.0,512.0,47833.0,0.0,0.0,512.0,47833.0,0.0,0.0,512.0,47833.0,0.0,0.0,512.0,47833.0,0.0,0.0,512.0,47833.0,0.0,0.0,512.0,47833.0,0.0,0.0,512.0,47833.0,0.0,0.0,512.0,47833.0,0.0,0.0,512.0,47833.0,0.0,0.0,512.0,47833.0,0.0,0.0,512.0,44756.0,0.0,0.0,512.0,44756.0,0.0,0.0,512.0,44756.0,0.0,0.0,512.0,44756.0,0.0,0.0,512.0,44756.0,0.0,0.0,512.0,44756.0,0.0,0.0,512.0,44756.0,0.0,0.0,512.0,44756.0,0.0,0.0,512.0,44756.0,0.0,0.0,512.0,44756.0,0.0,0.0,512.0,44756.0,0.0,0.0,512.0,44756.0,0.0,0.0,512.0,44756.0,0.0,0.0,512.0,44756.0,0.0,0.0,512.0,44756.0,0.0,0.0,512.0,44756.0,0.0,0.0,512.0,62026.0,0.0,0.0,512.0,62026.0,0.0,0.0,512.0,62026.0,0.0,0.0,512.0,62026.0,0.0,0.0,512.0,62026.0,0.0,0.0,512.0,62026.0,0.0,0.0,512.0,62026.0,0.0,0.0,512.0,62026.0,0.0,0.0,512.0,62026.0,0.0,0.0,512.0,62026.0,0.0,0.0,512.0,62026.0,0.0,0.0,512.0,62026.0,0.0,0.0,512.0,62026.0,0.0,0.0,512.0,62026.0,0.0,0.0,512.0,62026.0,0.0,0.0,512.0,62026.0,0.0,0.0,512.0,67392.0,0.0,0.0,512.0,67392.0,0.0,0.0,512.0,67392.0,0.0,0.0,512.0,67392.0,0.0,0.0,512.0,67392.0,0.0,0.0,512.0,67392.0,0.0,0.0,512.0,67392.0,0.0,0.0,512.0,67392.0,0.0,0.0,512.0,67392.0,0.0,0.0,512.0,67392.0,0.0,0.0,512.0,67392.0,0.0,0.0,512.0,67392.0,0.0,0.0,512.0,67392.0,0.0,0.0,512.0,67392.0,0.0,0.0,512.0,67392.0,0.0,0.0,512.0,67392.0,0.0,0.0,512.0,88078.0,0.0,0.0,512.0,88078.0,0.0,0.0,512.0,88078.0,0.0,0.0,512.0,88078.0,0.0,0.0,512.0,88078.0,0.0,0.0,512.0,88078.0,0.0,0.0,512.0,88078.0,0.0,0.0,512.0,88078.0,0.0,0.0,512.0,88078.0,0.0,0.0,512.0,88078.0,0.0,0.0,512.0,88078.0,0.0,0.0,512.0,88078.0,0.0,0.0,512.0,88078.0,0.0,0.0,512.0,88078.0,0.0,0.0,512.0,88078.0,0.0,0.0,512.0,88078.0,0.0,0.0,512.0,100177.0,0.0,0.0,512.0,100177.0,0.0,0.0,512.0,100177.0,0.0,0.0,512.0,100177.0,0.0,0.0,512.0,100177.0,0.0,0.0,512.0,100177.0,0.0,0.0,512.0,100177.0,0.0,0.0,512.0,100177.0,0.0,0.0,512.0,100177.0,0.0,0.0,512.0,100177.0,0.0,0.0,512.0,100177.0,0.0,0.0,512.0,100177.0,0.0,0.0,512.0,100177.0,0.0,0.0,512.0,100177.0,0.0,0.0,512.0,100177.0,0.0,0.0,512.0,100177.0,0.0,0.0,512.0,102523.0,0.0,0.0,512.0,102523.0,0.0,0.0,512.0,102523.0,0.0,0.0,512.0,102523.0,0.0,0.0,512.0,102523.0,0.0,0.0,512.0,102523.0,0.0,0.0,512.0,102523.0,0.0,0.0,512.0,102523.0,0.0,0.0,512.0,102523.0,0.0,0.0,512.0,102523.0,0.0,0.0,512.0,102523.0,0.0,0.0,512.0,102523.0,0.0,0.0,512.0,102523.0,0.0,0.0,512.0,102523.0,0.0,0.0,512.0,102523.0,0.0,0.0,512.0,102523.0,0.0,0.0,512.0,112654.0,0.0,0.0,512.0,112654.0,0.0,0.0,512.0,112654.0,0.0,0.0,512.0,112654.0,0.0,0.0,512.0,112654.0,0.0,0.0,512.0,112654.0,0.0,0.0,512.0,112654.0,0.0,0.0,512.0,112654.0,0.0,0.0,512.0,112654.0,0.0,0.0,512.0,112654.0,0.0,0.0,512.0,112654.0,0.0,0.0,512.0,112654.0,0.0,0.0,512.0,112654.0,0.0,0.0,512.0,112654.0,0.0,0.0,512.0,112654.0,0.0,0.0,512.0,112654.0,0.0,64,0,0.0,0.0,1048576.0,0.0,0.0,0.0,0.0,0.0,0.0,32768.0,0.0,16384.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,64,0,131072.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,16384.0,0.0,0.0,106313320.0,78709793.0,287102.0,0.0,0.0,65536.0,131072.0,64,0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,124352.0,41261.0,2103449.0,696.0,0.0,457115.0,0.0,0.0,66160.0,131314.0,197474.0,0.0,2097152.0,1048576.0,1048576.0,2097152.0,0.0,16384.0,64,0,0,1024.0,512.0,1536.0,1536.0,1025.0,513.0,1537.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1046.0,534.0,1558.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1026.0,592.0,1616.0,1616.0,1027.0,515.0,1539.0,1536.0,1024.0,512.0,1536.0,1536.0,1025.0,513.0,1537.0,1536.0,1024.0,512.0,1536.0,1536.0,1046.0,534.0,1558.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1026.0,592.0,1616.0,1616.0,1030.0,518.0,1542.0,1536.0,1024.0,512.0,1536.0,1536.0,1025.0,513.0,1537.0,1536.0,1024.0,512.0,1536.0,1536.0,1025.0,513.0,1537.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1025.0,513.0,1537.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1046.0,534.0,1558.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1026.0,592.0,1616.0,1616.0,1028.0,516.0,1540.0,1536.0,1024.0,512.0,1536.0,1536.0,1025.0,513.0,1537.0,1536.0,1024.0,512.0,1536.0,1536.0,1046.0,534.0,1558.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1026.0,592.0,1616.0,1616.0,1027.0,515.0,1539.0,1536.0,1024.0,512.0,1536.0,1536.0,1025.0,513.0,1537.0,1536.0,1024.0,512.0,1536.0,1536.0,1025.0,513.0,1537.0,1536.0,1024.0,512.0,1536.0,1536Linha truncada
+1,60633,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",0,2964941.0,0.0,0.0,65536.0,60576.0,160.0,4800.0,32768.0,64,0,0,0.0,512.0,42306.0,0.0,0.0,512.0,42306.0,0.0,0.0,512.0,42306.0,0.0,0.0,512.0,42306.0,0.0,0.0,512.0,42306.0,0.0,0.0,512.0,42306.0,0.0,0.0,512.0,42306.0,0.0,0.0,512.0,42306.0,0.0,0.0,512.0,42306.0,0.0,0.0,512.0,42306.0,0.0,0.0,512.0,42306.0,0.0,0.0,512.0,42306.0,0.0,0.0,512.0,42306.0,0.0,0.0,512.0,42306.0,0.0,0.0,512.0,42306.0,0.0,0.0,512.0,42306.0,0.0,0.0,512.0,43334.0,0.0,0.0,512.0,43334.0,0.0,0.0,512.0,43334.0,0.0,0.0,512.0,43334.0,0.0,0.0,512.0,43334.0,0.0,0.0,512.0,43334.0,0.0,0.0,512.0,43334.0,0.0,0.0,512.0,43334.0,0.0,0.0,512.0,43334.0,0.0,0.0,512.0,43334.0,0.0,0.0,512.0,43334.0,0.0,0.0,512.0,43334.0,0.0,0.0,512.0,43334.0,0.0,0.0,512.0,43334.0,0.0,0.0,512.0,43334.0,0.0,0.0,512.0,43334.0,0.0,0.0,512.0,61831.0,0.0,0.0,512.0,61831.0,0.0,0.0,512.0,61831.0,0.0,0.0,512.0,61831.0,0.0,0.0,512.0,61831.0,0.0,0.0,512.0,61831.0,0.0,0.0,512.0,61831.0,0.0,0.0,512.0,61831.0,0.0,0.0,512.0,61831.0,0.0,0.0,512.0,61831.0,0.0,0.0,512.0,61831.0,0.0,0.0,512.0,61831.0,0.0,0.0,512.0,61831.0,0.0,0.0,512.0,61831.0,0.0,0.0,512.0,61831.0,0.0,0.0,512.0,61831.0,0.0,0.0,512.0,71556.0,0.0,0.0,512.0,71556.0,0.0,0.0,512.0,71556.0,0.0,0.0,512.0,71556.0,0.0,0.0,512.0,71556.0,0.0,0.0,512.0,71556.0,0.0,0.0,512.0,71556.0,0.0,0.0,512.0,71556.0,0.0,0.0,512.0,71556.0,0.0,0.0,512.0,71556.0,0.0,0.0,512.0,71556.0,0.0,0.0,512.0,71556.0,0.0,0.0,512.0,71556.0,0.0,0.0,512.0,71556.0,0.0,0.0,512.0,71556.0,0.0,0.0,512.0,71556.0,0.0,0.0,512.0,84426.0,0.0,0.0,512.0,84426.0,0.0,0.0,512.0,84426.0,0.0,0.0,512.0,84426.0,0.0,0.0,512.0,84426.0,0.0,0.0,512.0,84426.0,0.0,0.0,512.0,84426.0,0.0,0.0,512.0,84426.0,0.0,0.0,512.0,84426.0,0.0,0.0,512.0,84426.0,0.0,0.0,512.0,84426.0,0.0,0.0,512.0,84426.0,0.0,0.0,512.0,84426.0,0.0,0.0,512.0,84426.0,0.0,0.0,512.0,84426.0,0.0,0.0,512.0,84426.0,0.0,0.0,512.0,96245.0,0.0,0.0,512.0,96245.0,0.0,0.0,512.0,96245.0,0.0,0.0,512.0,96245.0,0.0,0.0,512.0,96245.0,0.0,0.0,512.0,96245.0,0.0,0.0,512.0,96245.0,0.0,0.0,512.0,96245.0,0.0,0.0,512.0,96245.0,0.0,0.0,512.0,96245.0,0.0,0.0,512.0,96245.0,0.0,0.0,512.0,96245.0,0.0,0.0,512.0,96245.0,0.0,0.0,512.0,96245.0,0.0,0.0,512.0,96245.0,0.0,0.0,512.0,96245.0,0.0,0.0,512.0,97295.0,0.0,0.0,512.0,97295.0,0.0,0.0,512.0,97295.0,0.0,0.0,512.0,97295.0,0.0,0.0,512.0,97295.0,0.0,0.0,512.0,97295.0,0.0,0.0,512.0,97295.0,0.0,0.0,512.0,97295.0,0.0,0.0,512.0,97295.0,0.0,0.0,512.0,97295.0,0.0,0.0,512.0,97295.0,0.0,0.0,512.0,97295.0,0.0,0.0,512.0,97295.0,0.0,0.0,512.0,97295.0,0.0,0.0,512.0,97295.0,0.0,0.0,512.0,97295.0,0.0,0.0,512.0,105864.0,0.0,0.0,512.0,105864.0,0.0,0.0,512.0,105864.0,0.0,0.0,512.0,105864.0,0.0,0.0,512.0,105864.0,0.0,0.0,512.0,105864.0,0.0,0.0,512.0,105864.0,0.0,0.0,512.0,105864.0,0.0,0.0,512.0,105864.0,0.0,0.0,512.0,105864.0,0.0,0.0,512.0,105864.0,0.0,0.0,512.0,105864.0,0.0,0.0,512.0,105864.0,0.0,0.0,512.0,105864.0,0.0,0.0,512.0,105864.0,0.0,0.0,512.0,105864.0,0.0,64,0,0.0,0.0,1048576.0,0.0,0.0,0.0,0.0,0.0,0.0,32768.0,0.0,16384.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,64,0,131072.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,16384.0,0.0,0.0,58781442.0,79949547.0,289329.0,0.0,0.0,65536.0,131072.0,64,0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,49090.0,29851.0,1995062.0,9609.0,0.0,242373.0,0.0,0.0,65536.0,131321.0,196857.0,0.0,2097152.0,1048576.0,1048576.0,2097152.0,0.0,16384.0,64,0,0,1024.0,512.0,1536.0,1536.0,1026.0,514.0,1538.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1046.0,534.0,1558.0,1536.0,1025.0,513.0,1537.0,1536.0,1025.0,513.0,1537.0,1536.0,1025.0,513.0,1537.0,1536.0,1027.0,515.0,1539.0,1536.0,1024.0,512.0,1536.0,1536.0,1025.0,513.0,1537.0,1536.0,1024.0,512.0,1536.0,1536.0,1045.0,533.0,1557.0,1536.0,1025.0,513.0,1537.0,1536.0,1024.0,512.0,1536.0,1536.0,1025.0,513.0,1537.0,1536.0,1027.0,515.0,1539.0,1536.0,1024.0,512.0,1536.0,1536.0,1025.0,513.0,1537.0,1536.0,1024.0,512.0,1536.0,1536.0,1026.0,514.0,1538.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1025.0,513.0,1537.0,1536.0,1025.0,513.0,1537.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1026.0,514.0,1538.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1025.0,513.0,1537.0,1536.0,1025.0,513.0,1537.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1045.0,533.0,1557.0,1536.0,1025.0,513.0,1537.0,1536.0,1024.0,512.0,1536.0,1536.0,1025.0,513.0,1537.0,1536.0,1026.0,514.0,1538.0,1536.0,1024.0,512.0,1536.0,1536.0,1025.0,513.0,1537.0,1536.0,1024.0,512.0,1536.0,1536.0,1046.0,534.0,1558.0,1536.0,1025.0,513.0,1537.0,1536.0,1025.0,513.0,1537.0,1536.0,1025.0,513.0,1537.0,1536.0,1028.0,516.0,1540.0,1536.0,1024.0,512.0,1536.0,1536.0,1026.0,514.0,1538.0,1536.0,1024.0,512.0,1536.0,1536.0,1027.0,515.0,1539.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,102Linha truncada
+2,60633,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",0,2920449.0,0.0,0.0,65536.0,60576.0,160.0,4800.0,32768.0,64,0,0,0.0,512.0,42343.0,0.0,0.0,512.0,42343.0,0.0,0.0,512.0,42343.0,0.0,0.0,512.0,42343.0,0.0,0.0,512.0,42343.0,0.0,0.0,512.0,42343.0,0.0,0.0,512.0,42343.0,0.0,0.0,512.0,42343.0,0.0,0.0,512.0,42343.0,0.0,0.0,512.0,42343.0,0.0,0.0,512.0,42343.0,0.0,0.0,512.0,42343.0,0.0,0.0,512.0,42343.0,0.0,0.0,512.0,42343.0,0.0,0.0,512.0,42343.0,0.0,0.0,512.0,42343.0,0.0,0.0,512.0,35792.0,0.0,0.0,512.0,35792.0,0.0,0.0,512.0,35792.0,0.0,0.0,512.0,35792.0,0.0,0.0,512.0,35792.0,0.0,0.0,512.0,35792.0,0.0,0.0,512.0,35792.0,0.0,0.0,512.0,35792.0,0.0,0.0,512.0,35792.0,0.0,0.0,512.0,35792.0,0.0,0.0,512.0,35792.0,0.0,0.0,512.0,35792.0,0.0,0.0,512.0,35792.0,0.0,0.0,512.0,35792.0,0.0,0.0,512.0,35792.0,0.0,0.0,512.0,35792.0,0.0,0.0,512.0,56305.0,0.0,0.0,512.0,56305.0,0.0,0.0,512.0,56305.0,0.0,0.0,512.0,56305.0,0.0,0.0,512.0,56305.0,0.0,0.0,512.0,56305.0,0.0,0.0,512.0,56305.0,0.0,0.0,512.0,56305.0,0.0,0.0,512.0,56305.0,0.0,0.0,512.0,56305.0,0.0,0.0,512.0,56305.0,0.0,0.0,512.0,56305.0,0.0,0.0,512.0,56305.0,0.0,0.0,512.0,56305.0,0.0,0.0,512.0,56305.0,0.0,0.0,512.0,56305.0,0.0,0.0,512.0,66837.0,0.0,0.0,512.0,66837.0,0.0,0.0,512.0,66837.0,0.0,0.0,512.0,66837.0,0.0,0.0,512.0,66837.0,0.0,0.0,512.0,66837.0,0.0,0.0,512.0,66837.0,0.0,0.0,512.0,66837.0,0.0,0.0,512.0,66837.0,0.0,0.0,512.0,66837.0,0.0,0.0,512.0,66837.0,0.0,0.0,512.0,66837.0,0.0,0.0,512.0,66837.0,0.0,0.0,512.0,66837.0,0.0,0.0,512.0,66837.0,0.0,0.0,512.0,66837.0,0.0,0.0,512.0,77526.0,0.0,0.0,512.0,77526.0,0.0,0.0,512.0,77526.0,0.0,0.0,512.0,77526.0,0.0,0.0,512.0,77526.0,0.0,0.0,512.0,77526.0,0.0,0.0,512.0,77526.0,0.0,0.0,512.0,77526.0,0.0,0.0,512.0,77526.0,0.0,0.0,512.0,77526.0,0.0,0.0,512.0,77526.0,0.0,0.0,512.0,77526.0,0.0,0.0,512.0,77526.0,0.0,0.0,512.0,77526.0,0.0,0.0,512.0,77526.0,0.0,0.0,512.0,77526.0,0.0,0.0,512.0,88886.0,0.0,0.0,512.0,88886.0,0.0,0.0,512.0,88886.0,0.0,0.0,512.0,88886.0,0.0,0.0,512.0,88886.0,0.0,0.0,512.0,88886.0,0.0,0.0,512.0,88886.0,0.0,0.0,512.0,88886.0,0.0,0.0,512.0,88886.0,0.0,0.0,512.0,88886.0,0.0,0.0,512.0,88886.0,0.0,0.0,512.0,88886.0,0.0,0.0,512.0,88886.0,0.0,0.0,512.0,88886.0,0.0,0.0,512.0,88886.0,0.0,0.0,512.0,88886.0,0.0,0.0,512.0,90144.0,0.0,0.0,512.0,90144.0,0.0,0.0,512.0,90144.0,0.0,0.0,512.0,90144.0,0.0,0.0,512.0,90144.0,0.0,0.0,512.0,90144.0,0.0,0.0,512.0,90144.0,0.0,0.0,512.0,90144.0,0.0,0.0,512.0,90144.0,0.0,0.0,512.0,90144.0,0.0,0.0,512.0,90144.0,0.0,0.0,512.0,90144.0,0.0,0.0,512.0,90144.0,0.0,0.0,512.0,90144.0,0.0,0.0,512.0,90144.0,0.0,0.0,512.0,90144.0,0.0,0.0,512.0,100192.0,0.0,0.0,512.0,100192.0,0.0,0.0,512.0,100192.0,0.0,0.0,512.0,100192.0,0.0,0.0,512.0,100192.0,0.0,0.0,512.0,100192.0,0.0,0.0,512.0,100192.0,0.0,0.0,512.0,100192.0,0.0,0.0,512.0,100192.0,0.0,0.0,512.0,100192.0,0.0,0.0,512.0,100192.0,0.0,0.0,512.0,100192.0,0.0,0.0,512.0,100192.0,0.0,0.0,512.0,100192.0,0.0,0.0,512.0,100192.0,0.0,0.0,512.0,100192.0,0.0,64,0,0.0,0.0,1048576.0,0.0,0.0,0.0,0.0,0.0,0.0,32768.0,0.0,16384.0,0.0,0.0,25.0,0.0,0.0,0.0,0.0,0.0,64,0,131072.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,16384.0,0.0,0.0,39165814.0,52183729.0,131388.0,0.0,0.0,65536.0,131072.0,64,0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,49601.0,30790.0,1995849.0,9682.0,0.0,247415.0,0.0,0.0,65536.0,131326.0,196862.0,0.0,2097152.0,1048576.0,1048576.0,2097152.0,0.0,16384.0,64,0,0,1024.0,512.0,1536.0,1536.0,1026.0,514.0,1538.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1046.0,534.0,1558.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1025.0,513.0,1537.0,1536.0,1027.0,515.0,1539.0,1536.0,1024.0,512.0,1536.0,1536.0,1025.0,513.0,1537.0,1536.0,1024.0,512.0,1536.0,1536.0,1046.0,534.0,1558.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1025.0,513.0,1537.0,1536.0,1028.0,516.0,1540.0,1536.0,1024.0,512.0,1536.0,1536.0,1025.0,513.0,1537.0,1536.0,1024.0,512.0,1536.0,1536.0,1026.0,514.0,1538.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1026.0,514.0,1538.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1046.0,534.0,1558.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1025.0,513.0,1537.0,1536.0,1026.0,514.0,1538.0,1536.0,1024.0,512.0,1536.0,1536.0,1025.0,513.0,1537.0,1536.0,1024.0,512.0,1536.0,1536.0,1046.0,534.0,1558.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1025.0,513.0,1537.0,1536.0,1026.0,514.0,1538.0,1536.0,1024.0,512.0,1536.0,1536.0,1025.0,513.0,1537.0,1536.0,1024.0,512.0,1536.0,1536.0,1026.0,514.0,1538.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,10Linha truncada
@@ -0,0 +1,2 @@
+workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd
+device_filter,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Wed 29 May 2024 12:03:10 PM  (CDT),2,splinter-126-wr-c6,AMD Ryzen 9 7950X 16-Core Processor,"American Megatrends International, LLC.VS2683299N.FD",Ubuntu 22.04.4 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,114656528,,6.2.0-13611,113-MI3SRIOV-001,SPX,NPS1,MI300X_A1,gfx942,32,4096,304,4,32,64,1024,32,2100,1300,2100,1300,128,32,160,4,5324.8,8
@@ -0,0 +1,4 @@
+Dispatch_ID,GPU_ID,Queue_ID,PID,TID,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,Wave_Size,Kernel_Name,Start_Timestamp,End_Timestamp,Correlation_ID
+1,60633,1,967084,967084,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",716380685145736,716380685161855,0
+2,60633,1,967084,967084,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",716380685184013,716380685197573,0
+3,60633,1,967084,967084,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",716380685217852,716380685231332,0
@@ -0,0 +1,4 @@
+Dispatch_ID,GPU_ID,Queue_ID,PID,TID,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,Wave_Size,Kernel_Name,Start_Timestamp,End_Timestamp,Correlation_ID,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES
+0,11995,1,147631,147631,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",73775713810508,73775713819482,0,198768.0,198768.0,16384.0,65536.0,30553.0,2437716.0
+1,11995,1,147631,147631,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",73775713837269,73775713843599,0,185170.0,185170.0,16384.0,65536.0,13014.0,1048612.0
+2,11995,1,147631,147631,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",73775713858742,73775713864711,0,166578.0,166578.0,16384.0,65536.0,13160.0,1048760.0
@@ -0,0 +1,4 @@
+Dispatch_ID,GPU_ID,Queue_ID,PID,TID,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,Wave_Size,Kernel_Name,Start_Timestamp,End_Timestamp,Correlation_ID,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES
+0,11995,1,147642,147642,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",73775713810508,73775713819482,0,0.0,0.0,0.0
+1,11995,1,147642,147642,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",73775713837269,73775713843599,0,0.0,0.0,0.0
+2,11995,1,147642,147642,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",73775713858742,73775713864711,0,0.0,0.0,0.0
@@ -0,0 +1,4 @@
+Dispatch_ID,GPU_ID,Queue_ID,PID,TID,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,Wave_Size,Kernel_Name,Start_Timestamp,End_Timestamp,Correlation_ID,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES
+0,11995,1,147653,147653,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",73775713810508,73775713819482,0,65536.0,295872.0,23626064.0
+1,11995,1,147653,147653,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",73775713837269,73775713843599,0,65536.0,312782.0,24988448.0
+2,11995,1,147653,147653,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",73775713858742,73775713864711,0,65536.0,210580.0,16805392.0
@@ -0,0 +1,4 @@
+Dispatch_ID,GPU_ID,Queue_ID,PID,TID,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,Wave_Size,Kernel_Name,Start_Timestamp,End_Timestamp,Correlation_ID,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES
+0,11995,1,147664,147664,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",73775713810508,73775713819482,0,32768.0,538994.0,43116484.0
+1,11995,1,147664,147664,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",73775713837269,73775713843599,0,32768.0,402738.0,32213296.0
+2,11995,1,147664,147664,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",73775713858742,73775713864711,0,32768.0,403310.0,32259720.0
@@ -0,0 +1,4 @@
+Dispatch_ID,GPU_ID,Queue_ID,PID,TID,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,Wave_Size,Kernel_Name,Start_Timestamp,End_Timestamp,Correlation_ID,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES
+0,11995,1,147675,147675,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",73775713810508,73775713819482,0,209852.0,209852.0,118131.0,839408.0,16384.0,13412399.0,248440.0,0.0,54053128.0
+1,11995,1,147675,147675,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",73775713837269,73775713843599,0,195449.0,195449.0,109420.0,781796.0,16384.0,11478548.0,207429.0,0.0,46306644.0
+2,11995,1,147675,147675,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",73775713858742,73775713864711,0,171967.0,171967.0,93464.0,687868.0,16384.0,10057887.0,187792.0,0.0,40635096.0
@@ -0,0 +1,280 @@
+Omniperf version: 2.0.0
+Profiler choice: rocprofv2
+Path: /home/colramos/omniperf/tests/workloads/device_inv_int/MI300A_A1
+Target: MI300A_A1
+Command: ./tests/vcopy -n 1048576 -b 256 -i 3
+Kernel Selection: None
+Dispatch Selection: None
+Hardware Blocks: All
+
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Collecting Performance Counters
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+[profiling] Current input file: tests/workloads/device_inv_int/MI300A_A1/perfmon/SQ_IFETCH_LEVEL.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - GRBM_COUNT
+   |-> [/opt/rocm/bin/rocprofv2] - GRBM_GUI_ACTIVE
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_WAVES
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_IFETCH
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_IFETCH_LEVEL
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_ACCUM_PREV_HIRES
+   |-> [/opt/rocm/bin/rocprofv2] Enabling Counter Collection
+   |-> [/opt/rocm/bin/rocprofv2] vcopy testing on GCD 0
+   |-> [/opt/rocm/bin/rocprofv2] Finished allocating vectors on the CPU
+   |-> [/opt/rocm/bin/rocprofv2] Finished allocating vectors on the GPU
+   |-> [/opt/rocm/bin/rocprofv2] Finished copying vectors to the GPU
+   |-> [/opt/rocm/bin/rocprofv2] sw thinks it moved 1.000000 KB per wave
+   |-> [/opt/rocm/bin/rocprofv2] Total threads: 1048576, Grid Size: 4096 block Size:256, Wavefronts:16384:
+   |-> [/opt/rocm/bin/rocprofv2] Launching the  kernel on the GPU
+   |-> [/opt/rocm/bin/rocprofv2] Finished executing kernel
+   |-> [/opt/rocm/bin/rocprofv2] Finished executing kernel
+[profiling] Current input file: tests/workloads/device_inv_int/MI300A_A1/perfmon/SQ_INST_LEVEL_LDS.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_LDS
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INST_LEVEL_LDS
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_ACCUM_PREV_HIRES
+   |-> [/opt/rocm/bin/rocprofv2] Enabling Counter Collection
+   |-> [/opt/rocm/bin/rocprofv2] vcopy testing on GCD 0
+   |-> [/opt/rocm/bin/rocprofv2] Finished allocating vectors on the CPU
+   |-> [/opt/rocm/bin/rocprofv2] Finished allocating vectors on the GPU
+   |-> [/opt/rocm/bin/rocprofv2] Finished copying vectors to the GPU
+   |-> [/opt/rocm/bin/rocprofv2] sw thinks it moved 1.000000 KB per wave
+   |-> [/opt/rocm/bin/rocprofv2] Total threads: 1048576, Grid Size: 4096 block Size:256, Wavefronts:16384:
+   |-> [/opt/rocm/bin/rocprofv2] Launching the  kernel on the GPU
+   |-> [/opt/rocm/bin/rocprofv2] Finished executing kernel
+   |-> [/opt/rocm/bin/rocprofv2] Finished executing kernel
+[profiling] Current input file: tests/workloads/device_inv_int/MI300A_A1/perfmon/SQ_INST_LEVEL_SMEM.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_SMEM
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INST_LEVEL_SMEM
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_ACCUM_PREV_HIRES
+   |-> [/opt/rocm/bin/rocprofv2] Enabling Counter Collection
+   |-> [/opt/rocm/bin/rocprofv2] vcopy testing on GCD 0
+   |-> [/opt/rocm/bin/rocprofv2] Finished allocating vectors on the CPU
+   |-> [/opt/rocm/bin/rocprofv2] Finished allocating vectors on the GPU
+   |-> [/opt/rocm/bin/rocprofv2] Finished copying vectors to the GPU
+   |-> [/opt/rocm/bin/rocprofv2] sw thinks it moved 1.000000 KB per wave
+   |-> [/opt/rocm/bin/rocprofv2] Total threads: 1048576, Grid Size: 4096 block Size:256, Wavefronts:16384:
+   |-> [/opt/rocm/bin/rocprofv2] Launching the  kernel on the GPU
+   |-> [/opt/rocm/bin/rocprofv2] Finished executing kernel
+   |-> [/opt/rocm/bin/rocprofv2] Finished executing kernel
+   |-> [/opt/rocm/bin/rocprofv2] Finished executing kernel
+   |-> [/opt/rocm/bin/rocprofv2] Finished copying the output vector from the GPU to the CPU
+   |-> [/opt/rocm/bin/rocprofv2] Releasing GPU memory
+   |-> [/opt/rocm/bin/rocprofv2] Releasing CPU memory
+   |-> [/opt/rocm/bin/rocprofv2] Results File: "tests/workloads/device_inv_int/MI300A_A1/out/pmc_1/results_SQ_INST_LEVEL_SMEM.csv"
+   |-> [/opt/rocm/bin/rocprofv2] 
+   |-> [/opt/rocm/bin/rocprofv2] The output path for the following counters: tests/workloads/device_inv_int/MI300A_A1/out/pmc_1
+[profiling] Current input file: tests/workloads/device_inv_int/MI300A_A1/perfmon/SQ_INST_LEVEL_VMEM.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VMEM
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INST_LEVEL_VMEM
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_ACCUM_PREV_HIRES
+   |-> [/opt/rocm/bin/rocprofv2] Enabling Counter Collection
+   |-> [/opt/rocm/bin/rocprofv2] vcopy testing on GCD 0
+   |-> [/opt/rocm/bin/rocprofv2] Finished allocating vectors on the CPU
+   |-> [/opt/rocm/bin/rocprofv2] Finished allocating vectors on the GPU
+   |-> [/opt/rocm/bin/rocprofv2] Finished copying vectors to the GPU
+   |-> [/opt/rocm/bin/rocprofv2] sw thinks it moved 1.000000 KB per wave
+[profiling] Current input file: tests/workloads/device_inv_int/MI300A_A1/perfmon/SQ_LEVEL_WAVES.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - GRBM_COUNT
+   |-> [/opt/rocm/bin/rocprofv2] - GRBM_GUI_ACTIVE
+   |-> [/opt/rocm/bin/rocprofv2] - CPC_ME1_BUSY_FOR_PACKET_DECODE
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_CYCLES
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_WAVES
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_WAVE_CYCLES
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_BUSY_CYCLES
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_LEVEL_WAVES
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_ACCUM_PREV_HIRES
+   |-> [/opt/rocm/bin/rocprofv2] Enabling Counter Collection
+   |-> [/opt/rocm/bin/rocprofv2] vcopy testing on GCD 0
+   |-> [/opt/rocm/bin/rocprofv2] Finished allocating vectors on the CPU
+   |-> [/opt/rocm/bin/rocprofv2] Finished allocating vectors on the GPU
+   |-> [/opt/rocm/bin/rocprofv2] Finished copying vectors to the GPU
+   |-> [/opt/rocm/bin/rocprofv2] sw thinks it moved 1.000000 KB per wave
+   |-> [/opt/rocm/bin/rocprofv2] Total threads: 1048576, Grid Size: 4096 block Size:256, Wavefronts:16384:
+   |-> [/opt/rocm/bin/rocprofv2] Launching the  kernel on the GPU
+   |-> [/opt/rocm/bin/rocprofv2] Finished executing kernel
+   |-> [/opt/rocm/bin/rocprofv2] Finished executing kernel
+   |-> [/opt/rocm/bin/rocprofv2] Finished executing kernel
+   |-> [/opt/rocm/bin/rocprofv2] Finished copying the output vector from the GPU to the CPU
+   |-> [/opt/rocm/bin/rocprofv2] Releasing GPU memory
+   |-> [/opt/rocm/bin/rocprofv2] Releasing CPU memory
+   |-> [/opt/rocm/bin/rocprofv2] Results File: "tests/workloads/device_inv_int/MI300A_A1/out/pmc_1/results_SQ_LEVEL_WAVES.csv"
+   |-> [/opt/rocm/bin/rocprofv2] 
+   |-> [/opt/rocm/bin/rocprofv2] The output path for the following counters: tests/workloads/device_inv_int/MI300A_A1/out/pmc_1
+[profiling] Current input file: tests/workloads/device_inv_int/MI300A_A1/perfmon/pmc_perf_0.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_CYCLES
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_BUSY_CYCLES
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_BUSY_CU_CYCLES
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_WAVES
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_WAVE_CYCLES
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_CVT
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VMEM_WR
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VMEM_RD
+[profiling] Current input file: tests/workloads/device_inv_int/MI300A_A1/perfmon/pmc_perf_1.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VMEM
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_SALU
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VSKIPPED
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_ADD_F16
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_MUL_F16
+[profiling] Current input file: tests/workloads/device_inv_int/MI300A_A1/perfmon/pmc_perf_10.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQC_TC_DATA_ATOMIC_REQ
+   |-> [/opt/rocm/bin/rocprofv2] - SQC_TC_STALL
+   |-> [/opt/rocm/bin/rocprofv2] - SQC_TC_REQ
+   |-> [/opt/rocm/bin/rocprofv2] - SQC_DCACHE_REQ_READ_16
+   |-> [/opt/rocm/bin/rocprofv2] - SQC_ICACHE_REQ
+   |-> [/opt/rocm/bin/rocprofv2] - SQC_ICACHE_HITS
+[profiling] Current input file: tests/workloads/device_inv_int/MI300A_A1/perfmon/pmc_perf_11.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQC_DCACHE_INPUT_VALID_READYB
+   |-> [/opt/rocm/bin/rocprofv2] - SQC_DCACHE_ATOMIC
+   |-> [/opt/rocm/bin/rocprofv2] - SQC_DCACHE_REQ_READ_8
+   |-> [/opt/rocm/bin/rocprofv2] - SQC_DCACHE_REQ
+   |-> [/opt/rocm/bin/rocprofv2] - SQC_DCACHE_HITS
+   |-> [/opt/rocm/bin/rocprofv2] - SQC_DCACHE_MISSES
+   |-> [/opt/rocm/bin/rocprofv2] - SQC_DCACHE_MISSES_DUPLICATE
+[profiling] Current input file: tests/workloads/device_inv_int/MI300A_A1/perfmon/pmc_perf_12.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQC_DCACHE_REQ_READ_2
+   |-> [/opt/rocm/bin/rocprofv2] - SQC_DCACHE_REQ_READ_4
+   |-> [/opt/rocm/bin/rocprofv2] Enabling Counter Collection
+   |-> [/opt/rocm/bin/rocprofv2] vcopy testing on GCD 0
+   |-> [/opt/rocm/bin/rocprofv2] Finished allocating vectors on the CPU
+   |-> [/opt/rocm/bin/rocprofv2] Finished allocating vectors on the GPU
+   |-> [/opt/rocm/bin/rocprofv2] Finished copying vectors to the GPU
+   |-> [/opt/rocm/bin/rocprofv2] sw thinks it moved 1.000000 KB per wave
+[profiling] Current input file: tests/workloads/device_inv_int/MI300A_A1/perfmon/pmc_perf_13.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_ATOMIC[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_BUBBLE[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_CYCLE[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_EA0_ATOMIC[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_ATOMIC[1]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_BUBBLE[1]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_CYCLE[1]
+[profiling] Current input file: tests/workloads/device_inv_int/MI300A_A1/perfmon/pmc_perf_14.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_EA0_ATOMIC_LEVEL[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_EA0_RDREQ[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_EA0_RDREQ_32B[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_EA0_RDREQ_LEVEL[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_EA0_ATOMIC_LEVEL[1]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_EA0_RDREQ[1]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_EA0_RDREQ_32B[1]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_EA0_RDREQ_LEVEL[1]
+[profiling] Current input file: tests/workloads/device_inv_int/MI300A_A1/perfmon/pmc_perf_15.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_EA0_WRREQ[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_EA0_WRREQ_64B[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_EA0_WRREQ_LEVEL[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_HIT[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_EA0_WRREQ[1]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_EA0_WRREQ_64B[1]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_EA0_WRREQ_LEVEL[1]
+[profiling] Current input file: tests/workloads/device_inv_int/MI300A_A1/perfmon/pmc_perf_16.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_MISS[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_READ[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_REQ[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_RW_REQ[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_MISS[1]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_READ[1]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_REQ[1]
+[profiling] Current input file: tests/workloads/device_inv_int/MI300A_A1/perfmon/pmc_perf_17.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_TAG_STALL[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_TOO_MANY_EA_WRREQS_STALL[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_WRITE[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_TAG_STALL[1]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_TOO_MANY_EA_WRREQS_STALL[1]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_WRITE[1]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_TAG_STALL[2]
+[profiling] Current input file: tests/workloads/device_inv_int/MI300A_A1/perfmon/pmc_perf_2.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_TRANS_F16
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_ADD_F32
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_MUL_F32
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_FMA_F32
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_TRANS_F32
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_ADD_F64
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_MUL_F64
+[profiling] Current input file: tests/workloads/device_inv_int/MI300A_A1/perfmon/pmc_perf_3.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_TRANS_F64
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_INT32
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_INT64
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_SMEM
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_FLAT
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_LDS
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_GDS
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_EXP_GDS
+[profiling] Current input file: tests/workloads/device_inv_int/MI300A_A1/perfmon/pmc_perf_4.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_BRANCH
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_SENDMSG
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_WAIT_ANY
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_WAIT_INST_ANY
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_ACTIVE_INST_ANY
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_ACTIVE_INST_VMEM
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_ACTIVE_INST_LDS
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_ACTIVE_INST_VALU
+[profiling] Current input file: tests/workloads/device_inv_int/MI300A_A1/perfmon/pmc_perf_5.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_ACTIVE_INST_SCA
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_ACTIVE_INST_EXP_GDS
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_ACTIVE_INST_MISC
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_ACTIVE_INST_FLAT
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INST_CYCLES_VMEM_WR
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INST_CYCLES_VMEM_RD
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INST_CYCLES_SMEM
+[profiling] Current input file: tests/workloads/device_inv_int/MI300A_A1/perfmon/pmc_perf_6.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_THREAD_CYCLES_VALU
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_IFETCH
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_LDS_BANK_CONFLICT
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_LDS_ADDR_CONFLICT
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_LDS_UNALIGNED_STALL
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_WAVES_EQ_64
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_WAVES_LT_64
+[profiling] Current input file: tests/workloads/device_inv_int/MI300A_A1/perfmon/pmc_perf_7.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_WAVES_LT_32
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_WAVES_LT_16
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_ITEMS
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_LDS_MEM_VIOLATIONS
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_LDS_ATOMIC_RETURN
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_LDS_IDX_ACTIVE
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_WAVES_RESTORED
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_WAVES_SAVED
+[profiling] Current input file: tests/workloads/device_inv_int/MI300A_A1/perfmon/pmc_perf_8.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_SMEM_NORM
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_MFMA
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_MFMA_I8
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_MFMA_F16
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_MFMA_BF16
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_MFMA_F32
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_MFMA_F64
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_VALU_MFMA_BUSY_CYCLES
+[profiling] Current input file: tests/workloads/device_inv_int/MI300A_A1/perfmon/pmc_perf_9.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_MFMA_MOPS_I8
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_MFMA_MOPS_F16
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_MFMA_MOPS_BF16
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_MFMA_MOPS_F32
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_MFMA_MOPS_F64
+   |-> [/opt/rocm/bin/rocprofv2] - SQC_TC_INST_REQ
+   |-> [/opt/rocm/bin/rocprofv2] - SQC_TC_DATA_READ_REQ
+   |-> [/opt/rocm/bin/rocprofv2] - SQC_TC_DATA_WRITE_REQ
+[profiling] Current input file: tests/workloads/device_inv_int/MI300A_A1/perfmon/timestamps.txt
+   |-> [/opt/rocm/bin/rocprofv2] vcopy testing on GCD 0
+   |-> [/opt/rocm/bin/rocprofv2] Finished allocating vectors on the CPU
+[roofline] Roofline temporarily disabled in MI300
@@ -0,0 +1,5 @@
+pmc: GRBM_COUNT GRBM_GUI_ACTIVE SQ_WAVES SQ_IFETCH SQ_IFETCH_LEVEL  SQ_ACCUM_PREV_HIRES
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc: SQ_INSTS_LDS SQ_INST_LEVEL_LDS  SQ_ACCUM_PREV_HIRES
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc: SQ_INSTS_SMEM  SQ_INST_LEVEL_SMEM SQ_ACCUM_PREV_HIRES
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc: SQ_INSTS_VMEM  SQ_INST_LEVEL_VMEM SQ_ACCUM_PREV_HIRES
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc: GRBM_COUNT GRBM_GUI_ACTIVE CPC_ME1_BUSY_FOR_PACKET_DECODE SQ_CYCLES SQ_WAVES SQ_WAVE_CYCLES SQ_BUSY_CYCLES SQ_LEVEL_WAVES  SQ_ACCUM_PREV_HIRES
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQ_CYCLES SQ_BUSY_CYCLES SQ_BUSY_CU_CYCLES SQ_WAVES SQ_WAVE_CYCLES SQ_INSTS_VALU_CVT SQ_INSTS_VMEM_WR SQ_INSTS_VMEM_RD GRBM_COUNT GRBM_GUI_ACTIVE TCP_GATE_EN1_sum TCP_GATE_EN2_sum TCP_TD_TCP_STALL_CYCLES_sum TCP_TCR_TCP_STALL_CYCLES_sum TA_TA_BUSY_sum TA_BUFFER_WAVEFRONTS_sum TD_TD_BUSY_sum TD_TC_STALL_sum SPI_CSN_WINDOW_VALID SPI_CSN_BUSY CPC_CPC_STAT_BUSY CPC_CPC_STAT_IDLE CPF_CPF_STAT_BUSY CPF_CPF_STAT_STALL TCC_CYCLE_sum TCC_BUSY_sum TCC_PROBE_sum TCC_PROBE_ALL_sum
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQ_INSTS_VMEM SQ_INSTS_SALU SQ_INSTS_VSKIPPED SQ_INSTS SQ_INSTS_VALU SQ_INSTS_VALU_ADD_F16 SQ_INSTS_VALU_MUL_F16 SQ_INSTS_VALU_FMA_F16 GRBM_SPI_BUSY TCP_READ_TAGCONFLICT_STALL_CYCLES_sum TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum TCP_TA_TCP_STATE_READ_sum TA_BUFFER_READ_WAVEFRONTS_sum TA_BUFFER_WRITE_WAVEFRONTS_sum TD_SPI_STALL_sum TD_LOAD_WAVEFRONT_sum SPI_CSN_NUM_THREADGROUPS SPI_CSN_WAVE CPC_CPC_TCIU_BUSY CPC_CPC_TCIU_IDLE CPF_CPF_TCIU_BUSY CPF_CPF_TCIU_STALL TCC_NC_REQ_sum TCC_UC_REQ_sum TCC_CC_REQ_sum TCC_RW_REQ_sum
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQC_TC_DATA_ATOMIC_REQ SQC_TC_STALL SQC_TC_REQ SQC_DCACHE_REQ_READ_16 SQC_ICACHE_REQ SQC_ICACHE_HITS SQC_ICACHE_MISSES SQC_ICACHE_MISSES_DUPLICATE
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQC_DCACHE_INPUT_VALID_READYB SQC_DCACHE_ATOMIC SQC_DCACHE_REQ_READ_8 SQC_DCACHE_REQ SQC_DCACHE_HITS SQC_DCACHE_MISSES SQC_DCACHE_MISSES_DUPLICATE SQC_DCACHE_REQ_READ_1
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQC_DCACHE_REQ_READ_2 SQC_DCACHE_REQ_READ_4
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  TCC_ATOMIC[0] TCC_BUBBLE[0] TCC_CYCLE[0] TCC_EA0_ATOMIC[0] TCC_ATOMIC[1] TCC_BUBBLE[1] TCC_CYCLE[1] TCC_EA0_ATOMIC[1] TCC_ATOMIC[2] TCC_BUBBLE[2] TCC_CYCLE[2] TCC_EA0_ATOMIC[2] TCC_ATOMIC[3] TCC_BUBBLE[3] TCC_CYCLE[3] TCC_EA0_ATOMIC[3] TCC_ATOMIC[4] TCC_BUBBLE[4] TCC_CYCLE[4] TCC_EA0_ATOMIC[4] TCC_ATOMIC[5] TCC_BUBBLE[5] TCC_CYCLE[5] TCC_EA0_ATOMIC[5] TCC_ATOMIC[6] TCC_BUBBLE[6] TCC_CYCLE[6] TCC_EA0_ATOMIC[6] TCC_ATOMIC[7] TCC_BUBBLE[7] TCC_CYCLE[7] TCC_EA0_ATOMIC[7] TCC_ATOMIC[8] TCC_BUBBLE[8] TCC_CYCLE[8] TCC_EA0_ATOMIC[8] TCC_ATOMIC[9] TCC_BUBBLE[9] TCC_CYCLE[9] TCC_EA0_ATOMIC[9] TCC_ATOMIC[10] TCC_BUBBLE[10] TCC_CYCLE[10] TCC_EA0_ATOMIC[10] TCC_ATOMIC[11] TCC_BUBBLE[11] TCC_CYCLE[11] TCC_EA0_ATOMIC[11] TCC_ATOMIC[12] TCC_BUBBLE[12] TCC_CYCLE[12] TCC_EA0_ATOMIC[12] TCC_ATOMIC[13] TCC_BUBBLE[13] TCC_CYCLE[13] TCC_EA0_ATOMIC[13] TCC_ATOMIC[14] TCC_BUBBLE[14] TCC_CYCLE[14] TCC_EA0_ATOMIC[14] TCC_ATOMIC[15] TCC_BUBBLE[15] TCC_CYCLE[15] TCC_EA0_ATOMIC[15]
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  TCC_EA0_ATOMIC_LEVEL[0] TCC_EA0_RDREQ[0] TCC_EA0_RDREQ_32B[0] TCC_EA0_RDREQ_LEVEL[0] TCC_EA0_ATOMIC_LEVEL[1] TCC_EA0_RDREQ[1] TCC_EA0_RDREQ_32B[1] TCC_EA0_RDREQ_LEVEL[1] TCC_EA0_ATOMIC_LEVEL[2] TCC_EA0_RDREQ[2] TCC_EA0_RDREQ_32B[2] TCC_EA0_RDREQ_LEVEL[2] TCC_EA0_ATOMIC_LEVEL[3] TCC_EA0_RDREQ[3] TCC_EA0_RDREQ_32B[3] TCC_EA0_RDREQ_LEVEL[3] TCC_EA0_ATOMIC_LEVEL[4] TCC_EA0_RDREQ[4] TCC_EA0_RDREQ_32B[4] TCC_EA0_RDREQ_LEVEL[4] TCC_EA0_ATOMIC_LEVEL[5] TCC_EA0_RDREQ[5] TCC_EA0_RDREQ_32B[5] TCC_EA0_RDREQ_LEVEL[5] TCC_EA0_ATOMIC_LEVEL[6] TCC_EA0_RDREQ[6] TCC_EA0_RDREQ_32B[6] TCC_EA0_RDREQ_LEVEL[6] TCC_EA0_ATOMIC_LEVEL[7] TCC_EA0_RDREQ[7] TCC_EA0_RDREQ_32B[7] TCC_EA0_RDREQ_LEVEL[7] TCC_EA0_ATOMIC_LEVEL[8] TCC_EA0_RDREQ[8] TCC_EA0_RDREQ_32B[8] TCC_EA0_RDREQ_LEVEL[8] TCC_EA0_ATOMIC_LEVEL[9] TCC_EA0_RDREQ[9] TCC_EA0_RDREQ_32B[9] TCC_EA0_RDREQ_LEVEL[9] TCC_EA0_ATOMIC_LEVEL[10] TCC_EA0_RDREQ[10] TCC_EA0_RDREQ_32B[10] TCC_EA0_RDREQ_LEVEL[10] TCC_EA0_ATOMIC_LEVEL[11] TCC_EA0_RDREQ[11] TCC_EA0_RDREQ_32B[11] TCC_EA0_RDREQ_LEVEL[11] TCC_EA0_ATOMIC_LEVEL[12] TCC_EA0_RDREQ[12] TCC_EA0_RDREQ_32B[12] TCC_EA0_RDREQ_LEVEL[12] TCC_EA0_ATOMIC_LEVEL[13] TCC_EA0_RDREQ[13] TCC_EA0_RDREQ_32B[13] TCC_EA0_RDREQ_LEVEL[13] TCC_EA0_ATOMIC_LEVEL[14] TCC_EA0_RDREQ[14] TCC_EA0_RDREQ_32B[14] TCC_EA0_RDREQ_LEVEL[14] TCC_EA0_ATOMIC_LEVEL[15] TCC_EA0_RDREQ[15] TCC_EA0_RDREQ_32B[15] TCC_EA0_RDREQ_LEVEL[15]
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  TCC_EA0_WRREQ[0] TCC_EA0_WRREQ_64B[0] TCC_EA0_WRREQ_LEVEL[0] TCC_HIT[0] TCC_EA0_WRREQ[1] TCC_EA0_WRREQ_64B[1] TCC_EA0_WRREQ_LEVEL[1] TCC_HIT[1] TCC_EA0_WRREQ[2] TCC_EA0_WRREQ_64B[2] TCC_EA0_WRREQ_LEVEL[2] TCC_HIT[2] TCC_EA0_WRREQ[3] TCC_EA0_WRREQ_64B[3] TCC_EA0_WRREQ_LEVEL[3] TCC_HIT[3] TCC_EA0_WRREQ[4] TCC_EA0_WRREQ_64B[4] TCC_EA0_WRREQ_LEVEL[4] TCC_HIT[4] TCC_EA0_WRREQ[5] TCC_EA0_WRREQ_64B[5] TCC_EA0_WRREQ_LEVEL[5] TCC_HIT[5] TCC_EA0_WRREQ[6] TCC_EA0_WRREQ_64B[6] TCC_EA0_WRREQ_LEVEL[6] TCC_HIT[6] TCC_EA0_WRREQ[7] TCC_EA0_WRREQ_64B[7] TCC_EA0_WRREQ_LEVEL[7] TCC_HIT[7] TCC_EA0_WRREQ[8] TCC_EA0_WRREQ_64B[8] TCC_EA0_WRREQ_LEVEL[8] TCC_HIT[8] TCC_EA0_WRREQ[9] TCC_EA0_WRREQ_64B[9] TCC_EA0_WRREQ_LEVEL[9] TCC_HIT[9] TCC_EA0_WRREQ[10] TCC_EA0_WRREQ_64B[10] TCC_EA0_WRREQ_LEVEL[10] TCC_HIT[10] TCC_EA0_WRREQ[11] TCC_EA0_WRREQ_64B[11] TCC_EA0_WRREQ_LEVEL[11] TCC_HIT[11] TCC_EA0_WRREQ[12] TCC_EA0_WRREQ_64B[12] TCC_EA0_WRREQ_LEVEL[12] TCC_HIT[12] TCC_EA0_WRREQ[13] TCC_EA0_WRREQ_64B[13] TCC_EA0_WRREQ_LEVEL[13] TCC_HIT[13] TCC_EA0_WRREQ[14] TCC_EA0_WRREQ_64B[14] TCC_EA0_WRREQ_LEVEL[14] TCC_HIT[14] TCC_EA0_WRREQ[15] TCC_EA0_WRREQ_64B[15] TCC_EA0_WRREQ_LEVEL[15] TCC_HIT[15]
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  TCC_MISS[0] TCC_READ[0] TCC_REQ[0] TCC_RW_REQ[0] TCC_MISS[1] TCC_READ[1] TCC_REQ[1] TCC_RW_REQ[1] TCC_MISS[2] TCC_READ[2] TCC_REQ[2] TCC_RW_REQ[2] TCC_MISS[3] TCC_READ[3] TCC_REQ[3] TCC_RW_REQ[3] TCC_MISS[4] TCC_READ[4] TCC_REQ[4] TCC_RW_REQ[4] TCC_MISS[5] TCC_READ[5] TCC_REQ[5] TCC_RW_REQ[5] TCC_MISS[6] TCC_READ[6] TCC_REQ[6] TCC_RW_REQ[6] TCC_MISS[7] TCC_READ[7] TCC_REQ[7] TCC_RW_REQ[7] TCC_MISS[8] TCC_READ[8] TCC_REQ[8] TCC_RW_REQ[8] TCC_MISS[9] TCC_READ[9] TCC_REQ[9] TCC_RW_REQ[9] TCC_MISS[10] TCC_READ[10] TCC_REQ[10] TCC_RW_REQ[10] TCC_MISS[11] TCC_READ[11] TCC_REQ[11] TCC_RW_REQ[11] TCC_MISS[12] TCC_READ[12] TCC_REQ[12] TCC_RW_REQ[12] TCC_MISS[13] TCC_READ[13] TCC_REQ[13] TCC_RW_REQ[13] TCC_MISS[14] TCC_READ[14] TCC_REQ[14] TCC_RW_REQ[14] TCC_MISS[15] TCC_READ[15] TCC_REQ[15] TCC_RW_REQ[15]
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  TCC_TAG_STALL[0] TCC_TOO_MANY_EA_WRREQS_STALL[0] TCC_WRITE[0] TCC_TAG_STALL[1] TCC_TOO_MANY_EA_WRREQS_STALL[1] TCC_WRITE[1] TCC_TAG_STALL[2] TCC_TOO_MANY_EA_WRREQS_STALL[2] TCC_WRITE[2] TCC_TAG_STALL[3] TCC_TOO_MANY_EA_WRREQS_STALL[3] TCC_WRITE[3] TCC_TAG_STALL[4] TCC_TOO_MANY_EA_WRREQS_STALL[4] TCC_WRITE[4] TCC_TAG_STALL[5] TCC_TOO_MANY_EA_WRREQS_STALL[5] TCC_WRITE[5] TCC_TAG_STALL[6] TCC_TOO_MANY_EA_WRREQS_STALL[6] TCC_WRITE[6] TCC_TAG_STALL[7] TCC_TOO_MANY_EA_WRREQS_STALL[7] TCC_WRITE[7] TCC_TAG_STALL[8] TCC_TOO_MANY_EA_WRREQS_STALL[8] TCC_WRITE[8] TCC_TAG_STALL[9] TCC_TOO_MANY_EA_WRREQS_STALL[9] TCC_WRITE[9] TCC_TAG_STALL[10] TCC_TOO_MANY_EA_WRREQS_STALL[10] TCC_WRITE[10] TCC_TAG_STALL[11] TCC_TOO_MANY_EA_WRREQS_STALL[11] TCC_WRITE[11] TCC_TAG_STALL[12] TCC_TOO_MANY_EA_WRREQS_STALL[12] TCC_WRITE[12] TCC_TAG_STALL[13] TCC_TOO_MANY_EA_WRREQS_STALL[13] TCC_WRITE[13] TCC_TAG_STALL[14] TCC_TOO_MANY_EA_WRREQS_STALL[14] TCC_WRITE[14] TCC_TAG_STALL[15] TCC_TOO_MANY_EA_WRREQS_STALL[15] TCC_WRITE[15]
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQ_INSTS_VALU_TRANS_F16 SQ_INSTS_VALU_ADD_F32 SQ_INSTS_VALU_MUL_F32 SQ_INSTS_VALU_FMA_F32 SQ_INSTS_VALU_TRANS_F32 SQ_INSTS_VALU_ADD_F64 SQ_INSTS_VALU_MUL_F64 SQ_INSTS_VALU_FMA_F64 TCP_VOLATILE_sum TCP_TOTAL_ACCESSES_sum TCP_TOTAL_READ_sum TCP_TOTAL_WRITE_sum TA_BUFFER_ATOMIC_WAVEFRONTS_sum TA_BUFFER_TOTAL_CYCLES_sum TD_ATOMIC_WAVEFRONT_sum TD_STORE_WAVEFRONT_sum SPI_RA_REQ_NO_ALLOC SPI_RA_REQ_NO_ALLOC_CSN CPC_CPC_STAT_STALL CPC_UTCL1_STALL_ON_TRANSLATION CPF_CPF_STAT_IDLE CPF_CPF_TCIU_IDLE TCC_REQ_sum TCC_STREAMING_REQ_sum TCC_HIT_sum TCC_MISS_sum
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQ_INSTS_VALU_TRANS_F64 SQ_INSTS_VALU_INT32 SQ_INSTS_VALU_INT64 SQ_INSTS_SMEM SQ_INSTS_FLAT SQ_INSTS_LDS SQ_INSTS_GDS SQ_INSTS_EXP_GDS TCP_TOTAL_ATOMIC_WITH_RET_sum TCP_TOTAL_ATOMIC_WITHOUT_RET_sum TCP_TOTAL_WRITEBACK_INVALIDATES_sum TCP_TOTAL_CACHE_ACCESSES_sum TA_BUFFER_COALESCED_READ_CYCLES_sum TA_BUFFER_COALESCED_WRITE_CYCLES_sum TD_COALESCABLE_WAVEFRONT_sum SPI_RA_RES_STALL_CSN SPI_RA_TMP_STALL_CSN CPC_CPC_UTCL2IU_BUSY CPC_CPC_UTCL2IU_IDLE CPF_CMP_UTCL1_STALL_ON_TRANSLATION TCC_READ_sum TCC_WRITE_sum TCC_ATOMIC_sum TCC_WRITEBACK_sum
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQ_INSTS_BRANCH SQ_INSTS_SENDMSG SQ_WAIT_ANY SQ_WAIT_INST_ANY SQ_ACTIVE_INST_ANY SQ_ACTIVE_INST_VMEM SQ_ACTIVE_INST_LDS SQ_ACTIVE_INST_VALU TCP_UTCL1_TRANSLATION_MISS_sum TCP_UTCL1_TRANSLATION_HIT_sum TCP_UTCL1_PERMISSION_MISS_sum TCP_UTCL1_REQUEST_sum TA_ADDR_STALLED_BY_TC_CYCLES_sum TA_TOTAL_WAVEFRONTS_sum SPI_RA_WAVE_SIMD_FULL_CSN SPI_RA_VGPR_SIMD_FULL_CSN CPC_CPC_UTCL2IU_STALL CPC_ME1_BUSY_FOR_PACKET_DECODE TCC_EA0_WRREQ_sum TCC_EA0_WRREQ_64B_sum TCC_EA0_WR_UNCACHED_32B_sum TCC_EA0_WRREQ_DRAM_sum
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQ_ACTIVE_INST_SCA SQ_ACTIVE_INST_EXP_GDS SQ_ACTIVE_INST_MISC SQ_ACTIVE_INST_FLAT SQ_INST_CYCLES_VMEM_WR SQ_INST_CYCLES_VMEM_RD SQ_INST_CYCLES_SMEM SQ_INST_CYCLES_SALU TCP_TCC_READ_REQ_sum TCP_TCC_WRITE_REQ_sum TCP_TCC_ATOMIC_WITH_RET_REQ_sum TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum TA_ADDR_STALLED_BY_TD_CYCLES_sum TA_DATA_STALLED_BY_TC_CYCLES_sum SPI_RA_SGPR_SIMD_FULL_CSN SPI_RA_LDS_CU_FULL_CSN CPC_ME1_DC0_SPI_BUSY TCC_EA0_RDREQ_sum TCC_EA0_RDREQ_32B_sum TCC_BUBBLE_sum TCC_EA0_RD_UNCACHED_32B_sum
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQ_THREAD_CYCLES_VALU SQ_IFETCH SQ_LDS_BANK_CONFLICT SQ_LDS_ADDR_CONFLICT SQ_LDS_UNALIGNED_STALL SQ_WAVES_EQ_64 SQ_WAVES_LT_64 SQ_WAVES_LT_48 TCP_TCC_NC_READ_REQ_sum TCP_TCC_NC_WRITE_REQ_sum TCP_TCC_NC_ATOMIC_REQ_sum TCP_TCC_UC_READ_REQ_sum TA_FLAT_WAVEFRONTS_sum TA_FLAT_READ_WAVEFRONTS_sum SPI_RA_BAR_CU_FULL_CSN SPI_RA_TGLIM_CU_FULL_CSN TCC_EA0_RDREQ_DRAM_sum TCC_TAG_STALL_sum TCC_NORMAL_WRITEBACK_sum TCC_ALL_TC_OP_WB_WRITEBACK_sum
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQ_WAVES_LT_32 SQ_WAVES_LT_16 SQ_ITEMS SQ_LDS_MEM_VIOLATIONS SQ_LDS_ATOMIC_RETURN SQ_LDS_IDX_ACTIVE SQ_WAVES_RESTORED SQ_WAVES_SAVED TCP_TCC_UC_WRITE_REQ_sum TCP_TCC_UC_ATOMIC_REQ_sum TCP_TCC_CC_READ_REQ_sum TCP_TCC_CC_WRITE_REQ_sum TA_FLAT_WRITE_WAVEFRONTS_sum TA_FLAT_ATOMIC_WAVEFRONTS_sum SPI_RA_WVLIM_STALL_CSN SPI_SWC_CSC_WR TCC_NORMAL_EVICT_sum TCC_ALL_TC_OP_INV_EVICT_sum TCC_TOO_MANY_EA_WRREQS_STALL_sum TCC_EA0_ATOMIC_sum
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQ_INSTS_SMEM_NORM SQ_INSTS_MFMA SQ_INSTS_VALU_MFMA_I8 SQ_INSTS_VALU_MFMA_F16 SQ_INSTS_VALU_MFMA_BF16 SQ_INSTS_VALU_MFMA_F32 SQ_INSTS_VALU_MFMA_F64 SQ_VALU_MFMA_BUSY_CYCLES TCP_TCC_CC_ATOMIC_REQ_sum TCP_TCC_RW_READ_REQ_sum TCP_TCC_RW_WRITE_REQ_sum TCP_TCC_RW_ATOMIC_REQ_sum SPI_VWC_CSC_WR SPI_RA_BULKY_CU_FULL_CSN TCC_EA0_RDREQ_LEVEL_sum TCC_EA0_WRREQ_LEVEL_sum TCC_EA0_ATOMIC_LEVEL_sum TCC_EA0_WRREQ_STALL_sum
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQ_INSTS_VALU_MFMA_MOPS_I8 SQ_INSTS_VALU_MFMA_MOPS_F16 SQ_INSTS_VALU_MFMA_MOPS_BF16 SQ_INSTS_VALU_MFMA_MOPS_F32 SQ_INSTS_VALU_MFMA_MOPS_F64 SQC_TC_INST_REQ SQC_TC_DATA_READ_REQ SQC_TC_DATA_WRITE_REQ TCP_PENDING_STALL_CYCLES_sum
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,5 @@
+pmc:
+
+gpu:
+range:
+kernel:
@@ -0,0 +1,4 @@
+Dispatch_ID,GPU_ID,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,Wave_Size,Kernel_Name,Correlation_ID,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_EA0_WRREQ_64B_sum,TCC_EA0_WRREQ_DRAM_sum,TCC_EA0_WRREQ_sum,TCC_EA0_WR_UNCACHED_32B_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_TRANSLATION_MISS_sum,Wave_Size_1,Correlation_ID_1,XCC_Index,TCC_EA0_WRREQ[0],TCC_EA0_WRREQ_64B[0],TCC_EA0_WRREQ_LEVEL[0],TCC_HIT[0],TCC_EA0_WRREQ[1],TCC_EA0_WRREQ_64B[1],TCC_EA0_WRREQ_LEVEL[1],TCC_HIT[1],TCC_EA0_WRREQ[2],TCC_EA0_WRREQ_64B[2],TCC_EA0_WRREQ_LEVEL[2],TCC_HIT[2],TCC_EA0_WRREQ[3],TCC_EA0_WRREQ_64B[3],TCC_EA0_WRREQ_LEVEL[3],TCC_HIT[3],TCC_EA0_WRREQ[4],TCC_EA0_WRREQ_64B[4],TCC_EA0_WRREQ_LEVEL[4],TCC_HIT[4],TCC_EA0_WRREQ[5],TCC_EA0_WRREQ_64B[5],TCC_EA0_WRREQ_LEVEL[5],TCC_HIT[5],TCC_EA0_WRREQ[6],TCC_EA0_WRREQ_64B[6],TCC_EA0_WRREQ_LEVEL[6],TCC_HIT[6],TCC_EA0_WRREQ[7],TCC_EA0_WRREQ_64B[7],TCC_EA0_WRREQ_LEVEL[7],TCC_HIT[7],TCC_EA0_WRREQ[8],TCC_EA0_WRREQ_64B[8],TCC_EA0_WRREQ_LEVEL[8],TCC_HIT[8],TCC_EA0_WRREQ[9],TCC_EA0_WRREQ_64B[9],TCC_EA0_WRREQ_LEVEL[9],TCC_HIT[9],TCC_EA0_WRREQ[10],TCC_EA0_WRREQ_64B[10],TCC_EA0_WRREQ_LEVEL[10],TCC_HIT[10],TCC_EA0_WRREQ[11],TCC_EA0_WRREQ_64B[11],TCC_EA0_WRREQ_LEVEL[11],TCC_HIT[11],TCC_EA0_WRREQ[12],TCC_EA0_WRREQ_64B[12],TCC_EA0_WRREQ_LEVEL[12],TCC_HIT[12],TCC_EA0_WRREQ[13],TCC_EA0_WRREQ_64B[13],TCC_EA0_WRREQ_LEVEL[13],TCC_HIT[13],TCC_EA0_WRREQ[14],TCC_EA0_WRREQ_64B[14],TCC_EA0_WRREQ_LEVEL[14],TCC_HIT[14],TCC_EA0_WRREQ[15],TCC_EA0_WRREQ_64B[15],TCC_EA0_WRREQ_LEVEL[15],TCC_HIT[15],TCC_EA0_WRREQ[16],TCC_EA0_WRREQ_64B[16],TCC_EA0_WRREQ_LEVEL[16],TCC_HIT[16],TCC_EA0_WRREQ[17],TCC_EA0_WRREQ_64B[17],TCC_EA0_WRREQ_LEVEL[17],TCC_HIT[17],TCC_EA0_WRREQ[18],TCC_EA0_WRREQ_64B[18],TCC_EA0_WRREQ_LEVEL[18],TCC_HIT[18],TCC_EA0_WRREQ[19],TCC_EA0_WRREQ_64B[19],TCC_EA0_WRREQ_LEVEL[19],TCC_HIT[19],TCC_EA0_WRREQ[20],TCC_EA0_WRREQ_64B[20],TCC_EA0_WRREQ_LEVEL[20],TCC_HIT[20],TCC_EA0_WRREQ[21],TCC_EA0_WRREQ_64B[21],TCC_EA0_WRREQ_LEVEL[21],TCC_HIT[21],TCC_EA0_WRREQ[22],TCC_EA0_WRREQ_64B[22],TCC_EA0_WRREQ_LEVEL[22],TCC_HIT[22],TCC_EA0_WRREQ[23],TCC_EA0_WRREQ_64B[23],TCC_EA0_WRREQ_LEVEL[23],TCC_HIT[23],TCC_EA0_WRREQ[24],TCC_EA0_WRREQ_64B[24],TCC_EA0_WRREQ_LEVEL[24],TCC_HIT[24],TCC_EA0_WRREQ[25],TCC_EA0_WRREQ_64B[25],TCC_EA0_WRREQ_LEVEL[25],TCC_HIT[25],TCC_EA0_WRREQ[26],TCC_EA0_WRREQ_64B[26],TCC_EA0_WRREQ_LEVEL[26],TCC_HIT[26],TCC_EA0_WRREQ[27],TCC_EA0_WRREQ_64B[27],TCC_EA0_WRREQ_LEVEL[27],TCC_HIT[27],TCC_EA0_WRREQ[28],TCC_EA0_WRREQ_64B[28],TCC_EA0_WRREQ_LEVEL[28],TCC_HIT[28],TCC_EA0_WRREQ[29],TCC_EA0_WRREQ_64B[29],TCC_EA0_WRREQ_LEVEL[29],TCC_HIT[29],TCC_EA0_WRREQ[30],TCC_EA0_WRREQ_64B[30],TCC_EA0_WRREQ_LEVEL[30],TCC_HIT[30],TCC_EA0_WRREQ[31],TCC_EA0_WRREQ_64B[31],TCC_EA0_WRREQ_LEVEL[31],TCC_HIT[31],TCC_EA0_WRREQ[32],TCC_EA0_WRREQ_64B[32],TCC_EA0_WRREQ_LEVEL[32],TCC_HIT[32],TCC_EA0_WRREQ[33],TCC_EA0_WRREQ_64B[33],TCC_EA0_WRREQ_LEVEL[33],TCC_HIT[33],TCC_EA0_WRREQ[34],TCC_EA0_WRREQ_64B[34],TCC_EA0_WRREQ_LEVEL[34],TCC_HIT[34],TCC_EA0_WRREQ[35],TCC_EA0_WRREQ_64B[35],TCC_EA0_WRREQ_LEVEL[35],TCC_HIT[35],TCC_EA0_WRREQ[36],TCC_EA0_WRREQ_64B[36],TCC_EA0_WRREQ_LEVEL[36],TCC_HIT[36],TCC_EA0_WRREQ[37],TCC_EA0_WRREQ_64B[37],TCC_EA0_WRREQ_LEVEL[37],TCC_HIT[37],TCC_EA0_WRREQ[38],TCC_EA0_WRREQ_64B[38],TCC_EA0_WRREQ_LEVEL[38],TCC_HIT[38],TCC_EA0_WRREQ[39],TCC_EA0_WRREQ_64B[39],TCC_EA0_WRREQ_LEVEL[39],TCC_HIT[39],TCC_EA0_WRREQ[40],TCC_EA0_WRREQ_64B[40],TCC_EA0_WRREQ_LEVEL[40],TCC_HIT[40],TCC_EA0_WRREQ[41],TCC_EA0_WRREQ_64B[41],TCC_EA0_WRREQ_LEVEL[41],TCC_HIT[41],TCC_EA0_WRREQ[42],TCC_EA0_WRREQ_64B[42],TCC_EA0_WRREQ_LEVEL[42],TCC_HIT[42],TCC_EA0_WRREQ[43],TCC_EA0_WRREQ_64B[43],TCC_EA0_WRREQ_LEVEL[43],TCC_HIT[43],TCC_EA0_WRREQ[44],TCC_EA0_WRREQ_64B[44],TCC_EA0_WRREQ_LEVEL[44],TCC_HIT[44],TCC_EA0_WRREQ[45],TCC_EA0_WRREQ_64B[45],TCC_EA0_WRREQ_LEVEL[45],TCC_HIT[45],TCC_EA0_WRREQ[46],TCC_EA0_WRREQ_64B[46],TCC_EA0_WRREQ_LEVEL[46],TCC_HIT[46],TCC_EA0_WRREQ[47],TCC_EA0_WRREQ_64B[47],TCC_EA0_WRREQ_LEVEL[47],TCC_HIT[47],TCC_EA0_WRREQ[48],TCC_EA0_WRREQ_64B[48],TCC_EA0_WRREQ_LEVEL[48],TCC_HIT[48],TCC_EA0_WRREQ[49],TCC_EA0_WRREQ_64B[49],TCC_EA0_WRREQ_LEVEL[49],TCC_HIT[49],TCC_EA0_WRREQ[50],TCC_EA0_WRREQ_64B[50],TCC_EA0_WRREQ_LEVEL[50],TCC_HIT[50],TCC_EA0_WRREQ[51],TCC_EA0_WRREQ_64B[51],TCC_EA0_WRREQ_LEVEL[51],TCC_HIT[51],TCC_EA0_WRREQ[52],TCC_EA0_WRREQ_64B[52],TCC_EA0_WRREQ_LEVEL[52],TCC_HIT[52],TCC_EA0_WRREQ[53],TCC_EA0_WRREQ_64B[53],TCC_EA0_WRREQ_LEVEL[53],TCC_HIT[53],TCC_EA0_WRREQ[54],TCC_EA0_WRREQ_64B[54],TCC_EA0_WRREQ_LEVEL[54],TCC_HIT[54],TCC_EA0_WRREQ[55],TCC_EA0_WRREQ_64B[55],TCC_EA0_WRREQ_LEVEL[55],TCC_HIT[55],TCC_EA0_WRREQ[56],TCC_EA0_WRREQ_64B[56],TCC_EA0_WRREQ_LEVEL[56],TCC_HIT[56],TCC_EA0_WRREQ[57Linha truncada
+0,11995,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",0,16384.0,16384.0,11690943.0,997614.0,278528.0,0.0,0.0,98304.0,355819.0,0.0,0.0,459465.0,201405.0,32768.0,131072.0,131072.0,131072.0,0.0,0.0,524288.0,453984.0,1820.0,64,0,0,1368.0,1368.0,522139.0,684.0,1368.0,1368.0,533671.0,684.0,1368.0,1368.0,532641.0,684.0,1368.0,1368.0,540306.0,684.0,1368.0,1368.0,534375.0,742.0,1368.0,1368.0,538464.0,684.0,1368.0,1368.0,542017.0,684.0,1368.0,1368.0,536845.0,684.0,1364.0,1364.0,526616.0,682.0,1364.0,1364.0,535201.0,682.0,1364.0,1364.0,545280.0,682.0,1364.0,1364.0,545161.0,701.0,1364.0,1364.0,540558.0,682.0,1364.0,1364.0,544311.0,682.0,1364.0,1364.0,556462.0,682.0,1364.0,1364.0,553126.0,682.0,1368.0,1368.0,527358.0,684.0,1368.0,1368.0,533758.0,684.0,1368.0,1368.0,546559.0,684.0,1368.0,1368.0,553248.0,703.0,1368.0,1368.0,539040.0,684.0,1368.0,1368.0,542265.0,684.0,1368.0,1368.0,557638.0,684.0,1368.0,1368.0,552265.0,684.0,1364.0,1364.0,527696.0,682.0,1364.0,1364.0,539097.0,682.0,1364.0,1364.0,538734.0,682.0,1364.0,1364.0,544533.0,682.0,1364.0,1364.0,537584.0,740.0,1364.0,1364.0,542440.0,682.0,1364.0,1364.0,547210.0,682.0,1364.0,1364.0,543434.0,682.0,1364.0,1364.0,544025.0,682.0,1364.0,1364.0,549699.0,682.0,1364.0,1364.0,562970.0,682.0,1364.0,1364.0,562011.0,701.0,1364.0,1364.0,544625.0,682.0,1364.0,1364.0,547381.0,682.0,1364.0,1364.0,564248.0,682.0,1364.0,1364.0,559747.0,682.0,1368.0,1368.0,529413.0,684.0,1368.0,1368.0,541628.0,684.0,1368.0,1368.0,541561.0,684.0,1368.0,1368.0,550487.0,684.0,1368.0,1368.0,537791.0,742.0,1368.0,1368.0,540596.0,684.0,1368.0,1368.0,549799.0,684.0,1368.0,1368.0,545474.0,684.0,1364.0,1364.0,541057.0,682.0,1364.0,1364.0,554558.0,682.0,1364.0,1364.0,550594.0,682.0,1364.0,1364.0,552718.0,682.0,1364.0,1364.0,546944.0,740.0,1364.0,1364.0,550463.0,682.0,1364.0,1364.0,560642.0,682.0,1364.0,1364.0,555106.0,682.0,1368.0,1368.0,530054.0,684.0,1368.0,1368.0,537601.0,684.0,1368.0,1368.0,549382.0,684.0,1368.0,1368.0,548354.0,703.0,1368.0,1368.0,538682.0,684.0,1368.0,1368.0,541630.0,684.0,1368.0,1368.0,555633.0,684.0,1368.0,1368.0,550344.0,684.0,1368.0,1368.0,543484.0,684.0,1368.0,1368.0,554525.0,684.0,1368.0,1368.0,546891.0,684.0,1368.0,1368.0,553675.0,703.0,1368.0,1368.0,550947.0,684.0,1368.0,1368.0,550969.0,684.0,1368.0,1368.0,562035.0,684.0,1368.0,1368.0,557039.0,684.0,1360.0,1360.0,539820.0,680.0,1360.0,1360.0,547197.0,680.0,1360.0,1360.0,556511.0,680.0,1360.0,1360.0,555476.0,680.0,1360.0,1360.0,548952.0,738.0,1360.0,1360.0,552944.0,680.0,1360.0,1360.0,567526.0,680.0,1360.0,1360.0,562164.0,680.0,1368.0,1368.0,546970.0,684.0,1368.0,1368.0,554281.0,684.0,1368.0,1368.0,563107.0,684.0,1368.0,1368.0,561138.0,684.0,1368.0,1368.0,555184.0,742.0,1368.0,1368.0,559394.0,684.0,1368.0,1368.0,572628.0,684.0,1368.0,1368.0,569134.0,684.0,1360.0,1360.0,544819.0,680.0,1360.0,1360.0,559044.0,680.0,1360.0,1360.0,552512.0,680.0,1360.0,1360.0,560062.0,699.0,1360.0,1360.0,550105.0,680.0,1360.0,1360.0,553556.0,680.0,1360.0,1360.0,561569.0,680.0,1360.0,1360.0,557142.0,680.0,64,0,6291456.0,65536.0,0.0,0.0,0.0,16384.0,0.0,0.0,0.0,0.0,16384.0,32768.0,49424.0,65602.0,16112.0,83967.0,0.0,0.0,0.0,0.0,64,0,0,899.0,0.0,1360.0,750.0,0.0,1360.0,755.0,0.0,1360.0,1000.0,0.0,1360.0,423.0,0.0,1360.0,856.0,0.0,1360.0,267.0,0.0,1360.0,244.0,0.0,1360.0,734.0,0.0,1368.0,948.0,0.0,1368.0,740.0,0.0,1368.0,644.0,0.0,1368.0,145.0,0.0,1368.0,133.0,0.0,1368.0,307.0,0.0,1368.0,256.0,0.0,1368.0,628.0,0.0,1360.0,824.0,0.0,1360.0,821.0,0.0,1360.0,489.0,0.0,1360.0,311.0,0.0,1360.0,251.0,0.0,1360.0,330.0,0.0,1360.0,297.0,0.0,1360.0,701.0,0.0,1368.0,565.0,0.0,1368.0,502.0,0.0,1368.0,712.0,0.0,1368.0,277.0,0.0,1368.0,592.0,0.0,1368.0,141.0,0.0,1368.0,126.0,0.0,1368.0,888.0,0.0,1364.0,676.0,0.0,1364.0,884.0,0.0,1364.0,430.0,0.0,1364.0,130.0,0.0,1364.0,123.0,0.0,1364.0,219.0,0.0,1364.0,211.0,0.0,1364.0,981.0,0.0,1368.0,825.0,0.0,1368.0,702.0,0.0,1368.0,912.0,0.0,1368.0,380.0,0.0,1368.0,848.0,0.0,1368.0,278.0,0.0,1368.0,241.0,0.0,1368.0,875.0,0.0,1364.0,646.0,0.0,1364.0,741.0,0.0,1364.0,978.0,0.0,1364.0,356.0,0.0,1364.0,870.0,0.0,1364.0,149.0,0.0,1364.0,135.0,0.0,1364.0,887.0,0.0,1368.0,674.0,0.0,1368.0,944.0,0.0,1368.0,467.0,0.0,1368.0,270.0,0.0,1368.0,264.0,0.0,1368.0,240.0,0.0,1368.0,218.0,0.0,1368.0,1209.0,0.0,1364.0,1258.0,0.0,1364.0,1183.0,0.0,1364.0,788.0,0.0,1364.0,562.0,0.0,1364.0,555.0,0.0,1364.0,674.0,0.0,1364.0,600.0,0.0,1364.0,1212.0,0.0,1368.0,1179.0,0.0,1368.0,1116.0,0.0,1368.0,1262.0,0.0,1368.0,827.0,0.0,1368.0,1197.0,0.0,1368.0,676.0,0.0,1368.0,656.0,0.0,1368.0,800.0,0.0,1364.0,731.0,0.0,1364.0,605.0,0.0,1364.0,794.0,0.0,1364.0,337.0,0.0,1364.0,910.0,0.0,1364.0,228.0,0.0,1364.0,244.0,0.0,1364.0,1163.0,0.0,1368.0,1240.0,0.0,1368.0,1208.0,0.0,1368.0,648.0,0.0,1368.0,654.0,0.0,1368.0,615.0,0.0,1368.0,582.0,0.0,1368.0,539.0,0.0,1368.0,64,0,0.0,49152.0,32768.0,65536.0,32768.0,0.0,0.0,0.0,12241.0,0.0,510.0,607116.0,78.0,0.0,0.0,0.0,66074.0,65536.0,131072.0,0.0,0.0,524288.0,228.0,0.0,64,0,0.0,0.0,1048576.0,0.0,0.0,0Linha truncada
+1,11995,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",0,16384.0,16384.0,9762750.0,1033508.0,278528.0,0.0,0.0,98304.0,256117.0,0.0,0.0,467219.0,206850.0,32768.0,131072.0,131072.0,131072.0,0.0,0.0,524288.0,454364.0,1824.0,64,0,0,1364.0,1364.0,553173.0,682.0,1364.0,1364.0,562582.0,682.0,1364.0,1364.0,567419.0,682.0,1364.0,1364.0,578488.0,682.0,1364.0,1364.0,563718.0,682.0,1364.0,1364.0,574598.0,682.0,1364.0,1364.0,572066.0,682.0,1364.0,1364.0,565585.0,682.0,1368.0,1368.0,583854.0,684.0,1368.0,1368.0,590123.0,684.0,1368.0,1368.0,602067.0,684.0,1368.0,1368.0,601831.0,703.0,1368.0,1368.0,588663.0,684.0,1368.0,1368.0,596838.0,684.0,1368.0,1368.0,617461.0,684.0,1368.0,1368.0,612233.0,684.0,1364.0,1364.0,568208.0,682.0,1364.0,1364.0,576062.0,682.0,1364.0,1364.0,581310.0,682.0,1364.0,1364.0,582493.0,701.0,1364.0,1364.0,582276.0,682.0,1364.0,1364.0,586185.0,682.0,1364.0,1364.0,606001.0,682.0,1364.0,1364.0,610253.0,682.0,1368.0,1368.0,564548.0,684.0,1368.0,1368.0,578247.0,684.0,1368.0,1368.0,577881.0,684.0,1368.0,1368.0,588427.0,684.0,1368.0,1368.0,580138.0,684.0,1368.0,1368.0,585881.0,684.0,1368.0,1368.0,583334.0,684.0,1368.0,1368.0,577858.0,684.0,1368.0,1368.0,560044.0,684.0,1368.0,1368.0,567921.0,684.0,1368.0,1368.0,578603.0,684.0,1368.0,1368.0,577692.0,703.0,1368.0,1368.0,567486.0,684.0,1368.0,1368.0,571410.0,684.0,1368.0,1368.0,591999.0,684.0,1368.0,1368.0,588792.0,684.0,1364.0,1364.0,569109.0,682.0,1364.0,1364.0,581489.0,682.0,1364.0,1364.0,584540.0,682.0,1364.0,1364.0,582990.0,682.0,1364.0,1364.0,572764.0,682.0,1364.0,1364.0,575958.0,682.0,1364.0,1364.0,583845.0,682.0,1364.0,1364.0,577975.0,682.0,1360.0,1360.0,567276.0,680.0,1360.0,1360.0,576823.0,680.0,1360.0,1360.0,578125.0,680.0,1360.0,1360.0,579621.0,680.0,1360.0,1360.0,566469.0,680.0,1360.0,1360.0,582828.0,680.0,1360.0,1360.0,586143.0,680.0,1360.0,1360.0,578706.0,680.0,1368.0,1368.0,576167.0,684.0,1368.0,1368.0,586999.0,684.0,1368.0,1368.0,585754.0,684.0,1368.0,1368.0,584857.0,703.0,1368.0,1368.0,579570.0,684.0,1368.0,1368.0,583546.0,684.0,1368.0,1368.0,602542.0,684.0,1368.0,1368.0,602689.0,684.0,1360.0,1360.0,549398.0,680.0,1360.0,1360.0,562603.0,680.0,1360.0,1360.0,562556.0,680.0,1360.0,1360.0,570809.0,699.0,1360.0,1360.0,560662.0,680.0,1360.0,1360.0,565081.0,680.0,1360.0,1360.0,570428.0,680.0,1360.0,1360.0,567339.0,680.0,1368.0,1368.0,562210.0,684.0,1368.0,1368.0,568736.0,684.0,1368.0,1368.0,586070.0,684.0,1368.0,1368.0,582519.0,684.0,1368.0,1368.0,571686.0,684.0,1368.0,1368.0,575596.0,684.0,1368.0,1368.0,589648.0,684.0,1368.0,1368.0,584767.0,684.0,1368.0,1368.0,590487.0,684.0,1368.0,1368.0,594240.0,684.0,1368.0,1368.0,597878.0,684.0,1368.0,1368.0,597463.0,684.0,1368.0,1368.0,604452.0,684.0,1368.0,1368.0,608680.0,684.0,1368.0,1368.0,607140.0,684.0,1368.0,1368.0,600641.0,684.0,1364.0,1364.0,554578.0,682.0,1364.0,1364.0,561372.0,682.0,1364.0,1364.0,559095.0,682.0,1364.0,1364.0,565959.0,701.0,1364.0,1364.0,563360.0,682.0,1364.0,1364.0,568957.0,682.0,1364.0,1364.0,565619.0,682.0,1364.0,1364.0,564319.0,682.0,64,0,6291456.0,65536.0,0.0,0.0,0.0,16384.0,0.0,0.0,0.0,0.0,16384.0,32768.0,48688.0,65608.0,16848.0,112749.0,0.0,0.0,0.0,0.0,64,0,0,518.0,0.0,1368.0,493.0,0.0,1368.0,465.0,0.0,1368.0,497.0,0.0,1368.0,448.0,0.0,1368.0,447.0,0.0,1368.0,409.0,0.0,1368.0,379.0,0.0,1368.0,369.0,0.0,1360.0,421.0,0.0,1360.0,445.0,0.0,1360.0,352.0,0.0,1360.0,332.0,0.0,1360.0,314.0,0.0,1360.0,346.0,0.0,1360.0,335.0,0.0,1360.0,272.0,0.0,1364.0,343.0,0.0,1364.0,419.0,0.0,1364.0,275.0,0.0,1364.0,453.0,0.0,1364.0,415.0,0.0,1364.0,274.0,0.0,1364.0,244.0,0.0,1364.0,678.0,0.0,1368.0,642.0,0.0,1368.0,805.0,0.0,1368.0,804.0,0.0,1368.0,758.0,0.0,1368.0,846.0,0.0,1368.0,876.0,0.0,1368.0,825.0,0.0,1368.0,630.0,0.0,1368.0,652.0,0.0,1368.0,593.0,0.0,1368.0,706.0,0.0,1368.0,371.0,0.0,1368.0,396.0,0.0,1368.0,575.0,0.0,1368.0,552.0,0.0,1368.0,240.0,0.0,1364.0,209.0,0.0,1364.0,156.0,0.0,1364.0,155.0,0.0,1364.0,189.0,0.0,1364.0,211.0,0.0,1364.0,305.0,0.0,1364.0,264.0,0.0,1364.0,501.0,0.0,1368.0,530.0,0.0,1368.0,575.0,0.0,1368.0,596.0,0.0,1368.0,456.0,0.0,1368.0,498.0,0.0,1368.0,539.0,0.0,1368.0,506.0,0.0,1368.0,747.0,0.0,1364.0,714.0,0.0,1364.0,690.0,0.0,1364.0,686.0,0.0,1364.0,669.0,0.0,1364.0,627.0,0.0,1364.0,785.0,0.0,1364.0,700.0,0.0,1364.0,410.0,0.0,1368.0,411.0,0.0,1368.0,390.0,0.0,1368.0,312.0,0.0,1368.0,294.0,0.0,1368.0,284.0,0.0,1368.0,360.0,0.0,1368.0,338.0,0.0,1368.0,721.0,0.0,1364.0,751.0,0.0,1364.0,727.0,0.0,1364.0,737.0,0.0,1364.0,725.0,0.0,1364.0,764.0,0.0,1364.0,789.0,0.0,1364.0,763.0,0.0,1364.0,318.0,0.0,1360.0,342.0,0.0,1360.0,401.0,0.0,1360.0,387.0,0.0,1360.0,430.0,0.0,1360.0,459.0,0.0,1360.0,384.0,0.0,1360.0,360.0,0.0,1360.0,480.0,0.0,1368.0,505.0,0.0,1368.0,474.0,0.0,1368.0,463.0,0.0,1368.0,554.0,0.0,1368.0,535.0,0.0,1368.0,436.0,0.0,1368.0,367.0,0.0,1368.0,64,0,0.0,49152.0,32768.0,65536.0,32768.0,0.0,0.0,0.0,8731.0,0.0,7934.0,587025.0,901.0,0.0,0.0,0.0,65736.0,65536.0,131072.0,0.0,0.0,524288.0,228.0,0.0,64,0,0.0,0.0,1048576.0,0.0,0.0,0.0,0.0,0.0Linha truncada
+2,11995,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",0,16384.0,16384.0,9791848.0,1014160.0,278528.0,0.0,0.0,98304.0,256656.0,0.0,0.0,455148.0,203949.0,32768.0,131072.0,131072.0,131072.0,0.0,0.0,524288.0,454757.0,1824.0,64,0,0,1368.0,1368.0,562270.0,684.0,1368.0,1368.0,571974.0,684.0,1368.0,1368.0,568855.0,684.0,1368.0,1368.0,572349.0,684.0,1368.0,1368.0,565087.0,684.0,1368.0,1368.0,572615.0,684.0,1368.0,1368.0,579323.0,684.0,1368.0,1368.0,576037.0,684.0,1364.0,1364.0,574241.0,682.0,1364.0,1364.0,582780.0,682.0,1364.0,1364.0,588536.0,682.0,1364.0,1364.0,592133.0,701.0,1364.0,1364.0,580363.0,682.0,1364.0,1364.0,585555.0,682.0,1364.0,1364.0,602859.0,682.0,1364.0,1364.0,599059.0,682.0,1368.0,1368.0,554998.0,684.0,1368.0,1368.0,565504.0,684.0,1368.0,1368.0,577394.0,684.0,1368.0,1368.0,582175.0,703.0,1368.0,1368.0,569337.0,684.0,1368.0,1368.0,575925.0,684.0,1368.0,1368.0,585396.0,684.0,1368.0,1368.0,582083.0,684.0,1364.0,1364.0,566783.0,682.0,1364.0,1364.0,577624.0,682.0,1364.0,1364.0,571567.0,682.0,1364.0,1364.0,577170.0,682.0,1364.0,1364.0,570618.0,682.0,1364.0,1364.0,573977.0,682.0,1364.0,1364.0,582164.0,682.0,1364.0,1364.0,581146.0,682.0,1368.0,1368.0,570248.0,684.0,1368.0,1368.0,580469.0,684.0,1368.0,1368.0,593412.0,684.0,1368.0,1368.0,592736.0,703.0,1368.0,1368.0,580653.0,684.0,1368.0,1368.0,580529.0,684.0,1368.0,1368.0,591367.0,684.0,1368.0,1368.0,591746.0,684.0,1360.0,1360.0,559102.0,680.0,1360.0,1360.0,573375.0,680.0,1360.0,1360.0,575869.0,680.0,1360.0,1360.0,580330.0,680.0,1360.0,1360.0,566310.0,680.0,1360.0,1360.0,571572.0,680.0,1360.0,1360.0,580128.0,680.0,1360.0,1360.0,574093.0,680.0,1368.0,1368.0,569899.0,684.0,1368.0,1368.0,583604.0,684.0,1368.0,1368.0,583275.0,684.0,1368.0,1368.0,589453.0,684.0,1368.0,1368.0,579207.0,684.0,1368.0,1368.0,578541.0,684.0,1368.0,1368.0,585798.0,684.0,1368.0,1368.0,581736.0,684.0,1360.0,1360.0,569686.0,680.0,1360.0,1360.0,581100.0,680.0,1360.0,1360.0,590615.0,680.0,1360.0,1360.0,588839.0,699.0,1360.0,1360.0,578698.0,680.0,1360.0,1360.0,579985.0,680.0,1360.0,1360.0,593029.0,680.0,1360.0,1360.0,591868.0,680.0,1364.0,1364.0,551521.0,682.0,1364.0,1364.0,561335.0,682.0,1364.0,1364.0,552203.0,682.0,1364.0,1364.0,557048.0,701.0,1364.0,1364.0,554461.0,682.0,1364.0,1364.0,558836.0,682.0,1364.0,1364.0,567788.0,682.0,1364.0,1364.0,563729.0,682.0,1368.0,1368.0,586277.0,684.0,1368.0,1368.0,594709.0,684.0,1368.0,1368.0,592472.0,684.0,1368.0,1368.0,596051.0,684.0,1368.0,1368.0,593117.0,684.0,1368.0,1368.0,595305.0,684.0,1368.0,1368.0,606911.0,684.0,1368.0,1368.0,600492.0,684.0,1364.0,1364.0,549203.0,682.0,1364.0,1364.0,558020.0,682.0,1364.0,1364.0,575069.0,682.0,1364.0,1364.0,574311.0,682.0,1364.0,1364.0,554062.0,682.0,1364.0,1364.0,556987.0,682.0,1364.0,1364.0,570590.0,682.0,1364.0,1364.0,567519.0,682.0,1368.0,1368.0,585536.0,684.0,1368.0,1368.0,596539.0,684.0,1368.0,1368.0,594917.0,684.0,1368.0,1368.0,602948.0,703.0,1368.0,1368.0,594540.0,684.0,1368.0,1368.0,596588.0,684.0,1368.0,1368.0,615936.0,684.0,1368.0,1368.0,610653.0,684.0,64,0,6291456.0,65536.0,0.0,0.0,0.0,16384.0,0.0,0.0,0.0,0.0,16384.0,32768.0,48703.0,65624.0,16833.0,107774.0,0.0,0.0,0.0,0.0,64,0,0,614.0,0.0,1368.0,591.0,0.0,1368.0,541.0,0.0,1368.0,581.0,0.0,1368.0,632.0,0.0,1368.0,675.0,0.0,1368.0,753.0,0.0,1368.0,745.0,0.0,1368.0,231.0,0.0,1364.0,248.0,0.0,1364.0,163.0,0.0,1364.0,207.0,0.0,1364.0,501.0,0.0,1364.0,422.0,0.0,1364.0,319.0,0.0,1364.0,262.0,0.0,1364.0,664.0,0.0,1368.0,672.0,0.0,1368.0,713.0,0.0,1368.0,644.0,0.0,1368.0,734.0,0.0,1368.0,701.0,0.0,1368.0,806.0,0.0,1368.0,680.0,0.0,1368.0,412.0,0.0,1364.0,421.0,0.0,1364.0,306.0,0.0,1364.0,305.0,0.0,1364.0,314.0,0.0,1364.0,419.0,0.0,1364.0,459.0,0.0,1364.0,438.0,0.0,1364.0,661.0,0.0,1364.0,671.0,0.0,1364.0,688.0,0.0,1364.0,654.0,0.0,1364.0,679.0,0.0,1364.0,671.0,0.0,1364.0,667.0,0.0,1364.0,610.0,0.0,1364.0,421.0,0.0,1368.0,440.0,0.0,1368.0,440.0,0.0,1368.0,436.0,0.0,1368.0,393.0,0.0,1368.0,433.0,0.0,1368.0,443.0,0.0,1368.0,424.0,0.0,1368.0,684.0,0.0,1364.0,716.0,0.0,1364.0,604.0,0.0,1364.0,646.0,0.0,1364.0,761.0,0.0,1364.0,802.0,0.0,1364.0,782.0,0.0,1364.0,741.0,0.0,1364.0,443.0,0.0,1368.0,359.0,0.0,1368.0,561.0,0.0,1368.0,418.0,0.0,1368.0,483.0,0.0,1368.0,482.0,0.0,1368.0,562.0,0.0,1368.0,493.0,0.0,1368.0,386.0,0.0,1368.0,358.0,0.0,1368.0,513.0,0.0,1368.0,464.0,0.0,1368.0,459.0,0.0,1368.0,420.0,0.0,1368.0,546.0,0.0,1368.0,454.0,0.0,1368.0,336.0,0.0,1360.0,350.0,0.0,1360.0,346.0,0.0,1360.0,346.0,0.0,1360.0,404.0,0.0,1360.0,413.0,0.0,1360.0,460.0,0.0,1360.0,448.0,0.0,1360.0,478.0,0.0,1368.0,507.0,0.0,1368.0,397.0,0.0,1368.0,397.0,0.0,1368.0,398.0,0.0,1368.0,484.0,0.0,1368.0,479.0,0.0,1368.0,380.0,0.0,1368.0,443.0,0.0,1360.0,349.0,0.0,1360.0,441.0,0.0,1360.0,308.0,0.0,1360.0,322.0,0.0,1360.0,309.0,0.0,1360.0,371.0,0.0,1360.0,310.0,0.0,1360.0,64,0,0.0,49152.0,32768.0,65536.0,32768.0,0.0,0.0,0.0,8799.0,0.0,7807.0,611975.0,0.0,0.0,0.0,0.0,65702.0,65536.0,131072.0,0.0,0.0,524288.0,228.0,0.0,64,0,0.0,0.0,1048576.0,0.0,0.0,0.0,0.0,0.0,0Linha truncada
@@ -0,0 +1,2 @@
+workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd
+device_inv_int,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Wed 29 May 2024 01:38:17 PM  (CDT),2,sh5-1w300-rg3-3,AMD Instinct MI300A Accelerator,"American Megatrends International, LLC.RMO1002DS",Ubuntu 22.04.2 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,131174852,,6.1.2-110,N/A,SPX,NPS1,MI300A_A1,gfx942,32,24576,228,4,24,64,1024,32,2100,1300,2100,1300,96,32,120,4,5324.8,6
@@ -0,0 +1,4 @@
+Dispatch_ID,GPU_ID,Queue_ID,PID,TID,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,Wave_Size,Kernel_Name,Start_Timestamp,End_Timestamp,Correlation_ID
+1,11995,1,147884,147884,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",73775713810508,73775713819482,0
+2,11995,1,147884,147884,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",73775713837269,73775713843599,0
+3,11995,1,147884,147884,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",73775713858742,73775713864711,0
@@ -0,0 +1,4 @@
+Dispatch_ID,GPU_ID,Queue_ID,PID,TID,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,Wave_Size,Kernel_Name,Start_Timestamp,End_Timestamp,Correlation_ID,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES
+0,60633,1,966139,966139,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",716335581813913,716335581830632,0,433757.0,433757.0,16384.0,65536.0,34988.0,2816156.0
+1,60633,1,966139,966139,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",716335581852432,716335581866430,0,504905.0,504905.0,16384.0,65536.0,13133.0,1048584.0
+2,60633,1,966139,966139,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",716335581886549,716335581900789,0,376743.0,376743.0,16384.0,65536.0,13119.0,1048576.0