Add CI workloads for MI300A_A1 and MI300X_A1

Signed-off-by: coleramos425 <colramos@amd.com>
2024-05-31 16:09:58 -05:00
1 parent 7d79fcc276
commit b8af814467
@@ -0,0 +1,4 @@
+Dispatch_ID,GPU_ID,Queue_ID,PID,TID,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,Wave_Size,Kernel_Name,Start_Timestamp,End_Timestamp,Correlation_ID,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES
+0,11995,1,142118,142118,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",73285541833672,73285541841404,0,202827.0,202827.0,16384.0,65536.0,28620.0,2297628.0
+1,11995,1,142118,142118,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",73285541860632,73285541867162,0,202737.0,202737.0,16384.0,65536.0,13055.0,1048628.0
+2,11995,1,142118,142118,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",73285541884388,73285541890838,0,162339.0,162339.0,16384.0,65536.0,13065.0,1049388.0
@@ -0,0 +1,4 @@
+Dispatch_ID,GPU_ID,Queue_ID,PID,TID,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,Wave_Size,Kernel_Name,Start_Timestamp,End_Timestamp,Correlation_ID,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES
+0,11995,1,142130,142130,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",73285541833672,73285541841404,0,0.0,0.0,0.0
+1,11995,1,142130,142130,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",73285541860632,73285541867162,0,0.0,0.0,0.0
+2,11995,1,142130,142130,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",73285541884388,73285541890838,0,0.0,0.0,0.0
@@ -0,0 +1,4 @@
+Dispatch_ID,GPU_ID,Queue_ID,PID,TID,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,Wave_Size,Kernel_Name,Start_Timestamp,End_Timestamp,Correlation_ID,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES
+0,11995,1,142142,142142,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",73285541833672,73285541841404,0,65536.0,341158.0,27350288.0
+1,11995,1,142142,142142,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",73285541860632,73285541867162,0,65536.0,288638.0,23108600.0
+2,11995,1,142142,142142,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",73285541884388,73285541890838,0,65536.0,195816.0,15617512.0
@@ -0,0 +1,4 @@
+Dispatch_ID,GPU_ID,Queue_ID,PID,TID,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,Wave_Size,Kernel_Name,Start_Timestamp,End_Timestamp,Correlation_ID,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES
+0,11995,1,142154,142154,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",73285541833672,73285541841404,0,32768.0,538203.0,43053984.0
+1,11995,1,142154,142154,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",73285541860632,73285541867162,0,32768.0,425515.0,34036704.0
+2,11995,1,142154,142154,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",73285541884388,73285541890838,0,32768.0,430832.0,34453616.0
@@ -0,0 +1,4 @@
+Dispatch_ID,GPU_ID,Queue_ID,PID,TID,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,Wave_Size,Kernel_Name,Start_Timestamp,End_Timestamp,Correlation_ID,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES
+0,11995,1,142166,142166,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",73285541833672,73285541841404,0,212714.0,212714.0,117273.0,850856.0,16384.0,13896876.0,258927.0,0.0,56015688.0
+1,11995,1,142166,142166,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",73285541860632,73285541867162,0,200364.0,200364.0,117231.0,801456.0,16384.0,10727754.0,200440.0,0.0,43332436.0
+2,11995,1,142166,142166,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",73285541884388,73285541890838,0,175947.0,175947.0,94374.0,703788.0,16384.0,10086001.0,192594.0,0.0,40773648.0
@@ -0,0 +1,233 @@
+Omniperf version: 2.0.0
+Profiler choice: rocprofv2
+Path: /home/colramos/omniperf/tests/workloads/dispatch_inv/MI300A_A1
+Target: MI300A_A1
+Command: ./tests/vcopy -n 1048576 -b 256 -i 3
+Kernel Selection: None
+Dispatch Selection: ['invalid']
+Hardware Blocks: All
+
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Collecting Performance Counters
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+
+[profiling] Current input file: tests/workloads/dispatch_inv/MI300A_A1/perfmon/SQ_IFETCH_LEVEL.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - GRBM_COUNT
+   |-> [/opt/rocm/bin/rocprofv2] - GRBM_GUI_ACTIVE
+
+[profiling] Current input file: tests/workloads/dispatch_inv/MI300A_A1/perfmon/SQ_INST_LEVEL_LDS.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_LDS
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INST_LEVEL_LDS
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_ACCUM_PREV_HIRES
+   |-> [/opt/rocm/bin/rocprofv2] Enabling Counter Collection
+   |-> [/opt/rocm/bin/rocprofv2] vcopy testing on GCD 0
+   |-> [/opt/rocm/bin/rocprofv2] Finished allocating vectors on the CPU
+   |-> [/opt/rocm/bin/rocprofv2] Finished allocating vectors on the GPU
+   |-> [/opt/rocm/bin/rocprofv2] Finished copying vectors to the GPU
+   |-> [/opt/rocm/bin/rocprofv2] sw thinks it moved 1.000000 KB per wave
+   |-> [/opt/rocm/bin/rocprofv2] Total threads: 1048576, Grid Size: 4096 block Size:256, Wavefronts:16384:
+   |-> [/opt/rocm/bin/rocprofv2] Launching the  kernel on the GPU
+   |-> [/opt/rocm/bin/rocprofv2] Finished executing kernel
+
+[profiling] Current input file: tests/workloads/dispatch_inv/MI300A_A1/perfmon/SQ_INST_LEVEL_SMEM.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_SMEM
+
+[profiling] Current input file: tests/workloads/dispatch_inv/MI300A_A1/perfmon/SQ_INST_LEVEL_VMEM.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VMEM
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INST_LEVEL_VMEM
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_ACCUM_PREV_HIRES
+   |-> [/opt/rocm/bin/rocprofv2] Enabling Counter Collection
+   |-> [/opt/rocm/bin/rocprofv2] vcopy testing on GCD 0
+   |-> [/opt/rocm/bin/rocprofv2] Finished allocating vectors on the CPU
+   |-> [/opt/rocm/bin/rocprofv2] Finished allocating vectors on the GPU
+   |-> [/opt/rocm/bin/rocprofv2] Finished copying vectors to the GPU
+
+[profiling] Current input file: tests/workloads/dispatch_inv/MI300A_A1/perfmon/SQ_LEVEL_WAVES.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - GRBM_COUNT
+   |-> [/opt/rocm/bin/rocprofv2] - GRBM_GUI_ACTIVE
+   |-> [/opt/rocm/bin/rocprofv2] - CPC_ME1_BUSY_FOR_PACKET_DECODE
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_CYCLES
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_WAVES
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_WAVE_CYCLES
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_BUSY_CYCLES
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_LEVEL_WAVES
+
+[profiling] Current input file: tests/workloads/dispatch_inv/MI300A_A1/perfmon/pmc_perf_0.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_CYCLES
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_BUSY_CYCLES
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_BUSY_CU_CYCLES
+
+[profiling] Current input file: tests/workloads/dispatch_inv/MI300A_A1/perfmon/pmc_perf_1.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VMEM
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_SALU
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VSKIPPED
+
+[profiling] Current input file: tests/workloads/dispatch_inv/MI300A_A1/perfmon/pmc_perf_10.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQC_TC_DATA_ATOMIC_REQ
+   |-> [/opt/rocm/bin/rocprofv2] - SQC_TC_STALL
+   |-> [/opt/rocm/bin/rocprofv2] - SQC_TC_REQ
+
+[profiling] Current input file: tests/workloads/dispatch_inv/MI300A_A1/perfmon/pmc_perf_11.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQC_DCACHE_INPUT_VALID_READYB
+   |-> [/opt/rocm/bin/rocprofv2] - SQC_DCACHE_ATOMIC
+   |-> [/opt/rocm/bin/rocprofv2] - SQC_DCACHE_REQ_READ_8
+   |-> [/opt/rocm/bin/rocprofv2] - SQC_DCACHE_REQ
+
+[profiling] Current input file: tests/workloads/dispatch_inv/MI300A_A1/perfmon/pmc_perf_12.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQC_DCACHE_REQ_READ_2
+   |-> [/opt/rocm/bin/rocprofv2] - SQC_DCACHE_REQ_READ_4
+   |-> [/opt/rocm/bin/rocprofv2] Enabling Counter Collection
+   |-> [/opt/rocm/bin/rocprofv2] vcopy testing on GCD 0
+   |-> [/opt/rocm/bin/rocprofv2] Finished allocating vectors on the CPU
+   |-> [/opt/rocm/bin/rocprofv2] Finished allocating vectors on the GPU
+   |-> [/opt/rocm/bin/rocprofv2] Finished copying vectors to the GPU
+   |-> [/opt/rocm/bin/rocprofv2] sw thinks it moved 1.000000 KB per wave
+
+[profiling] Current input file: tests/workloads/dispatch_inv/MI300A_A1/perfmon/pmc_perf_13.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_ATOMIC[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_BUBBLE[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_CYCLE[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_EA0_ATOMIC[0]
+
+[profiling] Current input file: tests/workloads/dispatch_inv/MI300A_A1/perfmon/pmc_perf_14.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_EA0_ATOMIC_LEVEL[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_EA0_RDREQ[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_EA0_RDREQ_32B[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_EA0_RDREQ_LEVEL[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_EA0_ATOMIC_LEVEL[1]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_EA0_RDREQ[1]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_EA0_RDREQ_32B[1]
+
+[profiling] Current input file: tests/workloads/dispatch_inv/MI300A_A1/perfmon/pmc_perf_15.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_EA0_WRREQ[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_EA0_WRREQ_64B[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_EA0_WRREQ_LEVEL[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_HIT[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_EA0_WRREQ[1]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_EA0_WRREQ_64B[1]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_EA0_WRREQ_LEVEL[1]
+
+[profiling] Current input file: tests/workloads/dispatch_inv/MI300A_A1/perfmon/pmc_perf_16.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_MISS[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_READ[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_REQ[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_RW_REQ[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_MISS[1]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_READ[1]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_REQ[1]
+
+[profiling] Current input file: tests/workloads/dispatch_inv/MI300A_A1/perfmon/pmc_perf_17.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_TAG_STALL[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_TOO_MANY_EA_WRREQS_STALL[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_WRITE[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_TAG_STALL[1]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_TOO_MANY_EA_WRREQS_STALL[1]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_WRITE[1]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_TAG_STALL[2]
+
+[profiling] Current input file: tests/workloads/dispatch_inv/MI300A_A1/perfmon/pmc_perf_2.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_TRANS_F16
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_ADD_F32
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_MUL_F32
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_FMA_F32
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_TRANS_F32
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_ADD_F64
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_MUL_F64
+
+[profiling] Current input file: tests/workloads/dispatch_inv/MI300A_A1/perfmon/pmc_perf_3.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_TRANS_F64
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_INT32
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_INT64
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_SMEM
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_FLAT
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_LDS
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_GDS
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_EXP_GDS
+
+[profiling] Current input file: tests/workloads/dispatch_inv/MI300A_A1/perfmon/pmc_perf_4.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_BRANCH
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_SENDMSG
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_WAIT_ANY
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_WAIT_INST_ANY
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_ACTIVE_INST_ANY
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_ACTIVE_INST_VMEM
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_ACTIVE_INST_LDS
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_ACTIVE_INST_VALU
+
+[profiling] Current input file: tests/workloads/dispatch_inv/MI300A_A1/perfmon/pmc_perf_5.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_ACTIVE_INST_SCA
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_ACTIVE_INST_EXP_GDS
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_ACTIVE_INST_MISC
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_ACTIVE_INST_FLAT
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INST_CYCLES_VMEM_WR
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INST_CYCLES_VMEM_RD
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INST_CYCLES_SMEM
+
+[profiling] Current input file: tests/workloads/dispatch_inv/MI300A_A1/perfmon/pmc_perf_6.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_THREAD_CYCLES_VALU
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_IFETCH
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_LDS_BANK_CONFLICT
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_LDS_ADDR_CONFLICT
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_LDS_UNALIGNED_STALL
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_WAVES_EQ_64
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_WAVES_LT_64
+
+[profiling] Current input file: tests/workloads/dispatch_inv/MI300A_A1/perfmon/pmc_perf_7.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_WAVES_LT_32
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_WAVES_LT_16
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_ITEMS
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_LDS_MEM_VIOLATIONS
+
+[profiling] Current input file: tests/workloads/dispatch_inv/MI300A_A1/perfmon/pmc_perf_8.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_SMEM_NORM
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_MFMA
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_MFMA_I8
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_MFMA_F16
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_MFMA_BF16
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_MFMA_F32
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_MFMA_F64
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_VALU_MFMA_BUSY_CYCLES
+
+[profiling] Current input file: tests/workloads/dispatch_inv/MI300A_A1/perfmon/pmc_perf_9.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_MFMA_MOPS_I8
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_MFMA_MOPS_F16
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_MFMA_MOPS_BF16
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_MFMA_MOPS_F32
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_MFMA_MOPS_F64
+   |-> [/opt/rocm/bin/rocprofv2] - SQC_TC_INST_REQ
+   |-> [/opt/rocm/bin/rocprofv2] - SQC_TC_DATA_READ_REQ
+
+[profiling] Current input file: tests/workloads/dispatch_inv/MI300A_A1/perfmon/timestamps.txt
+   |-> [/opt/rocm/bin/rocprofv2] vcopy testing on GCD 0
+   |-> [/opt/rocm/bin/rocprofv2] Finished allocating vectors on the CPU
+   |-> [/opt/rocm/bin/rocprofv2] Finished allocating vectors on the GPU
+   |-> [/opt/rocm/bin/rocprofv2] Finished copying vectors to the GPU
+   |-> [/opt/rocm/bin/rocprofv2] sw thinks it moved 1.000000 KB per wave
+   |-> [/opt/rocm/bin/rocprofv2] Total threads: 1048576, Grid Size: 4096 block Size:256, Wavefronts:16384:
+   |-> [/opt/rocm/bin/rocprofv2] Launching the  kernel on the GPU
+   |-> [/opt/rocm/bin/rocprofv2] Finished executing kernel
+[roofline] Roofline temporarily disabled in MI300
@@ -0,0 +1,5 @@
+pmc: GRBM_COUNT GRBM_GUI_ACTIVE SQ_WAVES SQ_IFETCH SQ_IFETCH_LEVEL  SQ_ACCUM_PREV_HIRES
+
+gpu:
+range: invalid
+kernel:
@@ -0,0 +1,5 @@
+pmc: SQ_INSTS_LDS SQ_INST_LEVEL_LDS  SQ_ACCUM_PREV_HIRES
+
+gpu:
+range: invalid
+kernel:
@@ -0,0 +1,5 @@
+pmc: SQ_INSTS_SMEM  SQ_INST_LEVEL_SMEM SQ_ACCUM_PREV_HIRES
+
+gpu:
+range: invalid
+kernel:
@@ -0,0 +1,5 @@
+pmc: SQ_INSTS_VMEM  SQ_INST_LEVEL_VMEM SQ_ACCUM_PREV_HIRES
+
+gpu:
+range: invalid
+kernel:
@@ -0,0 +1,5 @@
+pmc: GRBM_COUNT GRBM_GUI_ACTIVE CPC_ME1_BUSY_FOR_PACKET_DECODE SQ_CYCLES SQ_WAVES SQ_WAVE_CYCLES SQ_BUSY_CYCLES SQ_LEVEL_WAVES  SQ_ACCUM_PREV_HIRES
+
+gpu:
+range: invalid
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQ_CYCLES SQ_BUSY_CYCLES SQ_BUSY_CU_CYCLES SQ_WAVES SQ_WAVE_CYCLES SQ_INSTS_VALU_CVT SQ_INSTS_VMEM_WR SQ_INSTS_VMEM_RD GRBM_COUNT GRBM_GUI_ACTIVE TCP_GATE_EN1_sum TCP_GATE_EN2_sum TCP_TD_TCP_STALL_CYCLES_sum TCP_TCR_TCP_STALL_CYCLES_sum TA_TA_BUSY_sum TA_BUFFER_WAVEFRONTS_sum TD_TD_BUSY_sum TD_TC_STALL_sum SPI_CSN_WINDOW_VALID SPI_CSN_BUSY CPC_CPC_STAT_BUSY CPC_CPC_STAT_IDLE CPF_CPF_STAT_BUSY CPF_CPF_STAT_STALL TCC_CYCLE_sum TCC_BUSY_sum TCC_PROBE_sum TCC_PROBE_ALL_sum
+
+gpu:
+range: invalid
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQ_INSTS_VMEM SQ_INSTS_SALU SQ_INSTS_VSKIPPED SQ_INSTS SQ_INSTS_VALU SQ_INSTS_VALU_ADD_F16 SQ_INSTS_VALU_MUL_F16 SQ_INSTS_VALU_FMA_F16 GRBM_SPI_BUSY TCP_READ_TAGCONFLICT_STALL_CYCLES_sum TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum TCP_TA_TCP_STATE_READ_sum TA_BUFFER_READ_WAVEFRONTS_sum TA_BUFFER_WRITE_WAVEFRONTS_sum TD_SPI_STALL_sum TD_LOAD_WAVEFRONT_sum SPI_CSN_NUM_THREADGROUPS SPI_CSN_WAVE CPC_CPC_TCIU_BUSY CPC_CPC_TCIU_IDLE CPF_CPF_TCIU_BUSY CPF_CPF_TCIU_STALL TCC_NC_REQ_sum TCC_UC_REQ_sum TCC_CC_REQ_sum TCC_RW_REQ_sum
+
+gpu:
+range: invalid
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQC_TC_DATA_ATOMIC_REQ SQC_TC_STALL SQC_TC_REQ SQC_DCACHE_REQ_READ_16 SQC_ICACHE_REQ SQC_ICACHE_HITS SQC_ICACHE_MISSES SQC_ICACHE_MISSES_DUPLICATE
+
+gpu:
+range: invalid
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQC_DCACHE_INPUT_VALID_READYB SQC_DCACHE_ATOMIC SQC_DCACHE_REQ_READ_8 SQC_DCACHE_REQ SQC_DCACHE_HITS SQC_DCACHE_MISSES SQC_DCACHE_MISSES_DUPLICATE SQC_DCACHE_REQ_READ_1
+
+gpu:
+range: invalid
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQC_DCACHE_REQ_READ_2 SQC_DCACHE_REQ_READ_4
+
+gpu:
+range: invalid
+kernel:
@@ -0,0 +1,5 @@
+pmc:  TCC_ATOMIC[0] TCC_BUBBLE[0] TCC_CYCLE[0] TCC_EA0_ATOMIC[0] TCC_ATOMIC[1] TCC_BUBBLE[1] TCC_CYCLE[1] TCC_EA0_ATOMIC[1] TCC_ATOMIC[2] TCC_BUBBLE[2] TCC_CYCLE[2] TCC_EA0_ATOMIC[2] TCC_ATOMIC[3] TCC_BUBBLE[3] TCC_CYCLE[3] TCC_EA0_ATOMIC[3] TCC_ATOMIC[4] TCC_BUBBLE[4] TCC_CYCLE[4] TCC_EA0_ATOMIC[4] TCC_ATOMIC[5] TCC_BUBBLE[5] TCC_CYCLE[5] TCC_EA0_ATOMIC[5] TCC_ATOMIC[6] TCC_BUBBLE[6] TCC_CYCLE[6] TCC_EA0_ATOMIC[6] TCC_ATOMIC[7] TCC_BUBBLE[7] TCC_CYCLE[7] TCC_EA0_ATOMIC[7] TCC_ATOMIC[8] TCC_BUBBLE[8] TCC_CYCLE[8] TCC_EA0_ATOMIC[8] TCC_ATOMIC[9] TCC_BUBBLE[9] TCC_CYCLE[9] TCC_EA0_ATOMIC[9] TCC_ATOMIC[10] TCC_BUBBLE[10] TCC_CYCLE[10] TCC_EA0_ATOMIC[10] TCC_ATOMIC[11] TCC_BUBBLE[11] TCC_CYCLE[11] TCC_EA0_ATOMIC[11] TCC_ATOMIC[12] TCC_BUBBLE[12] TCC_CYCLE[12] TCC_EA0_ATOMIC[12] TCC_ATOMIC[13] TCC_BUBBLE[13] TCC_CYCLE[13] TCC_EA0_ATOMIC[13] TCC_ATOMIC[14] TCC_BUBBLE[14] TCC_CYCLE[14] TCC_EA0_ATOMIC[14] TCC_ATOMIC[15] TCC_BUBBLE[15] TCC_CYCLE[15] TCC_EA0_ATOMIC[15]
+
+gpu:
+range: invalid
+kernel:
@@ -0,0 +1,5 @@
+pmc:  TCC_EA0_ATOMIC_LEVEL[0] TCC_EA0_RDREQ[0] TCC_EA0_RDREQ_32B[0] TCC_EA0_RDREQ_LEVEL[0] TCC_EA0_ATOMIC_LEVEL[1] TCC_EA0_RDREQ[1] TCC_EA0_RDREQ_32B[1] TCC_EA0_RDREQ_LEVEL[1] TCC_EA0_ATOMIC_LEVEL[2] TCC_EA0_RDREQ[2] TCC_EA0_RDREQ_32B[2] TCC_EA0_RDREQ_LEVEL[2] TCC_EA0_ATOMIC_LEVEL[3] TCC_EA0_RDREQ[3] TCC_EA0_RDREQ_32B[3] TCC_EA0_RDREQ_LEVEL[3] TCC_EA0_ATOMIC_LEVEL[4] TCC_EA0_RDREQ[4] TCC_EA0_RDREQ_32B[4] TCC_EA0_RDREQ_LEVEL[4] TCC_EA0_ATOMIC_LEVEL[5] TCC_EA0_RDREQ[5] TCC_EA0_RDREQ_32B[5] TCC_EA0_RDREQ_LEVEL[5] TCC_EA0_ATOMIC_LEVEL[6] TCC_EA0_RDREQ[6] TCC_EA0_RDREQ_32B[6] TCC_EA0_RDREQ_LEVEL[6] TCC_EA0_ATOMIC_LEVEL[7] TCC_EA0_RDREQ[7] TCC_EA0_RDREQ_32B[7] TCC_EA0_RDREQ_LEVEL[7] TCC_EA0_ATOMIC_LEVEL[8] TCC_EA0_RDREQ[8] TCC_EA0_RDREQ_32B[8] TCC_EA0_RDREQ_LEVEL[8] TCC_EA0_ATOMIC_LEVEL[9] TCC_EA0_RDREQ[9] TCC_EA0_RDREQ_32B[9] TCC_EA0_RDREQ_LEVEL[9] TCC_EA0_ATOMIC_LEVEL[10] TCC_EA0_RDREQ[10] TCC_EA0_RDREQ_32B[10] TCC_EA0_RDREQ_LEVEL[10] TCC_EA0_ATOMIC_LEVEL[11] TCC_EA0_RDREQ[11] TCC_EA0_RDREQ_32B[11] TCC_EA0_RDREQ_LEVEL[11] TCC_EA0_ATOMIC_LEVEL[12] TCC_EA0_RDREQ[12] TCC_EA0_RDREQ_32B[12] TCC_EA0_RDREQ_LEVEL[12] TCC_EA0_ATOMIC_LEVEL[13] TCC_EA0_RDREQ[13] TCC_EA0_RDREQ_32B[13] TCC_EA0_RDREQ_LEVEL[13] TCC_EA0_ATOMIC_LEVEL[14] TCC_EA0_RDREQ[14] TCC_EA0_RDREQ_32B[14] TCC_EA0_RDREQ_LEVEL[14] TCC_EA0_ATOMIC_LEVEL[15] TCC_EA0_RDREQ[15] TCC_EA0_RDREQ_32B[15] TCC_EA0_RDREQ_LEVEL[15]
+
+gpu:
+range: invalid
+kernel:
@@ -0,0 +1,5 @@
+pmc:  TCC_EA0_WRREQ[0] TCC_EA0_WRREQ_64B[0] TCC_EA0_WRREQ_LEVEL[0] TCC_HIT[0] TCC_EA0_WRREQ[1] TCC_EA0_WRREQ_64B[1] TCC_EA0_WRREQ_LEVEL[1] TCC_HIT[1] TCC_EA0_WRREQ[2] TCC_EA0_WRREQ_64B[2] TCC_EA0_WRREQ_LEVEL[2] TCC_HIT[2] TCC_EA0_WRREQ[3] TCC_EA0_WRREQ_64B[3] TCC_EA0_WRREQ_LEVEL[3] TCC_HIT[3] TCC_EA0_WRREQ[4] TCC_EA0_WRREQ_64B[4] TCC_EA0_WRREQ_LEVEL[4] TCC_HIT[4] TCC_EA0_WRREQ[5] TCC_EA0_WRREQ_64B[5] TCC_EA0_WRREQ_LEVEL[5] TCC_HIT[5] TCC_EA0_WRREQ[6] TCC_EA0_WRREQ_64B[6] TCC_EA0_WRREQ_LEVEL[6] TCC_HIT[6] TCC_EA0_WRREQ[7] TCC_EA0_WRREQ_64B[7] TCC_EA0_WRREQ_LEVEL[7] TCC_HIT[7] TCC_EA0_WRREQ[8] TCC_EA0_WRREQ_64B[8] TCC_EA0_WRREQ_LEVEL[8] TCC_HIT[8] TCC_EA0_WRREQ[9] TCC_EA0_WRREQ_64B[9] TCC_EA0_WRREQ_LEVEL[9] TCC_HIT[9] TCC_EA0_WRREQ[10] TCC_EA0_WRREQ_64B[10] TCC_EA0_WRREQ_LEVEL[10] TCC_HIT[10] TCC_EA0_WRREQ[11] TCC_EA0_WRREQ_64B[11] TCC_EA0_WRREQ_LEVEL[11] TCC_HIT[11] TCC_EA0_WRREQ[12] TCC_EA0_WRREQ_64B[12] TCC_EA0_WRREQ_LEVEL[12] TCC_HIT[12] TCC_EA0_WRREQ[13] TCC_EA0_WRREQ_64B[13] TCC_EA0_WRREQ_LEVEL[13] TCC_HIT[13] TCC_EA0_WRREQ[14] TCC_EA0_WRREQ_64B[14] TCC_EA0_WRREQ_LEVEL[14] TCC_HIT[14] TCC_EA0_WRREQ[15] TCC_EA0_WRREQ_64B[15] TCC_EA0_WRREQ_LEVEL[15] TCC_HIT[15]
+
+gpu:
+range: invalid
+kernel:
@@ -0,0 +1,5 @@
+pmc:  TCC_MISS[0] TCC_READ[0] TCC_REQ[0] TCC_RW_REQ[0] TCC_MISS[1] TCC_READ[1] TCC_REQ[1] TCC_RW_REQ[1] TCC_MISS[2] TCC_READ[2] TCC_REQ[2] TCC_RW_REQ[2] TCC_MISS[3] TCC_READ[3] TCC_REQ[3] TCC_RW_REQ[3] TCC_MISS[4] TCC_READ[4] TCC_REQ[4] TCC_RW_REQ[4] TCC_MISS[5] TCC_READ[5] TCC_REQ[5] TCC_RW_REQ[5] TCC_MISS[6] TCC_READ[6] TCC_REQ[6] TCC_RW_REQ[6] TCC_MISS[7] TCC_READ[7] TCC_REQ[7] TCC_RW_REQ[7] TCC_MISS[8] TCC_READ[8] TCC_REQ[8] TCC_RW_REQ[8] TCC_MISS[9] TCC_READ[9] TCC_REQ[9] TCC_RW_REQ[9] TCC_MISS[10] TCC_READ[10] TCC_REQ[10] TCC_RW_REQ[10] TCC_MISS[11] TCC_READ[11] TCC_REQ[11] TCC_RW_REQ[11] TCC_MISS[12] TCC_READ[12] TCC_REQ[12] TCC_RW_REQ[12] TCC_MISS[13] TCC_READ[13] TCC_REQ[13] TCC_RW_REQ[13] TCC_MISS[14] TCC_READ[14] TCC_REQ[14] TCC_RW_REQ[14] TCC_MISS[15] TCC_READ[15] TCC_REQ[15] TCC_RW_REQ[15]
+
+gpu:
+range: invalid
+kernel:
@@ -0,0 +1,5 @@
+pmc:  TCC_TAG_STALL[0] TCC_TOO_MANY_EA_WRREQS_STALL[0] TCC_WRITE[0] TCC_TAG_STALL[1] TCC_TOO_MANY_EA_WRREQS_STALL[1] TCC_WRITE[1] TCC_TAG_STALL[2] TCC_TOO_MANY_EA_WRREQS_STALL[2] TCC_WRITE[2] TCC_TAG_STALL[3] TCC_TOO_MANY_EA_WRREQS_STALL[3] TCC_WRITE[3] TCC_TAG_STALL[4] TCC_TOO_MANY_EA_WRREQS_STALL[4] TCC_WRITE[4] TCC_TAG_STALL[5] TCC_TOO_MANY_EA_WRREQS_STALL[5] TCC_WRITE[5] TCC_TAG_STALL[6] TCC_TOO_MANY_EA_WRREQS_STALL[6] TCC_WRITE[6] TCC_TAG_STALL[7] TCC_TOO_MANY_EA_WRREQS_STALL[7] TCC_WRITE[7] TCC_TAG_STALL[8] TCC_TOO_MANY_EA_WRREQS_STALL[8] TCC_WRITE[8] TCC_TAG_STALL[9] TCC_TOO_MANY_EA_WRREQS_STALL[9] TCC_WRITE[9] TCC_TAG_STALL[10] TCC_TOO_MANY_EA_WRREQS_STALL[10] TCC_WRITE[10] TCC_TAG_STALL[11] TCC_TOO_MANY_EA_WRREQS_STALL[11] TCC_WRITE[11] TCC_TAG_STALL[12] TCC_TOO_MANY_EA_WRREQS_STALL[12] TCC_WRITE[12] TCC_TAG_STALL[13] TCC_TOO_MANY_EA_WRREQS_STALL[13] TCC_WRITE[13] TCC_TAG_STALL[14] TCC_TOO_MANY_EA_WRREQS_STALL[14] TCC_WRITE[14] TCC_TAG_STALL[15] TCC_TOO_MANY_EA_WRREQS_STALL[15] TCC_WRITE[15]
+
+gpu:
+range: invalid
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQ_INSTS_VALU_TRANS_F16 SQ_INSTS_VALU_ADD_F32 SQ_INSTS_VALU_MUL_F32 SQ_INSTS_VALU_FMA_F32 SQ_INSTS_VALU_TRANS_F32 SQ_INSTS_VALU_ADD_F64 SQ_INSTS_VALU_MUL_F64 SQ_INSTS_VALU_FMA_F64 TCP_VOLATILE_sum TCP_TOTAL_ACCESSES_sum TCP_TOTAL_READ_sum TCP_TOTAL_WRITE_sum TA_BUFFER_ATOMIC_WAVEFRONTS_sum TA_BUFFER_TOTAL_CYCLES_sum TD_ATOMIC_WAVEFRONT_sum TD_STORE_WAVEFRONT_sum SPI_RA_REQ_NO_ALLOC SPI_RA_REQ_NO_ALLOC_CSN CPC_CPC_STAT_STALL CPC_UTCL1_STALL_ON_TRANSLATION CPF_CPF_STAT_IDLE CPF_CPF_TCIU_IDLE TCC_REQ_sum TCC_STREAMING_REQ_sum TCC_HIT_sum TCC_MISS_sum
+
+gpu:
+range: invalid
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQ_INSTS_VALU_TRANS_F64 SQ_INSTS_VALU_INT32 SQ_INSTS_VALU_INT64 SQ_INSTS_SMEM SQ_INSTS_FLAT SQ_INSTS_LDS SQ_INSTS_GDS SQ_INSTS_EXP_GDS TCP_TOTAL_ATOMIC_WITH_RET_sum TCP_TOTAL_ATOMIC_WITHOUT_RET_sum TCP_TOTAL_WRITEBACK_INVALIDATES_sum TCP_TOTAL_CACHE_ACCESSES_sum TA_BUFFER_COALESCED_READ_CYCLES_sum TA_BUFFER_COALESCED_WRITE_CYCLES_sum TD_COALESCABLE_WAVEFRONT_sum SPI_RA_RES_STALL_CSN SPI_RA_TMP_STALL_CSN CPC_CPC_UTCL2IU_BUSY CPC_CPC_UTCL2IU_IDLE CPF_CMP_UTCL1_STALL_ON_TRANSLATION TCC_READ_sum TCC_WRITE_sum TCC_ATOMIC_sum TCC_WRITEBACK_sum
+
+gpu:
+range: invalid
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQ_INSTS_BRANCH SQ_INSTS_SENDMSG SQ_WAIT_ANY SQ_WAIT_INST_ANY SQ_ACTIVE_INST_ANY SQ_ACTIVE_INST_VMEM SQ_ACTIVE_INST_LDS SQ_ACTIVE_INST_VALU TCP_UTCL1_TRANSLATION_MISS_sum TCP_UTCL1_TRANSLATION_HIT_sum TCP_UTCL1_PERMISSION_MISS_sum TCP_UTCL1_REQUEST_sum TA_ADDR_STALLED_BY_TC_CYCLES_sum TA_TOTAL_WAVEFRONTS_sum SPI_RA_WAVE_SIMD_FULL_CSN SPI_RA_VGPR_SIMD_FULL_CSN CPC_CPC_UTCL2IU_STALL CPC_ME1_BUSY_FOR_PACKET_DECODE TCC_EA0_WRREQ_sum TCC_EA0_WRREQ_64B_sum TCC_EA0_WR_UNCACHED_32B_sum TCC_EA0_WRREQ_DRAM_sum
+
+gpu:
+range: invalid
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQ_ACTIVE_INST_SCA SQ_ACTIVE_INST_EXP_GDS SQ_ACTIVE_INST_MISC SQ_ACTIVE_INST_FLAT SQ_INST_CYCLES_VMEM_WR SQ_INST_CYCLES_VMEM_RD SQ_INST_CYCLES_SMEM SQ_INST_CYCLES_SALU TCP_TCC_READ_REQ_sum TCP_TCC_WRITE_REQ_sum TCP_TCC_ATOMIC_WITH_RET_REQ_sum TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum TA_ADDR_STALLED_BY_TD_CYCLES_sum TA_DATA_STALLED_BY_TC_CYCLES_sum SPI_RA_SGPR_SIMD_FULL_CSN SPI_RA_LDS_CU_FULL_CSN CPC_ME1_DC0_SPI_BUSY TCC_EA0_RDREQ_sum TCC_EA0_RDREQ_32B_sum TCC_BUBBLE_sum TCC_EA0_RD_UNCACHED_32B_sum
+
+gpu:
+range: invalid
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQ_THREAD_CYCLES_VALU SQ_IFETCH SQ_LDS_BANK_CONFLICT SQ_LDS_ADDR_CONFLICT SQ_LDS_UNALIGNED_STALL SQ_WAVES_EQ_64 SQ_WAVES_LT_64 SQ_WAVES_LT_48 TCP_TCC_NC_READ_REQ_sum TCP_TCC_NC_WRITE_REQ_sum TCP_TCC_NC_ATOMIC_REQ_sum TCP_TCC_UC_READ_REQ_sum TA_FLAT_WAVEFRONTS_sum TA_FLAT_READ_WAVEFRONTS_sum SPI_RA_BAR_CU_FULL_CSN SPI_RA_TGLIM_CU_FULL_CSN TCC_EA0_RDREQ_DRAM_sum TCC_TAG_STALL_sum TCC_NORMAL_WRITEBACK_sum TCC_ALL_TC_OP_WB_WRITEBACK_sum
+
+gpu:
+range: invalid
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQ_WAVES_LT_32 SQ_WAVES_LT_16 SQ_ITEMS SQ_LDS_MEM_VIOLATIONS SQ_LDS_ATOMIC_RETURN SQ_LDS_IDX_ACTIVE SQ_WAVES_RESTORED SQ_WAVES_SAVED TCP_TCC_UC_WRITE_REQ_sum TCP_TCC_UC_ATOMIC_REQ_sum TCP_TCC_CC_READ_REQ_sum TCP_TCC_CC_WRITE_REQ_sum TA_FLAT_WRITE_WAVEFRONTS_sum TA_FLAT_ATOMIC_WAVEFRONTS_sum SPI_RA_WVLIM_STALL_CSN SPI_SWC_CSC_WR TCC_NORMAL_EVICT_sum TCC_ALL_TC_OP_INV_EVICT_sum TCC_TOO_MANY_EA_WRREQS_STALL_sum TCC_EA0_ATOMIC_sum
+
+gpu:
+range: invalid
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQ_INSTS_SMEM_NORM SQ_INSTS_MFMA SQ_INSTS_VALU_MFMA_I8 SQ_INSTS_VALU_MFMA_F16 SQ_INSTS_VALU_MFMA_BF16 SQ_INSTS_VALU_MFMA_F32 SQ_INSTS_VALU_MFMA_F64 SQ_VALU_MFMA_BUSY_CYCLES TCP_TCC_CC_ATOMIC_REQ_sum TCP_TCC_RW_READ_REQ_sum TCP_TCC_RW_WRITE_REQ_sum TCP_TCC_RW_ATOMIC_REQ_sum SPI_VWC_CSC_WR SPI_RA_BULKY_CU_FULL_CSN TCC_EA0_RDREQ_LEVEL_sum TCC_EA0_WRREQ_LEVEL_sum TCC_EA0_ATOMIC_LEVEL_sum TCC_EA0_WRREQ_STALL_sum
+
+gpu:
+range: invalid
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQ_INSTS_VALU_MFMA_MOPS_I8 SQ_INSTS_VALU_MFMA_MOPS_F16 SQ_INSTS_VALU_MFMA_MOPS_BF16 SQ_INSTS_VALU_MFMA_MOPS_F32 SQ_INSTS_VALU_MFMA_MOPS_F64 SQC_TC_INST_REQ SQC_TC_DATA_READ_REQ SQC_TC_DATA_WRITE_REQ TCP_PENDING_STALL_CYCLES_sum
+
+gpu:
+range: invalid
+kernel:
@@ -0,0 +1,5 @@
+pmc:
+
+gpu:
+range: invalid
+kernel:
@@ -0,0 +1,4 @@
+Dispatch_ID,GPU_ID,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,Wave_Size,Kernel_Name,Correlation_ID,SQ_INSTS_BRANCH,SQ_INSTS_SENDMSG,SQ_WAIT_ANY,SQ_WAIT_INST_ANY,SQ_ACTIVE_INST_ANY,SQ_ACTIVE_INST_VMEM,SQ_ACTIVE_INST_LDS,SQ_ACTIVE_INST_VALU,SPI_RA_WAVE_SIMD_FULL_CSN,SPI_RA_VGPR_SIMD_FULL_CSN,CPC_CPC_UTCL2IU_STALL,CPC_ME1_BUSY_FOR_PACKET_DECODE,TA_ADDR_STALLED_BY_TC_CYCLES_sum,TA_TOTAL_WAVEFRONTS_sum,TCC_EA0_WRREQ_64B_sum,TCC_EA0_WRREQ_DRAM_sum,TCC_EA0_WRREQ_sum,TCC_EA0_WR_UNCACHED_32B_sum,TCP_UTCL1_PERMISSION_MISS_sum,TCP_UTCL1_REQUEST_sum,TCP_UTCL1_TRANSLATION_HIT_sum,TCP_UTCL1_TRANSLATION_MISS_sum,Wave_Size_1,Correlation_ID_1,XCC_Index,TCC_EA0_WRREQ[0],TCC_EA0_WRREQ_64B[0],TCC_EA0_WRREQ_LEVEL[0],TCC_HIT[0],TCC_EA0_WRREQ[1],TCC_EA0_WRREQ_64B[1],TCC_EA0_WRREQ_LEVEL[1],TCC_HIT[1],TCC_EA0_WRREQ[2],TCC_EA0_WRREQ_64B[2],TCC_EA0_WRREQ_LEVEL[2],TCC_HIT[2],TCC_EA0_WRREQ[3],TCC_EA0_WRREQ_64B[3],TCC_EA0_WRREQ_LEVEL[3],TCC_HIT[3],TCC_EA0_WRREQ[4],TCC_EA0_WRREQ_64B[4],TCC_EA0_WRREQ_LEVEL[4],TCC_HIT[4],TCC_EA0_WRREQ[5],TCC_EA0_WRREQ_64B[5],TCC_EA0_WRREQ_LEVEL[5],TCC_HIT[5],TCC_EA0_WRREQ[6],TCC_EA0_WRREQ_64B[6],TCC_EA0_WRREQ_LEVEL[6],TCC_HIT[6],TCC_EA0_WRREQ[7],TCC_EA0_WRREQ_64B[7],TCC_EA0_WRREQ_LEVEL[7],TCC_HIT[7],TCC_EA0_WRREQ[8],TCC_EA0_WRREQ_64B[8],TCC_EA0_WRREQ_LEVEL[8],TCC_HIT[8],TCC_EA0_WRREQ[9],TCC_EA0_WRREQ_64B[9],TCC_EA0_WRREQ_LEVEL[9],TCC_HIT[9],TCC_EA0_WRREQ[10],TCC_EA0_WRREQ_64B[10],TCC_EA0_WRREQ_LEVEL[10],TCC_HIT[10],TCC_EA0_WRREQ[11],TCC_EA0_WRREQ_64B[11],TCC_EA0_WRREQ_LEVEL[11],TCC_HIT[11],TCC_EA0_WRREQ[12],TCC_EA0_WRREQ_64B[12],TCC_EA0_WRREQ_LEVEL[12],TCC_HIT[12],TCC_EA0_WRREQ[13],TCC_EA0_WRREQ_64B[13],TCC_EA0_WRREQ_LEVEL[13],TCC_HIT[13],TCC_EA0_WRREQ[14],TCC_EA0_WRREQ_64B[14],TCC_EA0_WRREQ_LEVEL[14],TCC_HIT[14],TCC_EA0_WRREQ[15],TCC_EA0_WRREQ_64B[15],TCC_EA0_WRREQ_LEVEL[15],TCC_HIT[15],TCC_EA0_WRREQ[16],TCC_EA0_WRREQ_64B[16],TCC_EA0_WRREQ_LEVEL[16],TCC_HIT[16],TCC_EA0_WRREQ[17],TCC_EA0_WRREQ_64B[17],TCC_EA0_WRREQ_LEVEL[17],TCC_HIT[17],TCC_EA0_WRREQ[18],TCC_EA0_WRREQ_64B[18],TCC_EA0_WRREQ_LEVEL[18],TCC_HIT[18],TCC_EA0_WRREQ[19],TCC_EA0_WRREQ_64B[19],TCC_EA0_WRREQ_LEVEL[19],TCC_HIT[19],TCC_EA0_WRREQ[20],TCC_EA0_WRREQ_64B[20],TCC_EA0_WRREQ_LEVEL[20],TCC_HIT[20],TCC_EA0_WRREQ[21],TCC_EA0_WRREQ_64B[21],TCC_EA0_WRREQ_LEVEL[21],TCC_HIT[21],TCC_EA0_WRREQ[22],TCC_EA0_WRREQ_64B[22],TCC_EA0_WRREQ_LEVEL[22],TCC_HIT[22],TCC_EA0_WRREQ[23],TCC_EA0_WRREQ_64B[23],TCC_EA0_WRREQ_LEVEL[23],TCC_HIT[23],TCC_EA0_WRREQ[24],TCC_EA0_WRREQ_64B[24],TCC_EA0_WRREQ_LEVEL[24],TCC_HIT[24],TCC_EA0_WRREQ[25],TCC_EA0_WRREQ_64B[25],TCC_EA0_WRREQ_LEVEL[25],TCC_HIT[25],TCC_EA0_WRREQ[26],TCC_EA0_WRREQ_64B[26],TCC_EA0_WRREQ_LEVEL[26],TCC_HIT[26],TCC_EA0_WRREQ[27],TCC_EA0_WRREQ_64B[27],TCC_EA0_WRREQ_LEVEL[27],TCC_HIT[27],TCC_EA0_WRREQ[28],TCC_EA0_WRREQ_64B[28],TCC_EA0_WRREQ_LEVEL[28],TCC_HIT[28],TCC_EA0_WRREQ[29],TCC_EA0_WRREQ_64B[29],TCC_EA0_WRREQ_LEVEL[29],TCC_HIT[29],TCC_EA0_WRREQ[30],TCC_EA0_WRREQ_64B[30],TCC_EA0_WRREQ_LEVEL[30],TCC_HIT[30],TCC_EA0_WRREQ[31],TCC_EA0_WRREQ_64B[31],TCC_EA0_WRREQ_LEVEL[31],TCC_HIT[31],TCC_EA0_WRREQ[32],TCC_EA0_WRREQ_64B[32],TCC_EA0_WRREQ_LEVEL[32],TCC_HIT[32],TCC_EA0_WRREQ[33],TCC_EA0_WRREQ_64B[33],TCC_EA0_WRREQ_LEVEL[33],TCC_HIT[33],TCC_EA0_WRREQ[34],TCC_EA0_WRREQ_64B[34],TCC_EA0_WRREQ_LEVEL[34],TCC_HIT[34],TCC_EA0_WRREQ[35],TCC_EA0_WRREQ_64B[35],TCC_EA0_WRREQ_LEVEL[35],TCC_HIT[35],TCC_EA0_WRREQ[36],TCC_EA0_WRREQ_64B[36],TCC_EA0_WRREQ_LEVEL[36],TCC_HIT[36],TCC_EA0_WRREQ[37],TCC_EA0_WRREQ_64B[37],TCC_EA0_WRREQ_LEVEL[37],TCC_HIT[37],TCC_EA0_WRREQ[38],TCC_EA0_WRREQ_64B[38],TCC_EA0_WRREQ_LEVEL[38],TCC_HIT[38],TCC_EA0_WRREQ[39],TCC_EA0_WRREQ_64B[39],TCC_EA0_WRREQ_LEVEL[39],TCC_HIT[39],TCC_EA0_WRREQ[40],TCC_EA0_WRREQ_64B[40],TCC_EA0_WRREQ_LEVEL[40],TCC_HIT[40],TCC_EA0_WRREQ[41],TCC_EA0_WRREQ_64B[41],TCC_EA0_WRREQ_LEVEL[41],TCC_HIT[41],TCC_EA0_WRREQ[42],TCC_EA0_WRREQ_64B[42],TCC_EA0_WRREQ_LEVEL[42],TCC_HIT[42],TCC_EA0_WRREQ[43],TCC_EA0_WRREQ_64B[43],TCC_EA0_WRREQ_LEVEL[43],TCC_HIT[43],TCC_EA0_WRREQ[44],TCC_EA0_WRREQ_64B[44],TCC_EA0_WRREQ_LEVEL[44],TCC_HIT[44],TCC_EA0_WRREQ[45],TCC_EA0_WRREQ_64B[45],TCC_EA0_WRREQ_LEVEL[45],TCC_HIT[45],TCC_EA0_WRREQ[46],TCC_EA0_WRREQ_64B[46],TCC_EA0_WRREQ_LEVEL[46],TCC_HIT[46],TCC_EA0_WRREQ[47],TCC_EA0_WRREQ_64B[47],TCC_EA0_WRREQ_LEVEL[47],TCC_HIT[47],TCC_EA0_WRREQ[48],TCC_EA0_WRREQ_64B[48],TCC_EA0_WRREQ_LEVEL[48],TCC_HIT[48],TCC_EA0_WRREQ[49],TCC_EA0_WRREQ_64B[49],TCC_EA0_WRREQ_LEVEL[49],TCC_HIT[49],TCC_EA0_WRREQ[50],TCC_EA0_WRREQ_64B[50],TCC_EA0_WRREQ_LEVEL[50],TCC_HIT[50],TCC_EA0_WRREQ[51],TCC_EA0_WRREQ_64B[51],TCC_EA0_WRREQ_LEVEL[51],TCC_HIT[51],TCC_EA0_WRREQ[52],TCC_EA0_WRREQ_64B[52],TCC_EA0_WRREQ_LEVEL[52],TCC_HIT[52],TCC_EA0_WRREQ[53],TCC_EA0_WRREQ_64B[53],TCC_EA0_WRREQ_LEVEL[53],TCC_HIT[53],TCC_EA0_WRREQ[54],TCC_EA0_WRREQ_64B[54],TCC_EA0_WRREQ_LEVEL[54],TCC_HIT[54],TCC_EA0_WRREQ[55],TCC_EA0_WRREQ_64B[55],TCC_EA0_WRREQ_LEVEL[55],TCC_HIT[55],TCC_EA0_WRREQ[56],TCC_EA0_WRREQ_64B[56],TCC_EA0_WRREQ_LEVEL[56],TCC_HIT[56],TCC_EA0_WRREQ[57Line truncated
+0,11995,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",0,16384.0,16384.0,12387648.0,1138074.0,278528.0,0.0,0.0,98304.0,398913.0,0.0,0.0,454687.0,157537.0,32768.0,131072.0,131072.0,131072.0,0.0,0.0,524288.0,453385.0,1824.0,64,0,0,1368.0,1368.0,537584.0,684.0,1368.0,1368.0,548806.0,684.0,1368.0,1368.0,549912.0,684.0,1368.0,1368.0,556551.0,684.0,1368.0,1368.0,545651.0,684.0,1368.0,1368.0,549555.0,684.0,1368.0,1368.0,557916.0,684.0,1368.0,1368.0,552454.0,742.0,1364.0,1364.0,536939.0,682.0,1364.0,1364.0,544312.0,682.0,1364.0,1364.0,554305.0,682.0,1364.0,1364.0,555837.0,701.0,1364.0,1364.0,543651.0,682.0,1364.0,1364.0,547792.0,682.0,1364.0,1364.0,568432.0,682.0,1364.0,1364.0,566416.0,682.0,1368.0,1368.0,543112.0,684.0,1368.0,1368.0,551021.0,684.0,1368.0,1368.0,562335.0,684.0,1368.0,1368.0,563208.0,703.0,1368.0,1368.0,553949.0,684.0,1368.0,1368.0,559453.0,684.0,1368.0,1368.0,572862.0,684.0,1368.0,1368.0,571276.0,684.0,1364.0,1364.0,549247.0,682.0,1364.0,1364.0,559462.0,682.0,1364.0,1364.0,559186.0,682.0,1364.0,1364.0,567926.0,682.0,1364.0,1364.0,557839.0,682.0,1364.0,1364.0,562068.0,682.0,1364.0,1364.0,569573.0,682.0,1364.0,1364.0,563775.0,740.0,1368.0,1368.0,546945.0,684.0,1368.0,1368.0,554211.0,684.0,1368.0,1368.0,564366.0,684.0,1368.0,1368.0,563877.0,703.0,1368.0,1368.0,552908.0,684.0,1368.0,1368.0,557966.0,684.0,1368.0,1368.0,569708.0,684.0,1368.0,1368.0,565168.0,684.0,1360.0,1360.0,554200.0,680.0,1360.0,1360.0,565282.0,680.0,1360.0,1360.0,565292.0,680.0,1360.0,1360.0,570854.0,680.0,1360.0,1360.0,566357.0,680.0,1360.0,1360.0,572723.0,680.0,1360.0,1360.0,578922.0,680.0,1360.0,1360.0,579827.0,738.0,1368.0,1368.0,545248.0,684.0,1368.0,1368.0,558411.0,684.0,1368.0,1368.0,555152.0,684.0,1368.0,1368.0,560946.0,684.0,1368.0,1368.0,552698.0,684.0,1368.0,1368.0,556282.0,684.0,1368.0,1368.0,564103.0,684.0,1368.0,1368.0,557005.0,742.0,1360.0,1360.0,547707.0,680.0,1360.0,1360.0,554719.0,680.0,1360.0,1360.0,566315.0,680.0,1360.0,1360.0,565434.0,699.0,1360.0,1360.0,554125.0,680.0,1360.0,1360.0,557684.0,680.0,1360.0,1360.0,574455.0,680.0,1360.0,1360.0,569959.0,680.0,1364.0,1364.0,534049.0,682.0,1364.0,1364.0,545154.0,682.0,1364.0,1364.0,540861.0,682.0,1364.0,1364.0,547699.0,701.0,1364.0,1364.0,540633.0,682.0,1364.0,1364.0,543734.0,682.0,1364.0,1364.0,551502.0,682.0,1364.0,1364.0,545999.0,682.0,1368.0,1368.0,540682.0,684.0,1368.0,1368.0,548568.0,684.0,1368.0,1368.0,556744.0,684.0,1368.0,1368.0,557924.0,684.0,1368.0,1368.0,550758.0,684.0,1368.0,1368.0,550844.0,684.0,1368.0,1368.0,566334.0,684.0,1368.0,1368.0,561822.0,742.0,1364.0,1364.0,533619.0,682.0,1364.0,1364.0,537093.0,682.0,1364.0,1364.0,545045.0,682.0,1364.0,1364.0,544535.0,682.0,1364.0,1364.0,539323.0,682.0,1364.0,1364.0,543890.0,682.0,1364.0,1364.0,555279.0,682.0,1364.0,1364.0,551390.0,740.0,1368.0,1368.0,532856.0,684.0,1368.0,1368.0,542968.0,684.0,1368.0,1368.0,540247.0,684.0,1368.0,1368.0,547722.0,703.0,1368.0,1368.0,535490.0,684.0,1368.0,1368.0,538740.0,684.0,1368.0,1368.0,550221.0,684.0,1368.0,1368.0,543098.0,684.0,64,0,6291456.0,65536.0,0.0,0.0,0.0,16384.0,0.0,0.0,0.0,0.0,16384.0,32768.0,49515.0,65585.0,16021.0,153064.0,0.0,0.0,0.0,0.0,64,0,0,1351.0,0.0,1368.0,1362.0,0.0,1368.0,1401.0,0.0,1368.0,1411.0,0.0,1368.0,1538.0,0.0,1368.0,1268.0,0.0,1368.0,1691.0,0.0,1368.0,1589.0,0.0,1368.0,1709.0,0.0,1364.0,1405.0,0.0,1364.0,1808.0,0.0,1364.0,1633.0,0.0,1364.0,1727.0,0.0,1364.0,1698.0,0.0,1364.0,1655.0,0.0,1364.0,1656.0,0.0,1364.0,1983.0,0.0,1368.0,1693.0,0.0,1368.0,2099.0,0.0,1368.0,1914.0,0.0,1368.0,2037.0,0.0,1368.0,2063.0,0.0,1368.0,2050.0,0.0,1368.0,2052.0,0.0,1368.0,1615.0,0.0,1364.0,1625.0,0.0,1364.0,1731.0,0.0,1364.0,1703.0,0.0,1364.0,1983.0,0.0,1364.0,1517.0,0.0,1364.0,2050.0,0.0,1364.0,1842.0,0.0,1364.0,1919.0,0.0,1364.0,1534.0,0.0,1364.0,1966.0,0.0,1364.0,1780.0,0.0,1364.0,1980.0,0.0,1364.0,1973.0,0.0,1364.0,1924.0,0.0,1364.0,1965.0,0.0,1364.0,1500.0,0.0,1368.0,1504.0,0.0,1368.0,1552.0,0.0,1368.0,1565.0,0.0,1368.0,1768.0,0.0,1368.0,1504.0,0.0,1368.0,1914.0,0.0,1368.0,1702.0,0.0,1368.0,1551.0,0.0,1364.0,1535.0,0.0,1364.0,1616.0,0.0,1364.0,1585.0,0.0,1364.0,1925.0,0.0,1364.0,1576.0,0.0,1364.0,2017.0,0.0,1364.0,1811.0,0.0,1364.0,1774.0,0.0,1368.0,1338.0,0.0,1368.0,1742.0,0.0,1368.0,1625.0,0.0,1368.0,1717.0,0.0,1368.0,1703.0,0.0,1368.0,1739.0,0.0,1368.0,1877.0,0.0,1368.0,2036.0,0.0,1368.0,1633.0,0.0,1368.0,1969.0,0.0,1368.0,1830.0,0.0,1368.0,1947.0,0.0,1368.0,1999.0,0.0,1368.0,1932.0,0.0,1368.0,1969.0,0.0,1368.0,1496.0,0.0,1360.0,1518.0,0.0,1360.0,1550.0,0.0,1360.0,1578.0,0.0,1360.0,1887.0,0.0,1360.0,1611.0,0.0,1360.0,1959.0,0.0,1360.0,1844.0,0.0,1360.0,1529.0,0.0,1368.0,1539.0,0.0,1368.0,1523.0,0.0,1368.0,1549.0,0.0,1368.0,1933.0,0.0,1368.0,1578.0,0.0,1368.0,2027.0,0.0,1368.0,1781.0,0.0,1368.0,1932.0,0.0,1360.0,1596.0,0.0,1360.0,1952.0,0.0,1360.0,1743.0,0.0,1360.0,1874.0,0.0,1360.0,1908.0,0.0,1360.0,1892.0,0.0,1360.0,1917.0,0.0,1360.0,64,0,0.0,49152.0,32768.0,65536.0,32768.0,0.0,0.0,0.0,11459.0,0.0,510.0,580842.0,78.0,0.0,0.0,0.Line truncated
+1,11995,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",0,16384.0,16384.0,10066975.0,940757.0,278528.0,0.0,0.0,98304.0,254931.0,0.0,0.0,468882.0,108356.0,32768.0,131072.0,131072.0,131072.0,0.0,0.0,524288.0,454178.0,1824.0,64,0,0,1364.0,1364.0,585195.0,682.0,1364.0,1364.0,595774.0,682.0,1364.0,1364.0,583238.0,682.0,1364.0,1364.0,603823.0,682.0,1364.0,1364.0,580972.0,682.0,1364.0,1364.0,584435.0,682.0,1364.0,1364.0,593731.0,682.0,1364.0,1364.0,588036.0,682.0,1368.0,1368.0,564379.0,684.0,1368.0,1368.0,573381.0,684.0,1368.0,1368.0,584276.0,684.0,1368.0,1368.0,578209.0,703.0,1368.0,1368.0,578420.0,684.0,1368.0,1368.0,583856.0,684.0,1368.0,1368.0,588343.0,684.0,1368.0,1368.0,583570.0,684.0,1368.0,1368.0,566010.0,684.0,1368.0,1368.0,576739.0,684.0,1368.0,1368.0,583435.0,684.0,1368.0,1368.0,586287.0,703.0,1368.0,1368.0,587987.0,684.0,1368.0,1368.0,586531.0,684.0,1368.0,1368.0,597751.0,684.0,1368.0,1368.0,598874.0,684.0,1360.0,1360.0,564687.0,680.0,1360.0,1360.0,575862.0,680.0,1360.0,1360.0,576678.0,680.0,1360.0,1360.0,581308.0,680.0,1360.0,1360.0,570035.0,680.0,1360.0,1360.0,576784.0,680.0,1360.0,1360.0,581307.0,680.0,1360.0,1360.0,575828.0,680.0,1360.0,1360.0,567059.0,680.0,1360.0,1360.0,572504.0,680.0,1360.0,1360.0,581874.0,680.0,1360.0,1360.0,580653.0,699.0,1360.0,1360.0,574208.0,680.0,1360.0,1360.0,580421.0,680.0,1360.0,1360.0,587195.0,680.0,1360.0,1360.0,582966.0,680.0,1368.0,1368.0,569399.0,684.0,1368.0,1368.0,584422.0,684.0,1368.0,1368.0,578418.0,684.0,1368.0,1368.0,588399.0,684.0,1368.0,1368.0,570052.0,684.0,1368.0,1368.0,575038.0,684.0,1368.0,1368.0,580105.0,684.0,1368.0,1368.0,575651.0,684.0,1368.0,1368.0,592817.0,684.0,1368.0,1368.0,605908.0,684.0,1368.0,1368.0,599588.0,684.0,1368.0,1368.0,603207.0,684.0,1368.0,1368.0,596751.0,684.0,1368.0,1368.0,597965.0,684.0,1368.0,1368.0,606415.0,684.0,1368.0,1368.0,600341.0,684.0,1364.0,1364.0,558096.0,682.0,1364.0,1364.0,567937.0,682.0,1364.0,1364.0,573365.0,682.0,1364.0,1364.0,573342.0,701.0,1364.0,1364.0,563863.0,682.0,1364.0,1364.0,565583.0,682.0,1364.0,1364.0,579052.0,682.0,1364.0,1364.0,574626.0,682.0,1368.0,1368.0,582374.0,684.0,1368.0,1368.0,591608.0,684.0,1368.0,1368.0,604800.0,684.0,1368.0,1368.0,598985.0,703.0,1368.0,1368.0,588857.0,684.0,1368.0,1368.0,594055.0,684.0,1368.0,1368.0,605446.0,684.0,1368.0,1368.0,598847.0,684.0,1364.0,1364.0,551123.0,682.0,1364.0,1364.0,558792.0,682.0,1364.0,1364.0,565965.0,682.0,1364.0,1364.0,564802.0,682.0,1364.0,1364.0,552515.0,682.0,1364.0,1364.0,556617.0,682.0,1364.0,1364.0,573608.0,682.0,1364.0,1364.0,569570.0,682.0,1368.0,1368.0,551623.0,684.0,1368.0,1368.0,558973.0,684.0,1368.0,1368.0,570786.0,684.0,1368.0,1368.0,567784.0,684.0,1368.0,1368.0,559860.0,684.0,1368.0,1368.0,565035.0,684.0,1368.0,1368.0,577400.0,684.0,1368.0,1368.0,574936.0,684.0,1364.0,1364.0,565185.0,682.0,1364.0,1364.0,578538.0,682.0,1364.0,1364.0,570335.0,682.0,1364.0,1364.0,578910.0,701.0,1364.0,1364.0,568385.0,682.0,1364.0,1364.0,574898.0,682.0,1364.0,1364.0,585976.0,682.0,1364.0,1364.0,579896.0,682.0,64,0,6291456.0,65536.0,0.0,0.0,0.0,16384.0,0.0,0.0,0.0,0.0,16384.0,32768.0,49217.0,65602.0,16319.0,152663.0,0.0,0.0,0.0,0.0,64,0,0,1181.0,0.0,1364.0,1136.0,0.0,1364.0,1203.0,0.0,1364.0,1223.0,0.0,1364.0,1158.0,0.0,1364.0,1138.0,0.0,1364.0,1233.0,0.0,1364.0,1175.0,0.0,1364.0,1481.0,0.0,1368.0,1497.0,0.0,1368.0,1472.0,0.0,1368.0,1527.0,0.0,1368.0,1307.0,0.0,1368.0,1332.0,0.0,1368.0,1445.0,0.0,1368.0,1502.0,0.0,1368.0,1600.0,0.0,1364.0,1607.0,0.0,1364.0,1645.0,0.0,1364.0,1666.0,0.0,1364.0,1702.0,0.0,1364.0,1688.0,0.0,1364.0,1680.0,0.0,1364.0,1701.0,0.0,1364.0,1025.0,0.0,1368.0,990.0,0.0,1368.0,1026.0,0.0,1368.0,998.0,0.0,1368.0,1230.0,0.0,1368.0,1203.0,0.0,1368.0,1194.0,0.0,1368.0,1165.0,0.0,1368.0,1351.0,0.0,1368.0,1401.0,0.0,1368.0,1487.0,0.0,1368.0,1442.0,0.0,1368.0,1540.0,0.0,1368.0,1495.0,0.0,1368.0,1528.0,0.0,1368.0,1534.0,0.0,1368.0,1566.0,0.0,1364.0,1549.0,0.0,1364.0,1543.0,0.0,1364.0,1556.0,0.0,1364.0,1650.0,0.0,1364.0,1618.0,0.0,1364.0,1700.0,0.0,1364.0,1680.0,0.0,1364.0,1504.0,0.0,1360.0,1456.0,0.0,1360.0,1347.0,0.0,1360.0,1345.0,0.0,1360.0,1518.0,0.0,1360.0,1565.0,0.0,1360.0,1486.0,0.0,1360.0,1477.0,0.0,1360.0,1559.0,0.0,1368.0,1560.0,0.0,1368.0,1521.0,0.0,1368.0,1500.0,0.0,1368.0,1488.0,0.0,1368.0,1601.0,0.0,1368.0,1573.0,0.0,1368.0,1590.0,0.0,1368.0,1513.0,0.0,1360.0,1506.0,0.0,1360.0,1504.0,0.0,1360.0,1497.0,0.0,1360.0,1474.0,0.0,1360.0,1523.0,0.0,1360.0,1461.0,0.0,1360.0,1522.0,0.0,1360.0,1542.0,0.0,1368.0,1496.0,0.0,1368.0,1569.0,0.0,1368.0,1541.0,0.0,1368.0,1630.0,0.0,1368.0,1670.0,0.0,1368.0,1733.0,0.0,1368.0,1708.0,0.0,1368.0,1595.0,0.0,1368.0,1501.0,0.0,1368.0,1597.0,0.0,1368.0,1569.0,0.0,1368.0,1668.0,0.0,1368.0,1719.0,0.0,1368.0,1683.0,0.0,1368.0,1672.0,0.0,1368.0,1470.0,0.0,1364.0,1484.0,0.0,1364.0,1503.0,0.0,1364.0,1501.0,0.0,1364.0,1542.0,0.0,1364.0,1601.0,0.0,1364.0,1485.0,0.0,1364.0,1526.0,0.0,1364.0,64,0,0.0,49152.0,32768.0,65536.0,32768.0,0.0,0.0,0.0,7171.0,0.0,5462.0,562426.0,77.0,0.0,0.0,0.0,6Line truncated
+2,11995,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",0,16384.0,16384.0,10012038.0,922562.0,278528.0,0.0,0.0,98304.0,252839.0,0.0,0.0,422883.0,112244.0,32768.0,131072.0,131072.0,131072.0,0.0,0.0,524288.0,454301.0,1824.0,64,0,0,1360.0,1360.0,571145.0,680.0,1360.0,1360.0,583430.0,680.0,1360.0,1360.0,580829.0,680.0,1360.0,1360.0,586858.0,680.0,1360.0,1360.0,572745.0,680.0,1360.0,1360.0,579241.0,680.0,1360.0,1360.0,584497.0,680.0,1360.0,1360.0,577046.0,680.0,1368.0,1368.0,568757.0,684.0,1368.0,1368.0,577724.0,684.0,1368.0,1368.0,586667.0,684.0,1368.0,1368.0,585845.0,703.0,1368.0,1368.0,578888.0,684.0,1368.0,1368.0,585170.0,684.0,1368.0,1368.0,595059.0,684.0,1368.0,1368.0,590526.0,684.0,1360.0,1360.0,559312.0,680.0,1360.0,1360.0,567118.0,680.0,1360.0,1360.0,579685.0,680.0,1360.0,1360.0,578840.0,699.0,1360.0,1360.0,571946.0,680.0,1360.0,1360.0,576552.0,680.0,1360.0,1360.0,585137.0,680.0,1360.0,1360.0,578710.0,680.0,1368.0,1368.0,570497.0,684.0,1368.0,1368.0,584798.0,684.0,1368.0,1368.0,581645.0,684.0,1368.0,1368.0,592236.0,684.0,1368.0,1368.0,578422.0,684.0,1368.0,1368.0,583217.0,684.0,1368.0,1368.0,596084.0,684.0,1368.0,1368.0,583128.0,684.0,1364.0,1364.0,551706.0,682.0,1364.0,1364.0,559403.0,682.0,1364.0,1364.0,571179.0,682.0,1364.0,1364.0,571604.0,701.0,1364.0,1364.0,560875.0,682.0,1364.0,1364.0,562751.0,682.0,1364.0,1364.0,573738.0,682.0,1364.0,1364.0,568289.0,682.0,1368.0,1368.0,595423.0,684.0,1368.0,1368.0,609112.0,684.0,1368.0,1368.0,607257.0,684.0,1368.0,1368.0,634065.0,684.0,1368.0,1368.0,613814.0,684.0,1368.0,1368.0,619274.0,684.0,1368.0,1368.0,612235.0,684.0,1368.0,1368.0,608572.0,684.0,1364.0,1364.0,556161.0,682.0,1364.0,1364.0,566324.0,682.0,1364.0,1364.0,568367.0,682.0,1364.0,1364.0,583439.0,682.0,1364.0,1364.0,566930.0,682.0,1364.0,1364.0,569721.0,682.0,1364.0,1364.0,577071.0,682.0,1364.0,1364.0,572025.0,682.0,1368.0,1368.0,582809.0,684.0,1368.0,1368.0,593196.0,684.0,1368.0,1368.0,599773.0,684.0,1368.0,1368.0,603406.0,703.0,1368.0,1368.0,605351.0,684.0,1368.0,1368.0,592499.0,684.0,1368.0,1368.0,608820.0,684.0,1368.0,1368.0,597978.0,684.0,1364.0,1364.0,553138.0,682.0,1364.0,1364.0,564617.0,682.0,1364.0,1364.0,567241.0,682.0,1364.0,1364.0,573805.0,701.0,1364.0,1364.0,566186.0,682.0,1364.0,1364.0,571883.0,682.0,1364.0,1364.0,573754.0,682.0,1364.0,1364.0,570797.0,682.0,1368.0,1368.0,562234.0,684.0,1368.0,1368.0,574291.0,684.0,1368.0,1368.0,577159.0,684.0,1368.0,1368.0,576520.0,684.0,1368.0,1368.0,567687.0,684.0,1368.0,1368.0,571832.0,684.0,1368.0,1368.0,585854.0,684.0,1368.0,1368.0,583904.0,684.0,1364.0,1364.0,563576.0,682.0,1364.0,1364.0,560157.0,682.0,1364.0,1364.0,568286.0,682.0,1364.0,1364.0,568340.0,682.0,1364.0,1364.0,560479.0,682.0,1364.0,1364.0,565396.0,682.0,1364.0,1364.0,580487.0,682.0,1364.0,1364.0,576553.0,682.0,1368.0,1368.0,555038.0,684.0,1368.0,1368.0,565503.0,684.0,1368.0,1368.0,564728.0,684.0,1368.0,1368.0,570612.0,703.0,1368.0,1368.0,555159.0,684.0,1368.0,1368.0,558967.0,684.0,1368.0,1368.0,559923.0,684.0,1368.0,1368.0,570416.0,684.0,64,0,6291456.0,65536.0,0.0,0.0,0.0,16384.0,0.0,0.0,0.0,0.0,16384.0,32768.0,49181.0,65579.0,16355.0,152868.0,0.0,0.0,0.0,0.0,64,0,0,1118.0,0.0,1368.0,1099.0,0.0,1368.0,1058.0,0.0,1368.0,983.0,0.0,1368.0,1163.0,0.0,1368.0,1134.0,0.0,1368.0,1215.0,0.0,1368.0,1176.0,0.0,1368.0,1739.0,0.0,1364.0,1845.0,0.0,1364.0,1571.0,0.0,1364.0,1580.0,0.0,1364.0,1670.0,0.0,1364.0,1637.0,0.0,1364.0,1604.0,0.0,1364.0,1644.0,0.0,1364.0,1183.0,0.0,1368.0,1098.0,0.0,1368.0,1156.0,0.0,1368.0,1151.0,0.0,1368.0,1245.0,0.0,1368.0,1217.0,0.0,1368.0,1224.0,0.0,1368.0,1283.0,0.0,1368.0,1692.0,0.0,1364.0,1593.0,0.0,1364.0,1476.0,0.0,1364.0,1340.0,0.0,1364.0,1859.0,0.0,1364.0,1769.0,0.0,1364.0,1683.0,0.0,1364.0,1598.0,0.0,1364.0,1462.0,0.0,1368.0,1489.0,0.0,1368.0,1501.0,0.0,1368.0,1537.0,0.0,1368.0,1504.0,0.0,1368.0,1513.0,0.0,1368.0,1432.0,0.0,1368.0,1554.0,0.0,1368.0,1437.0,0.0,1360.0,1390.0,0.0,1360.0,1383.0,0.0,1360.0,1435.0,0.0,1360.0,1437.0,0.0,1360.0,1482.0,0.0,1360.0,1498.0,0.0,1360.0,1485.0,0.0,1360.0,1555.0,0.0,1368.0,1493.0,0.0,1368.0,1487.0,0.0,1368.0,1486.0,0.0,1368.0,1539.0,0.0,1368.0,1623.0,0.0,1368.0,1573.0,0.0,1368.0,1561.0,0.0,1368.0,1426.0,0.0,1360.0,1430.0,0.0,1360.0,1432.0,0.0,1360.0,1428.0,0.0,1360.0,1499.0,0.0,1360.0,1495.0,0.0,1360.0,1465.0,0.0,1360.0,1500.0,0.0,1360.0,1512.0,0.0,1364.0,1516.0,0.0,1364.0,1446.0,0.0,1364.0,1445.0,0.0,1364.0,1475.0,0.0,1364.0,1508.0,0.0,1364.0,1401.0,0.0,1364.0,1457.0,0.0,1364.0,1765.0,0.0,1368.0,1748.0,0.0,1368.0,1732.0,0.0,1368.0,1750.0,0.0,1368.0,1680.0,0.0,1368.0,1721.0,0.0,1368.0,1741.0,0.0,1368.0,1721.0,0.0,1368.0,1628.0,0.0,1364.0,1423.0,0.0,1364.0,1494.0,0.0,1364.0,1484.0,0.0,1364.0,1604.0,0.0,1364.0,1621.0,0.0,1364.0,1639.0,0.0,1364.0,1462.0,0.0,1364.0,1656.0,0.0,1368.0,1666.0,0.0,1368.0,1622.0,0.0,1368.0,1544.0,0.0,1368.0,1576.0,0.0,1368.0,1656.0,0.0,1368.0,1763.0,0.0,1368.0,1772.0,0.0,1368.0,64,0,0.0,49152.0,32768.0,65536.0,32768.0,0.0,0.0,0.0,7256.0,0.0,5443.0,539846.0,0.0,0.0,0.0,0.0,6Line truncated
@@ -0,0 +1,2 @@
+workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd
+dispatch_inv,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Wed 29 May 2024 01:30:08 PM  (CDT),2,sh5-1w300-rg3-3,AMD Instinct MI300A Accelerator,"American Megatrends International, LLC.RMO1002DS",Ubuntu 22.04.2 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,131174852,,6.1.2-110,N/A,SPX,NPS1,MI300A_A1,gfx942,32,24576,228,4,24,64,1024,32,2100,1300,2100,1300,96,32,120,4,5324.8,6
@@ -0,0 +1,4 @@
+Dispatch_ID,GPU_ID,Queue_ID,PID,TID,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,Wave_Size,Kernel_Name,Start_Timestamp,End_Timestamp,Correlation_ID
+1,11995,1,142399,142399,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",73285541833672,73285541841404,0
+2,11995,1,142399,142399,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",73285541860632,73285541867162,0
+3,11995,1,142399,142399,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",73285541884388,73285541890838,0
@@ -0,0 +1,4 @@
+Dispatch_ID,GPU_ID,Queue_ID,PID,TID,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,Wave_Size,Kernel_Name,Start_Timestamp,End_Timestamp,Correlation_ID,GRBM_COUNT,GRBM_GUI_ACTIVE,SQ_WAVES,SQ_IFETCH,SQ_IFETCH_LEVEL,SQ_ACCUM_PREV_HIRES
+0,60633,1,960190,960190,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",716011730095458,716011730117977,0,414337.0,414337.0,16384.0,65536.0,32415.0,2598568.0
+1,60633,1,960190,960190,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",716011730139495,716011730153215,0,379448.0,379448.0,16384.0,65536.0,13011.0,1048576.0
+2,60633,1,960190,960190,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",716011730173414,716011730187774,0,335474.0,335474.0,16384.0,65536.0,13087.0,1048576.0
@@ -0,0 +1,4 @@
+Dispatch_ID,GPU_ID,Queue_ID,PID,TID,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,Wave_Size,Kernel_Name,Start_Timestamp,End_Timestamp,Correlation_ID,SQ_INSTS_LDS,SQ_INST_LEVEL_LDS,SQ_ACCUM_PREV_HIRES
+0,60633,1,960217,960217,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",716011730095458,716011730117977,0,0.0,0.0,0.0
+1,60633,1,960217,960217,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",716011730139495,716011730153215,0,0.0,0.0,0.0
+2,60633,1,960217,960217,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",716011730173414,716011730187774,0,0.0,0.0,0.0
@@ -0,0 +1,4 @@
+Dispatch_ID,GPU_ID,Queue_ID,PID,TID,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,Wave_Size,Kernel_Name,Start_Timestamp,End_Timestamp,Correlation_ID,SQ_INSTS_SMEM,SQ_INST_LEVEL_SMEM,SQ_ACCUM_PREV_HIRES
+0,60633,1,960244,960244,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",716011730095458,716011730117977,0,65536.0,3820564.0,305702704.0
+1,60633,1,960244,960244,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",716011730139495,716011730153215,0,65536.0,3956762.0,316492352.0
+2,60633,1,960244,960244,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",716011730173414,716011730187774,0,65536.0,3780070.0,302466928.0
@@ -0,0 +1,4 @@
+Dispatch_ID,GPU_ID,Queue_ID,PID,TID,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,Wave_Size,Kernel_Name,Start_Timestamp,End_Timestamp,Correlation_ID,SQ_INSTS_VMEM,SQ_INST_LEVEL_VMEM,SQ_ACCUM_PREV_HIRES
+0,60633,1,960271,960271,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",716011730095458,716011730117977,0,32768.0,447440.0,35784180.0
+1,60633,1,960271,960271,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",716011730139495,716011730153215,0,32768.0,277891.0,22219424.0
+2,60633,1,960271,960271,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",716011730173414,716011730187774,0,32768.0,291000.0,23271064.0
@@ -0,0 +1,4 @@
+Dispatch_ID,GPU_ID,Queue_ID,PID,TID,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,Wave_Size,Kernel_Name,Start_Timestamp,End_Timestamp,Correlation_ID,GRBM_COUNT,GRBM_GUI_ACTIVE,CPC_ME1_BUSY_FOR_PACKET_DECODE,SQ_CYCLES,SQ_WAVES,SQ_WAVE_CYCLES,SQ_BUSY_CYCLES,SQ_LEVEL_WAVES,SQ_ACCUM_PREV_HIRES
+0,60633,1,960283,960283,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",716011730095458,716011730117977,0,447610.0,447610.0,261596.0,1790440.0,16384.0,34553195.0,562377.0,0.0,138553848.0
+1,60633,1,960283,960283,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",716011730139495,716011730153215,0,423311.0,423311.0,246620.0,1693244.0,16384.0,31439535.0,504434.0,0.0,126111788.0
+2,60633,1,960283,960283,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",716011730173414,716011730187774,0,365800.0,365800.0,194280.0,1463200.0,16384.0,29593510.0,483473.0,0.0,118729636.0
@@ -0,0 +1,202 @@
+Omniperf version: 2.0.0
+Profiler choice: rocprofv2
+Path: /home/colramos/omniperf/tests/workloads/dispatch_inv/MI300X_A1
+Target: MI300X_A1
+Command: ./tests/vcopy -n 1048576 -b 256 -i 3
+Kernel Selection: None
+Dispatch Selection: ['invalid']
+Hardware Blocks: All
+
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+Collecting Performance Counters
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+
+[profiling] Current input file: tests/workloads/dispatch_inv/MI300X_A1/perfmon/SQ_IFETCH_LEVEL.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - GRBM_COUNT
+   |-> [/opt/rocm/bin/rocprofv2] - GRBM_GUI_ACTIVE
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_WAVES
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_IFETCH
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_IFETCH_LEVEL
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_ACCUM_PREV_HIRES
+   |-> [/opt/rocm/bin/rocprofv2] Enabling Counter Collection
+   |-> [/opt/rocm/bin/rocprofv2] vcopy testing on GCD 0
+
+[profiling] Current input file: tests/workloads/dispatch_inv/MI300X_A1/perfmon/SQ_INST_LEVEL_LDS.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_LDS
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INST_LEVEL_LDS
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_ACCUM_PREV_HIRES
+   |-> [/opt/rocm/bin/rocprofv2] Enabling Counter Collection
+   |-> [/opt/rocm/bin/rocprofv2] vcopy testing on GCD 0
+   |-> [/opt/rocm/bin/rocprofv2] Finished allocating vectors on the CPU
+   |-> [/opt/rocm/bin/rocprofv2] Finished allocating vectors on the GPU
+
+[profiling] Current input file: tests/workloads/dispatch_inv/MI300X_A1/perfmon/SQ_INST_LEVEL_SMEM.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_SMEM
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INST_LEVEL_SMEM
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_ACCUM_PREV_HIRES
+   |-> [/opt/rocm/bin/rocprofv2] Enabling Counter Collection
+   |-> [/opt/rocm/bin/rocprofv2] vcopy testing on GCD 0
+
+[profiling] Current input file: tests/workloads/dispatch_inv/MI300X_A1/perfmon/SQ_INST_LEVEL_VMEM.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VMEM
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INST_LEVEL_VMEM
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_ACCUM_PREV_HIRES
+
+[profiling] Current input file: tests/workloads/dispatch_inv/MI300X_A1/perfmon/SQ_LEVEL_WAVES.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - GRBM_COUNT
+   |-> [/opt/rocm/bin/rocprofv2] - GRBM_GUI_ACTIVE
+   |-> [/opt/rocm/bin/rocprofv2] - CPC_ME1_BUSY_FOR_PACKET_DECODE
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_CYCLES
+
+[profiling] Current input file: tests/workloads/dispatch_inv/MI300X_A1/perfmon/pmc_perf_0.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_CYCLES
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_BUSY_CYCLES
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_BUSY_CU_CYCLES
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_WAVES
+
+[profiling] Current input file: tests/workloads/dispatch_inv/MI300X_A1/perfmon/pmc_perf_1.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VMEM
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_SALU
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VSKIPPED
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS
+
+[profiling] Current input file: tests/workloads/dispatch_inv/MI300X_A1/perfmon/pmc_perf_10.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQC_TC_DATA_ATOMIC_REQ
+   |-> [/opt/rocm/bin/rocprofv2] - SQC_TC_STALL
+   |-> [/opt/rocm/bin/rocprofv2] - SQC_TC_REQ
+   |-> [/opt/rocm/bin/rocprofv2] - SQC_DCACHE_REQ_READ_16
+
+[profiling] Current input file: tests/workloads/dispatch_inv/MI300X_A1/perfmon/pmc_perf_11.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQC_DCACHE_INPUT_VALID_READYB
+   |-> [/opt/rocm/bin/rocprofv2] - SQC_DCACHE_ATOMIC
+
+[profiling] Current input file: tests/workloads/dispatch_inv/MI300X_A1/perfmon/pmc_perf_12.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQC_DCACHE_REQ_READ_2
+   |-> [/opt/rocm/bin/rocprofv2] - SQC_DCACHE_REQ_READ_4
+   |-> [/opt/rocm/bin/rocprofv2] Enabling Counter Collection
+   |-> [/opt/rocm/bin/rocprofv2] vcopy testing on GCD 0
+
+[profiling] Current input file: tests/workloads/dispatch_inv/MI300X_A1/perfmon/pmc_perf_13.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_ATOMIC[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_BUBBLE[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_CYCLE[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_EA0_ATOMIC[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_ATOMIC[1]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_BUBBLE[1]
+
+[profiling] Current input file: tests/workloads/dispatch_inv/MI300X_A1/perfmon/pmc_perf_14.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_EA0_ATOMIC_LEVEL[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_EA0_RDREQ[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_EA0_RDREQ_32B[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_EA0_RDREQ_LEVEL[0]
+
+[profiling] Current input file: tests/workloads/dispatch_inv/MI300X_A1/perfmon/pmc_perf_15.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_EA0_WRREQ[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_EA0_WRREQ_64B[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_EA0_WRREQ_LEVEL[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_HIT[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_EA0_WRREQ[1]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_EA0_WRREQ_64B[1]
+
+[profiling] Current input file: tests/workloads/dispatch_inv/MI300X_A1/perfmon/pmc_perf_16.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_MISS[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_READ[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_REQ[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_RW_REQ[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_MISS[1]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_READ[1]
+
+[profiling] Current input file: tests/workloads/dispatch_inv/MI300X_A1/perfmon/pmc_perf_17.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_TAG_STALL[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_TOO_MANY_EA_WRREQS_STALL[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_WRITE[0]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_TAG_STALL[1]
+   |-> [/opt/rocm/bin/rocprofv2] - TCC_TOO_MANY_EA_WRREQS_STALL[1]
+
+[profiling] Current input file: tests/workloads/dispatch_inv/MI300X_A1/perfmon/pmc_perf_2.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_TRANS_F16
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_ADD_F32
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_MUL_F32
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_FMA_F32
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_TRANS_F32
+
+[profiling] Current input file: tests/workloads/dispatch_inv/MI300X_A1/perfmon/pmc_perf_3.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_TRANS_F64
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_INT32
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_INT64
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_SMEM
+
+[profiling] Current input file: tests/workloads/dispatch_inv/MI300X_A1/perfmon/pmc_perf_4.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_BRANCH
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_SENDMSG
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_WAIT_ANY
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_WAIT_INST_ANY
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_ACTIVE_INST_ANY
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_ACTIVE_INST_VMEM
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_ACTIVE_INST_LDS
+
+[profiling] Current input file: tests/workloads/dispatch_inv/MI300X_A1/perfmon/pmc_perf_5.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_ACTIVE_INST_SCA
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_ACTIVE_INST_EXP_GDS
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_ACTIVE_INST_MISC
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_ACTIVE_INST_FLAT
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INST_CYCLES_VMEM_WR
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INST_CYCLES_VMEM_RD
+
+[profiling] Current input file: tests/workloads/dispatch_inv/MI300X_A1/perfmon/pmc_perf_6.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_THREAD_CYCLES_VALU
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_IFETCH
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_LDS_BANK_CONFLICT
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_LDS_ADDR_CONFLICT
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_LDS_UNALIGNED_STALL
+
+[profiling] Current input file: tests/workloads/dispatch_inv/MI300X_A1/perfmon/pmc_perf_7.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_WAVES_LT_32
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_WAVES_LT_16
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_ITEMS
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_LDS_MEM_VIOLATIONS
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_LDS_ATOMIC_RETURN
+
+[profiling] Current input file: tests/workloads/dispatch_inv/MI300X_A1/perfmon/pmc_perf_8.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_SMEM_NORM
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_MFMA
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_MFMA_I8
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_MFMA_F16
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_MFMA_BF16
+
+[profiling] Current input file: tests/workloads/dispatch_inv/MI300X_A1/perfmon/pmc_perf_9.txt
+   |-> [/opt/rocm/bin/rocprofv2] ROCProfilerV2: Collecting the following counters:
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_MFMA_MOPS_I8
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_MFMA_MOPS_F16
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_MFMA_MOPS_BF16
+   |-> [/opt/rocm/bin/rocprofv2] - SQ_INSTS_VALU_MFMA_MOPS_F32
+
+[profiling] Current input file: tests/workloads/dispatch_inv/MI300X_A1/perfmon/timestamps.txt
+   |-> [/opt/rocm/bin/rocprofv2] vcopy testing on GCD 0
+   |-> [/opt/rocm/bin/rocprofv2] Finished allocating vectors on the CPU
+   |-> [/opt/rocm/bin/rocprofv2] Finished allocating vectors on the GPU
+   |-> [/opt/rocm/bin/rocprofv2] Finished copying vectors to the GPU
+[roofline] Roofline temporarily disabled in MI300
@@ -0,0 +1,5 @@
+pmc: GRBM_COUNT GRBM_GUI_ACTIVE SQ_WAVES SQ_IFETCH SQ_IFETCH_LEVEL  SQ_ACCUM_PREV_HIRES
+
+gpu:
+range: invalid
+kernel:
@@ -0,0 +1,5 @@
+pmc: SQ_INSTS_LDS SQ_INST_LEVEL_LDS  SQ_ACCUM_PREV_HIRES
+
+gpu:
+range: invalid
+kernel:
@@ -0,0 +1,5 @@
+pmc: SQ_INSTS_SMEM  SQ_INST_LEVEL_SMEM SQ_ACCUM_PREV_HIRES
+
+gpu:
+range: invalid
+kernel:
@@ -0,0 +1,5 @@
+pmc: SQ_INSTS_VMEM  SQ_INST_LEVEL_VMEM SQ_ACCUM_PREV_HIRES
+
+gpu:
+range: invalid
+kernel:
@@ -0,0 +1,5 @@
+pmc: GRBM_COUNT GRBM_GUI_ACTIVE CPC_ME1_BUSY_FOR_PACKET_DECODE SQ_CYCLES SQ_WAVES SQ_WAVE_CYCLES SQ_BUSY_CYCLES SQ_LEVEL_WAVES  SQ_ACCUM_PREV_HIRES
+
+gpu:
+range: invalid
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQ_CYCLES SQ_BUSY_CYCLES SQ_BUSY_CU_CYCLES SQ_WAVES SQ_WAVE_CYCLES SQ_INSTS_VALU_CVT SQ_INSTS_VMEM_WR SQ_INSTS_VMEM_RD GRBM_COUNT GRBM_GUI_ACTIVE TCP_GATE_EN1_sum TCP_GATE_EN2_sum TCP_TD_TCP_STALL_CYCLES_sum TCP_TCR_TCP_STALL_CYCLES_sum TA_TA_BUSY_sum TA_BUFFER_WAVEFRONTS_sum TD_TD_BUSY_sum TD_TC_STALL_sum SPI_CSN_WINDOW_VALID SPI_CSN_BUSY CPC_CPC_STAT_BUSY CPC_CPC_STAT_IDLE CPF_CPF_STAT_BUSY CPF_CPF_STAT_STALL TCC_CYCLE_sum TCC_BUSY_sum TCC_PROBE_sum TCC_PROBE_ALL_sum
+
+gpu:
+range: invalid
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQ_INSTS_VMEM SQ_INSTS_SALU SQ_INSTS_VSKIPPED SQ_INSTS SQ_INSTS_VALU SQ_INSTS_VALU_ADD_F16 SQ_INSTS_VALU_MUL_F16 SQ_INSTS_VALU_FMA_F16 GRBM_SPI_BUSY TCP_READ_TAGCONFLICT_STALL_CYCLES_sum TCP_WRITE_TAGCONFLICT_STALL_CYCLES_sum TCP_ATOMIC_TAGCONFLICT_STALL_CYCLES_sum TCP_TA_TCP_STATE_READ_sum TA_BUFFER_READ_WAVEFRONTS_sum TA_BUFFER_WRITE_WAVEFRONTS_sum TD_SPI_STALL_sum TD_LOAD_WAVEFRONT_sum SPI_CSN_NUM_THREADGROUPS SPI_CSN_WAVE CPC_CPC_TCIU_BUSY CPC_CPC_TCIU_IDLE CPF_CPF_TCIU_BUSY CPF_CPF_TCIU_STALL TCC_NC_REQ_sum TCC_UC_REQ_sum TCC_CC_REQ_sum TCC_RW_REQ_sum
+
+gpu:
+range: invalid
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQC_TC_DATA_ATOMIC_REQ SQC_TC_STALL SQC_TC_REQ SQC_DCACHE_REQ_READ_16 SQC_ICACHE_REQ SQC_ICACHE_HITS SQC_ICACHE_MISSES SQC_ICACHE_MISSES_DUPLICATE
+
+gpu:
+range: invalid
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQC_DCACHE_INPUT_VALID_READYB SQC_DCACHE_ATOMIC SQC_DCACHE_REQ_READ_8 SQC_DCACHE_REQ SQC_DCACHE_HITS SQC_DCACHE_MISSES SQC_DCACHE_MISSES_DUPLICATE SQC_DCACHE_REQ_READ_1
+
+gpu:
+range: invalid
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQC_DCACHE_REQ_READ_2 SQC_DCACHE_REQ_READ_4
+
+gpu:
+range: invalid
+kernel:
@@ -0,0 +1,5 @@
+pmc:  TCC_ATOMIC[0] TCC_BUBBLE[0] TCC_CYCLE[0] TCC_EA0_ATOMIC[0] TCC_ATOMIC[1] TCC_BUBBLE[1] TCC_CYCLE[1] TCC_EA0_ATOMIC[1] TCC_ATOMIC[2] TCC_BUBBLE[2] TCC_CYCLE[2] TCC_EA0_ATOMIC[2] TCC_ATOMIC[3] TCC_BUBBLE[3] TCC_CYCLE[3] TCC_EA0_ATOMIC[3] TCC_ATOMIC[4] TCC_BUBBLE[4] TCC_CYCLE[4] TCC_EA0_ATOMIC[4] TCC_ATOMIC[5] TCC_BUBBLE[5] TCC_CYCLE[5] TCC_EA0_ATOMIC[5] TCC_ATOMIC[6] TCC_BUBBLE[6] TCC_CYCLE[6] TCC_EA0_ATOMIC[6] TCC_ATOMIC[7] TCC_BUBBLE[7] TCC_CYCLE[7] TCC_EA0_ATOMIC[7] TCC_ATOMIC[8] TCC_BUBBLE[8] TCC_CYCLE[8] TCC_EA0_ATOMIC[8] TCC_ATOMIC[9] TCC_BUBBLE[9] TCC_CYCLE[9] TCC_EA0_ATOMIC[9] TCC_ATOMIC[10] TCC_BUBBLE[10] TCC_CYCLE[10] TCC_EA0_ATOMIC[10] TCC_ATOMIC[11] TCC_BUBBLE[11] TCC_CYCLE[11] TCC_EA0_ATOMIC[11] TCC_ATOMIC[12] TCC_BUBBLE[12] TCC_CYCLE[12] TCC_EA0_ATOMIC[12] TCC_ATOMIC[13] TCC_BUBBLE[13] TCC_CYCLE[13] TCC_EA0_ATOMIC[13] TCC_ATOMIC[14] TCC_BUBBLE[14] TCC_CYCLE[14] TCC_EA0_ATOMIC[14] TCC_ATOMIC[15] TCC_BUBBLE[15] TCC_CYCLE[15] TCC_EA0_ATOMIC[15]
+
+gpu:
+range: invalid
+kernel:
@@ -0,0 +1,5 @@
+pmc:  TCC_EA0_ATOMIC_LEVEL[0] TCC_EA0_RDREQ[0] TCC_EA0_RDREQ_32B[0] TCC_EA0_RDREQ_LEVEL[0] TCC_EA0_ATOMIC_LEVEL[1] TCC_EA0_RDREQ[1] TCC_EA0_RDREQ_32B[1] TCC_EA0_RDREQ_LEVEL[1] TCC_EA0_ATOMIC_LEVEL[2] TCC_EA0_RDREQ[2] TCC_EA0_RDREQ_32B[2] TCC_EA0_RDREQ_LEVEL[2] TCC_EA0_ATOMIC_LEVEL[3] TCC_EA0_RDREQ[3] TCC_EA0_RDREQ_32B[3] TCC_EA0_RDREQ_LEVEL[3] TCC_EA0_ATOMIC_LEVEL[4] TCC_EA0_RDREQ[4] TCC_EA0_RDREQ_32B[4] TCC_EA0_RDREQ_LEVEL[4] TCC_EA0_ATOMIC_LEVEL[5] TCC_EA0_RDREQ[5] TCC_EA0_RDREQ_32B[5] TCC_EA0_RDREQ_LEVEL[5] TCC_EA0_ATOMIC_LEVEL[6] TCC_EA0_RDREQ[6] TCC_EA0_RDREQ_32B[6] TCC_EA0_RDREQ_LEVEL[6] TCC_EA0_ATOMIC_LEVEL[7] TCC_EA0_RDREQ[7] TCC_EA0_RDREQ_32B[7] TCC_EA0_RDREQ_LEVEL[7] TCC_EA0_ATOMIC_LEVEL[8] TCC_EA0_RDREQ[8] TCC_EA0_RDREQ_32B[8] TCC_EA0_RDREQ_LEVEL[8] TCC_EA0_ATOMIC_LEVEL[9] TCC_EA0_RDREQ[9] TCC_EA0_RDREQ_32B[9] TCC_EA0_RDREQ_LEVEL[9] TCC_EA0_ATOMIC_LEVEL[10] TCC_EA0_RDREQ[10] TCC_EA0_RDREQ_32B[10] TCC_EA0_RDREQ_LEVEL[10] TCC_EA0_ATOMIC_LEVEL[11] TCC_EA0_RDREQ[11] TCC_EA0_RDREQ_32B[11] TCC_EA0_RDREQ_LEVEL[11] TCC_EA0_ATOMIC_LEVEL[12] TCC_EA0_RDREQ[12] TCC_EA0_RDREQ_32B[12] TCC_EA0_RDREQ_LEVEL[12] TCC_EA0_ATOMIC_LEVEL[13] TCC_EA0_RDREQ[13] TCC_EA0_RDREQ_32B[13] TCC_EA0_RDREQ_LEVEL[13] TCC_EA0_ATOMIC_LEVEL[14] TCC_EA0_RDREQ[14] TCC_EA0_RDREQ_32B[14] TCC_EA0_RDREQ_LEVEL[14] TCC_EA0_ATOMIC_LEVEL[15] TCC_EA0_RDREQ[15] TCC_EA0_RDREQ_32B[15] TCC_EA0_RDREQ_LEVEL[15]
+
+gpu:
+range: invalid
+kernel:
@@ -0,0 +1,5 @@
+pmc:  TCC_EA0_WRREQ[0] TCC_EA0_WRREQ_64B[0] TCC_EA0_WRREQ_LEVEL[0] TCC_HIT[0] TCC_EA0_WRREQ[1] TCC_EA0_WRREQ_64B[1] TCC_EA0_WRREQ_LEVEL[1] TCC_HIT[1] TCC_EA0_WRREQ[2] TCC_EA0_WRREQ_64B[2] TCC_EA0_WRREQ_LEVEL[2] TCC_HIT[2] TCC_EA0_WRREQ[3] TCC_EA0_WRREQ_64B[3] TCC_EA0_WRREQ_LEVEL[3] TCC_HIT[3] TCC_EA0_WRREQ[4] TCC_EA0_WRREQ_64B[4] TCC_EA0_WRREQ_LEVEL[4] TCC_HIT[4] TCC_EA0_WRREQ[5] TCC_EA0_WRREQ_64B[5] TCC_EA0_WRREQ_LEVEL[5] TCC_HIT[5] TCC_EA0_WRREQ[6] TCC_EA0_WRREQ_64B[6] TCC_EA0_WRREQ_LEVEL[6] TCC_HIT[6] TCC_EA0_WRREQ[7] TCC_EA0_WRREQ_64B[7] TCC_EA0_WRREQ_LEVEL[7] TCC_HIT[7] TCC_EA0_WRREQ[8] TCC_EA0_WRREQ_64B[8] TCC_EA0_WRREQ_LEVEL[8] TCC_HIT[8] TCC_EA0_WRREQ[9] TCC_EA0_WRREQ_64B[9] TCC_EA0_WRREQ_LEVEL[9] TCC_HIT[9] TCC_EA0_WRREQ[10] TCC_EA0_WRREQ_64B[10] TCC_EA0_WRREQ_LEVEL[10] TCC_HIT[10] TCC_EA0_WRREQ[11] TCC_EA0_WRREQ_64B[11] TCC_EA0_WRREQ_LEVEL[11] TCC_HIT[11] TCC_EA0_WRREQ[12] TCC_EA0_WRREQ_64B[12] TCC_EA0_WRREQ_LEVEL[12] TCC_HIT[12] TCC_EA0_WRREQ[13] TCC_EA0_WRREQ_64B[13] TCC_EA0_WRREQ_LEVEL[13] TCC_HIT[13] TCC_EA0_WRREQ[14] TCC_EA0_WRREQ_64B[14] TCC_EA0_WRREQ_LEVEL[14] TCC_HIT[14] TCC_EA0_WRREQ[15] TCC_EA0_WRREQ_64B[15] TCC_EA0_WRREQ_LEVEL[15] TCC_HIT[15]
+
+gpu:
+range: invalid
+kernel:
@@ -0,0 +1,5 @@
+pmc:  TCC_MISS[0] TCC_READ[0] TCC_REQ[0] TCC_RW_REQ[0] TCC_MISS[1] TCC_READ[1] TCC_REQ[1] TCC_RW_REQ[1] TCC_MISS[2] TCC_READ[2] TCC_REQ[2] TCC_RW_REQ[2] TCC_MISS[3] TCC_READ[3] TCC_REQ[3] TCC_RW_REQ[3] TCC_MISS[4] TCC_READ[4] TCC_REQ[4] TCC_RW_REQ[4] TCC_MISS[5] TCC_READ[5] TCC_REQ[5] TCC_RW_REQ[5] TCC_MISS[6] TCC_READ[6] TCC_REQ[6] TCC_RW_REQ[6] TCC_MISS[7] TCC_READ[7] TCC_REQ[7] TCC_RW_REQ[7] TCC_MISS[8] TCC_READ[8] TCC_REQ[8] TCC_RW_REQ[8] TCC_MISS[9] TCC_READ[9] TCC_REQ[9] TCC_RW_REQ[9] TCC_MISS[10] TCC_READ[10] TCC_REQ[10] TCC_RW_REQ[10] TCC_MISS[11] TCC_READ[11] TCC_REQ[11] TCC_RW_REQ[11] TCC_MISS[12] TCC_READ[12] TCC_REQ[12] TCC_RW_REQ[12] TCC_MISS[13] TCC_READ[13] TCC_REQ[13] TCC_RW_REQ[13] TCC_MISS[14] TCC_READ[14] TCC_REQ[14] TCC_RW_REQ[14] TCC_MISS[15] TCC_READ[15] TCC_REQ[15] TCC_RW_REQ[15]
+
+gpu:
+range: invalid
+kernel:
@@ -0,0 +1,5 @@
+pmc:  TCC_TAG_STALL[0] TCC_TOO_MANY_EA_WRREQS_STALL[0] TCC_WRITE[0] TCC_TAG_STALL[1] TCC_TOO_MANY_EA_WRREQS_STALL[1] TCC_WRITE[1] TCC_TAG_STALL[2] TCC_TOO_MANY_EA_WRREQS_STALL[2] TCC_WRITE[2] TCC_TAG_STALL[3] TCC_TOO_MANY_EA_WRREQS_STALL[3] TCC_WRITE[3] TCC_TAG_STALL[4] TCC_TOO_MANY_EA_WRREQS_STALL[4] TCC_WRITE[4] TCC_TAG_STALL[5] TCC_TOO_MANY_EA_WRREQS_STALL[5] TCC_WRITE[5] TCC_TAG_STALL[6] TCC_TOO_MANY_EA_WRREQS_STALL[6] TCC_WRITE[6] TCC_TAG_STALL[7] TCC_TOO_MANY_EA_WRREQS_STALL[7] TCC_WRITE[7] TCC_TAG_STALL[8] TCC_TOO_MANY_EA_WRREQS_STALL[8] TCC_WRITE[8] TCC_TAG_STALL[9] TCC_TOO_MANY_EA_WRREQS_STALL[9] TCC_WRITE[9] TCC_TAG_STALL[10] TCC_TOO_MANY_EA_WRREQS_STALL[10] TCC_WRITE[10] TCC_TAG_STALL[11] TCC_TOO_MANY_EA_WRREQS_STALL[11] TCC_WRITE[11] TCC_TAG_STALL[12] TCC_TOO_MANY_EA_WRREQS_STALL[12] TCC_WRITE[12] TCC_TAG_STALL[13] TCC_TOO_MANY_EA_WRREQS_STALL[13] TCC_WRITE[13] TCC_TAG_STALL[14] TCC_TOO_MANY_EA_WRREQS_STALL[14] TCC_WRITE[14] TCC_TAG_STALL[15] TCC_TOO_MANY_EA_WRREQS_STALL[15] TCC_WRITE[15]
+
+gpu:
+range: invalid
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQ_INSTS_VALU_TRANS_F16 SQ_INSTS_VALU_ADD_F32 SQ_INSTS_VALU_MUL_F32 SQ_INSTS_VALU_FMA_F32 SQ_INSTS_VALU_TRANS_F32 SQ_INSTS_VALU_ADD_F64 SQ_INSTS_VALU_MUL_F64 SQ_INSTS_VALU_FMA_F64 TCP_VOLATILE_sum TCP_TOTAL_ACCESSES_sum TCP_TOTAL_READ_sum TCP_TOTAL_WRITE_sum TA_BUFFER_ATOMIC_WAVEFRONTS_sum TA_BUFFER_TOTAL_CYCLES_sum TD_ATOMIC_WAVEFRONT_sum TD_STORE_WAVEFRONT_sum SPI_RA_REQ_NO_ALLOC SPI_RA_REQ_NO_ALLOC_CSN CPC_CPC_STAT_STALL CPC_UTCL1_STALL_ON_TRANSLATION CPF_CPF_STAT_IDLE CPF_CPF_TCIU_IDLE TCC_REQ_sum TCC_STREAMING_REQ_sum TCC_HIT_sum TCC_MISS_sum
+
+gpu:
+range: invalid
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQ_INSTS_VALU_TRANS_F64 SQ_INSTS_VALU_INT32 SQ_INSTS_VALU_INT64 SQ_INSTS_SMEM SQ_INSTS_FLAT SQ_INSTS_LDS SQ_INSTS_GDS SQ_INSTS_EXP_GDS TCP_TOTAL_ATOMIC_WITH_RET_sum TCP_TOTAL_ATOMIC_WITHOUT_RET_sum TCP_TOTAL_WRITEBACK_INVALIDATES_sum TCP_TOTAL_CACHE_ACCESSES_sum TA_BUFFER_COALESCED_READ_CYCLES_sum TA_BUFFER_COALESCED_WRITE_CYCLES_sum TD_COALESCABLE_WAVEFRONT_sum SPI_RA_RES_STALL_CSN SPI_RA_TMP_STALL_CSN CPC_CPC_UTCL2IU_BUSY CPC_CPC_UTCL2IU_IDLE CPF_CMP_UTCL1_STALL_ON_TRANSLATION TCC_READ_sum TCC_WRITE_sum TCC_ATOMIC_sum TCC_WRITEBACK_sum
+
+gpu:
+range: invalid
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQ_INSTS_BRANCH SQ_INSTS_SENDMSG SQ_WAIT_ANY SQ_WAIT_INST_ANY SQ_ACTIVE_INST_ANY SQ_ACTIVE_INST_VMEM SQ_ACTIVE_INST_LDS SQ_ACTIVE_INST_VALU TCP_UTCL1_TRANSLATION_MISS_sum TCP_UTCL1_TRANSLATION_HIT_sum TCP_UTCL1_PERMISSION_MISS_sum TCP_UTCL1_REQUEST_sum TA_ADDR_STALLED_BY_TC_CYCLES_sum TA_TOTAL_WAVEFRONTS_sum SPI_RA_WAVE_SIMD_FULL_CSN SPI_RA_VGPR_SIMD_FULL_CSN CPC_CPC_UTCL2IU_STALL CPC_ME1_BUSY_FOR_PACKET_DECODE TCC_EA0_WRREQ_sum TCC_EA0_WRREQ_64B_sum TCC_EA0_WR_UNCACHED_32B_sum TCC_EA0_WRREQ_DRAM_sum
+
+gpu:
+range: invalid
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQ_ACTIVE_INST_SCA SQ_ACTIVE_INST_EXP_GDS SQ_ACTIVE_INST_MISC SQ_ACTIVE_INST_FLAT SQ_INST_CYCLES_VMEM_WR SQ_INST_CYCLES_VMEM_RD SQ_INST_CYCLES_SMEM SQ_INST_CYCLES_SALU TCP_TCC_READ_REQ_sum TCP_TCC_WRITE_REQ_sum TCP_TCC_ATOMIC_WITH_RET_REQ_sum TCP_TCC_ATOMIC_WITHOUT_RET_REQ_sum TA_ADDR_STALLED_BY_TD_CYCLES_sum TA_DATA_STALLED_BY_TC_CYCLES_sum SPI_RA_SGPR_SIMD_FULL_CSN SPI_RA_LDS_CU_FULL_CSN CPC_ME1_DC0_SPI_BUSY TCC_EA0_RDREQ_sum TCC_EA0_RDREQ_32B_sum TCC_BUBBLE_sum TCC_EA0_RD_UNCACHED_32B_sum
+
+gpu:
+range: invalid
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQ_THREAD_CYCLES_VALU SQ_IFETCH SQ_LDS_BANK_CONFLICT SQ_LDS_ADDR_CONFLICT SQ_LDS_UNALIGNED_STALL SQ_WAVES_EQ_64 SQ_WAVES_LT_64 SQ_WAVES_LT_48 TCP_TCC_NC_READ_REQ_sum TCP_TCC_NC_WRITE_REQ_sum TCP_TCC_NC_ATOMIC_REQ_sum TCP_TCC_UC_READ_REQ_sum TA_FLAT_WAVEFRONTS_sum TA_FLAT_READ_WAVEFRONTS_sum SPI_RA_BAR_CU_FULL_CSN SPI_RA_TGLIM_CU_FULL_CSN TCC_EA0_RDREQ_DRAM_sum TCC_TAG_STALL_sum TCC_NORMAL_WRITEBACK_sum TCC_ALL_TC_OP_WB_WRITEBACK_sum
+
+gpu:
+range: invalid
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQ_WAVES_LT_32 SQ_WAVES_LT_16 SQ_ITEMS SQ_LDS_MEM_VIOLATIONS SQ_LDS_ATOMIC_RETURN SQ_LDS_IDX_ACTIVE SQ_WAVES_RESTORED SQ_WAVES_SAVED TCP_TCC_UC_WRITE_REQ_sum TCP_TCC_UC_ATOMIC_REQ_sum TCP_TCC_CC_READ_REQ_sum TCP_TCC_CC_WRITE_REQ_sum TA_FLAT_WRITE_WAVEFRONTS_sum TA_FLAT_ATOMIC_WAVEFRONTS_sum SPI_RA_WVLIM_STALL_CSN SPI_SWC_CSC_WR TCC_NORMAL_EVICT_sum TCC_ALL_TC_OP_INV_EVICT_sum TCC_TOO_MANY_EA_WRREQS_STALL_sum TCC_EA0_ATOMIC_sum
+
+gpu:
+range: invalid
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQ_INSTS_SMEM_NORM SQ_INSTS_MFMA SQ_INSTS_VALU_MFMA_I8 SQ_INSTS_VALU_MFMA_F16 SQ_INSTS_VALU_MFMA_BF16 SQ_INSTS_VALU_MFMA_F32 SQ_INSTS_VALU_MFMA_F64 SQ_VALU_MFMA_BUSY_CYCLES TCP_TCC_CC_ATOMIC_REQ_sum TCP_TCC_RW_READ_REQ_sum TCP_TCC_RW_WRITE_REQ_sum TCP_TCC_RW_ATOMIC_REQ_sum SPI_VWC_CSC_WR SPI_RA_BULKY_CU_FULL_CSN TCC_EA0_RDREQ_LEVEL_sum TCC_EA0_WRREQ_LEVEL_sum TCC_EA0_ATOMIC_LEVEL_sum TCC_EA0_WRREQ_STALL_sum
+
+gpu:
+range: invalid
+kernel:
@@ -0,0 +1,5 @@
+pmc:  SQ_INSTS_VALU_MFMA_MOPS_I8 SQ_INSTS_VALU_MFMA_MOPS_F16 SQ_INSTS_VALU_MFMA_MOPS_BF16 SQ_INSTS_VALU_MFMA_MOPS_F32 SQ_INSTS_VALU_MFMA_MOPS_F64 SQC_TC_INST_REQ SQC_TC_DATA_READ_REQ SQC_TC_DATA_WRITE_REQ TCP_PENDING_STALL_CYCLES_sum
+
+gpu:
+range: invalid
+kernel:
@@ -0,0 +1,5 @@
+pmc:
+
+gpu:
+range: invalid
+kernel:
@@ -0,0 +1,4 @@
+Dispatch_ID,GPU_ID,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,Wave_Size,Kernel_Name,Correlation_ID,SQC_DCACHE_INPUT_VALID_READYB,SQC_DCACHE_ATOMIC,SQC_DCACHE_REQ_READ_8,SQC_DCACHE_REQ,SQC_DCACHE_HITS,SQC_DCACHE_MISSES,SQC_DCACHE_MISSES_DUPLICATE,SQC_DCACHE_REQ_READ_1,Wave_Size_1,Correlation_ID_1,XCC_Index,TCC_ATOMIC[0],TCC_BUBBLE[0],TCC_CYCLE[0],TCC_EA0_ATOMIC[0],TCC_ATOMIC[1],TCC_BUBBLE[1],TCC_CYCLE[1],TCC_EA0_ATOMIC[1],TCC_ATOMIC[2],TCC_BUBBLE[2],TCC_CYCLE[2],TCC_EA0_ATOMIC[2],TCC_ATOMIC[3],TCC_BUBBLE[3],TCC_CYCLE[3],TCC_EA0_ATOMIC[3],TCC_ATOMIC[4],TCC_BUBBLE[4],TCC_CYCLE[4],TCC_EA0_ATOMIC[4],TCC_ATOMIC[5],TCC_BUBBLE[5],TCC_CYCLE[5],TCC_EA0_ATOMIC[5],TCC_ATOMIC[6],TCC_BUBBLE[6],TCC_CYCLE[6],TCC_EA0_ATOMIC[6],TCC_ATOMIC[7],TCC_BUBBLE[7],TCC_CYCLE[7],TCC_EA0_ATOMIC[7],TCC_ATOMIC[8],TCC_BUBBLE[8],TCC_CYCLE[8],TCC_EA0_ATOMIC[8],TCC_ATOMIC[9],TCC_BUBBLE[9],TCC_CYCLE[9],TCC_EA0_ATOMIC[9],TCC_ATOMIC[10],TCC_BUBBLE[10],TCC_CYCLE[10],TCC_EA0_ATOMIC[10],TCC_ATOMIC[11],TCC_BUBBLE[11],TCC_CYCLE[11],TCC_EA0_ATOMIC[11],TCC_ATOMIC[12],TCC_BUBBLE[12],TCC_CYCLE[12],TCC_EA0_ATOMIC[12],TCC_ATOMIC[13],TCC_BUBBLE[13],TCC_CYCLE[13],TCC_EA0_ATOMIC[13],TCC_ATOMIC[14],TCC_BUBBLE[14],TCC_CYCLE[14],TCC_EA0_ATOMIC[14],TCC_ATOMIC[15],TCC_BUBBLE[15],TCC_CYCLE[15],TCC_EA0_ATOMIC[15],TCC_ATOMIC[16],TCC_BUBBLE[16],TCC_CYCLE[16],TCC_EA0_ATOMIC[16],TCC_ATOMIC[17],TCC_BUBBLE[17],TCC_CYCLE[17],TCC_EA0_ATOMIC[17],TCC_ATOMIC[18],TCC_BUBBLE[18],TCC_CYCLE[18],TCC_EA0_ATOMIC[18],TCC_ATOMIC[19],TCC_BUBBLE[19],TCC_CYCLE[19],TCC_EA0_ATOMIC[19],TCC_ATOMIC[20],TCC_BUBBLE[20],TCC_CYCLE[20],TCC_EA0_ATOMIC[20],TCC_ATOMIC[21],TCC_BUBBLE[21],TCC_CYCLE[21],TCC_EA0_ATOMIC[21],TCC_ATOMIC[22],TCC_BUBBLE[22],TCC_CYCLE[22],TCC_EA0_ATOMIC[22],TCC_ATOMIC[23],TCC_BUBBLE[23],TCC_CYCLE[23],TCC_EA0_ATOMIC[23],TCC_ATOMIC[24],TCC_BUBBLE[24],TCC_CYCLE[24],TCC_EA0_ATOMIC[24],TCC_ATOMIC[25],TCC_BUBBLE[25],TCC_CYCLE[25],TCC_EA0_ATOMIC[25],TCC_ATOMIC[26],TCC_BUBBLE[26],TCC_CYCLE[26],TCC_EA0_ATOMIC[26],TCC_ATOMIC[27],TCC_BUBBLE[27],TCC_CYCLE[27],TCC_EA0_ATOMIC[27],TCC_ATOMIC[28],TCC_BUBBLE[28],TCC_CYCLE[28],TCC_EA0_ATOMIC[28],TCC_ATOMIC[29],TCC_BUBBLE[29],TCC_CYCLE[29],TCC_EA0_ATOMIC[29],TCC_ATOMIC[30],TCC_BUBBLE[30],TCC_CYCLE[30],TCC_EA0_ATOMIC[30],TCC_ATOMIC[31],TCC_BUBBLE[31],TCC_CYCLE[31],TCC_EA0_ATOMIC[31],TCC_ATOMIC[32],TCC_BUBBLE[32],TCC_CYCLE[32],TCC_EA0_ATOMIC[32],TCC_ATOMIC[33],TCC_BUBBLE[33],TCC_CYCLE[33],TCC_EA0_ATOMIC[33],TCC_ATOMIC[34],TCC_BUBBLE[34],TCC_CYCLE[34],TCC_EA0_ATOMIC[34],TCC_ATOMIC[35],TCC_BUBBLE[35],TCC_CYCLE[35],TCC_EA0_ATOMIC[35],TCC_ATOMIC[36],TCC_BUBBLE[36],TCC_CYCLE[36],TCC_EA0_ATOMIC[36],TCC_ATOMIC[37],TCC_BUBBLE[37],TCC_CYCLE[37],TCC_EA0_ATOMIC[37],TCC_ATOMIC[38],TCC_BUBBLE[38],TCC_CYCLE[38],TCC_EA0_ATOMIC[38],TCC_ATOMIC[39],TCC_BUBBLE[39],TCC_CYCLE[39],TCC_EA0_ATOMIC[39],TCC_ATOMIC[40],TCC_BUBBLE[40],TCC_CYCLE[40],TCC_EA0_ATOMIC[40],TCC_ATOMIC[41],TCC_BUBBLE[41],TCC_CYCLE[41],TCC_EA0_ATOMIC[41],TCC_ATOMIC[42],TCC_BUBBLE[42],TCC_CYCLE[42],TCC_EA0_ATOMIC[42],TCC_ATOMIC[43],TCC_BUBBLE[43],TCC_CYCLE[43],TCC_EA0_ATOMIC[43],TCC_ATOMIC[44],TCC_BUBBLE[44],TCC_CYCLE[44],TCC_EA0_ATOMIC[44],TCC_ATOMIC[45],TCC_BUBBLE[45],TCC_CYCLE[45],TCC_EA0_ATOMIC[45],TCC_ATOMIC[46],TCC_BUBBLE[46],TCC_CYCLE[46],TCC_EA0_ATOMIC[46],TCC_ATOMIC[47],TCC_BUBBLE[47],TCC_CYCLE[47],TCC_EA0_ATOMIC[47],TCC_ATOMIC[48],TCC_BUBBLE[48],TCC_CYCLE[48],TCC_EA0_ATOMIC[48],TCC_ATOMIC[49],TCC_BUBBLE[49],TCC_CYCLE[49],TCC_EA0_ATOMIC[49],TCC_ATOMIC[50],TCC_BUBBLE[50],TCC_CYCLE[50],TCC_EA0_ATOMIC[50],TCC_ATOMIC[51],TCC_BUBBLE[51],TCC_CYCLE[51],TCC_EA0_ATOMIC[51],TCC_ATOMIC[52],TCC_BUBBLE[52],TCC_CYCLE[52],TCC_EA0_ATOMIC[52],TCC_ATOMIC[53],TCC_BUBBLE[53],TCC_CYCLE[53],TCC_EA0_ATOMIC[53],TCC_ATOMIC[54],TCC_BUBBLE[54],TCC_CYCLE[54],TCC_EA0_ATOMIC[54],TCC_ATOMIC[55],TCC_BUBBLE[55],TCC_CYCLE[55],TCC_EA0_ATOMIC[55],TCC_ATOMIC[56],TCC_BUBBLE[56],TCC_CYCLE[56],TCC_EA0_ATOMIC[56],TCC_ATOMIC[57],TCC_BUBBLE[57],TCC_CYCLE[57],TCC_EA0_ATOMIC[57],TCC_ATOMIC[58],TCC_BUBBLE[58],TCC_CYCLE[58],TCC_EA0_ATOMIC[58],TCC_ATOMIC[59],TCC_BUBBLE[59],TCC_CYCLE[59],TCC_EA0_ATOMIC[59],TCC_ATOMIC[60],TCC_BUBBLE[60],TCC_CYCLE[60],TCC_EA0_ATOMIC[60],TCC_ATOMIC[61],TCC_BUBBLE[61],TCC_CYCLE[61],TCC_EA0_ATOMIC[61],TCC_ATOMIC[62],TCC_BUBBLE[62],TCC_CYCLE[62],TCC_EA0_ATOMIC[62],TCC_ATOMIC[63],TCC_BUBBLE[63],TCC_CYCLE[63],TCC_EA0_ATOMIC[63],TCC_ATOMIC[64],TCC_BUBBLE[64],TCC_CYCLE[64],TCC_EA0_ATOMIC[64],TCC_ATOMIC[65],TCC_BUBBLE[65],TCC_CYCLE[65],TCC_EA0_ATOMIC[65],TCC_ATOMIC[66],TCC_BUBBLE[66],TCC_CYCLE[66],TCC_EA0_ATOMIC[66],TCC_ATOMIC[67],TCC_BUBBLE[67],TCC_CYCLE[67],TCC_EA0_ATOMIC[67],TCC_ATOMIC[68],TCC_BUBBLE[68],TCC_CYCLE[68],TCC_EA0_ATOMIC[68],TCC_ATOMIC[69],TCC_BUBBLE[69],TCC_CYCLE[69],TCC_EA0_ATOMIC[69],TCC_ATOMIC[70],TCC_BUBBLE[70],TCC_CYCLE[70],TCC_EA0_ATOMIC[70],TCC_ATOMIC[71],TCC_BUBBLE[71],TCC_CYCLE[71],TCC_EA0_ATOMIC[71],TCC_ATOMIC[72],TCC_BUBBLE[72],TCC_CYCLE[72],TCC_EA0_ATOMIC[72],TCC_ATOMIC[73],TCC_BUBBLE[73],TCC_CYCLE[73],TCC_EA0_ATOMIC[73],TCC_ATOMIC[74],TCC_BUBBLine truncated
+0,60633,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",0,2788816.0,0.0,0.0,65536.0,60576.0,160.0,4800.0,32768.0,64,0,0,0.0,512.0,47152.0,0.0,0.0,512.0,47152.0,0.0,0.0,512.0,47152.0,0.0,0.0,512.0,47152.0,0.0,0.0,512.0,47152.0,0.0,0.0,512.0,47152.0,0.0,0.0,512.0,47152.0,0.0,0.0,512.0,47152.0,0.0,0.0,512.0,47152.0,0.0,0.0,512.0,47152.0,0.0,0.0,512.0,47152.0,0.0,0.0,512.0,47152.0,0.0,0.0,512.0,47152.0,0.0,0.0,512.0,47152.0,0.0,0.0,512.0,47152.0,0.0,0.0,512.0,47152.0,0.0,0.0,512.0,44418.0,0.0,0.0,512.0,44418.0,0.0,0.0,512.0,44418.0,0.0,0.0,512.0,44418.0,0.0,0.0,512.0,44418.0,0.0,0.0,512.0,44418.0,0.0,0.0,512.0,44418.0,0.0,0.0,512.0,44418.0,0.0,0.0,512.0,44418.0,0.0,0.0,512.0,44418.0,0.0,0.0,512.0,44418.0,0.0,0.0,512.0,44418.0,0.0,0.0,512.0,44418.0,0.0,0.0,512.0,44418.0,0.0,0.0,512.0,44418.0,0.0,0.0,512.0,44418.0,0.0,0.0,512.0,60502.0,0.0,0.0,512.0,60502.0,0.0,0.0,512.0,60502.0,0.0,0.0,512.0,60502.0,0.0,0.0,512.0,60502.0,0.0,0.0,512.0,60502.0,0.0,0.0,512.0,60502.0,0.0,0.0,512.0,60502.0,0.0,0.0,512.0,60502.0,0.0,0.0,512.0,60502.0,0.0,0.0,512.0,60502.0,0.0,0.0,512.0,60502.0,0.0,0.0,512.0,60502.0,0.0,0.0,512.0,60502.0,0.0,0.0,512.0,60502.0,0.0,0.0,512.0,60502.0,0.0,0.0,512.0,66842.0,0.0,0.0,512.0,66842.0,0.0,0.0,512.0,66842.0,0.0,0.0,512.0,66842.0,0.0,0.0,512.0,66842.0,0.0,0.0,512.0,66842.0,0.0,0.0,512.0,66842.0,0.0,0.0,512.0,66842.0,0.0,0.0,512.0,66842.0,0.0,0.0,512.0,66842.0,0.0,0.0,512.0,66842.0,0.0,0.0,512.0,66842.0,0.0,0.0,512.0,66842.0,0.0,0.0,512.0,66842.0,0.0,0.0,512.0,66842.0,0.0,0.0,512.0,66842.0,0.0,0.0,512.0,84323.0,0.0,0.0,512.0,84323.0,0.0,0.0,512.0,84323.0,0.0,0.0,512.0,84323.0,0.0,0.0,512.0,84323.0,0.0,0.0,512.0,84323.0,0.0,0.0,512.0,84323.0,0.0,0.0,512.0,84323.0,0.0,0.0,512.0,84323.0,0.0,0.0,512.0,84323.0,0.0,0.0,512.0,84323.0,0.0,0.0,512.0,84323.0,0.0,0.0,512.0,84323.0,0.0,0.0,512.0,84323.0,0.0,0.0,512.0,84323.0,0.0,0.0,512.0,84323.0,0.0,0.0,512.0,91466.0,0.0,0.0,512.0,91466.0,0.0,0.0,512.0,91466.0,0.0,0.0,512.0,91466.0,0.0,0.0,512.0,91466.0,0.0,0.0,512.0,91466.0,0.0,0.0,512.0,91466.0,0.0,0.0,512.0,91466.0,0.0,0.0,512.0,91466.0,0.0,0.0,512.0,91466.0,0.0,0.0,512.0,91466.0,0.0,0.0,512.0,91466.0,0.0,0.0,512.0,91466.0,0.0,0.0,512.0,91466.0,0.0,0.0,512.0,91466.0,0.0,0.0,512.0,91466.0,0.0,0.0,512.0,97204.0,0.0,0.0,512.0,97204.0,0.0,0.0,512.0,97204.0,0.0,0.0,512.0,97204.0,0.0,0.0,512.0,97204.0,0.0,0.0,512.0,97204.0,0.0,0.0,512.0,97204.0,0.0,0.0,512.0,97204.0,0.0,0.0,512.0,97204.0,0.0,0.0,512.0,97204.0,0.0,0.0,512.0,97204.0,0.0,0.0,512.0,97204.0,0.0,0.0,512.0,97204.0,0.0,0.0,512.0,97204.0,0.0,0.0,512.0,97204.0,0.0,0.0,512.0,97204.0,0.0,0.0,512.0,105792.0,0.0,0.0,512.0,105792.0,0.0,0.0,512.0,105792.0,0.0,0.0,512.0,105792.0,0.0,0.0,512.0,105792.0,0.0,0.0,512.0,105792.0,0.0,0.0,512.0,105792.0,0.0,0.0,512.0,105792.0,0.0,0.0,512.0,105792.0,0.0,0.0,512.0,105792.0,0.0,0.0,512.0,105792.0,0.0,0.0,512.0,105792.0,0.0,0.0,512.0,105792.0,0.0,0.0,512.0,105792.0,0.0,0.0,512.0,105792.0,0.0,0.0,512.0,105792.0,0.0,64,0,0.0,0.0,1048576.0,0.0,0.0,0.0,0.0,0.0,0.0,32768.0,0.0,16384.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,64,0,131072.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,16384.0,0.0,0.0,85076047.0,56905344.0,178229.0,0.0,0.0,65536.0,131072.0,64,0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,59173.0,35946.0,2034380.0,696.0,0.0,341462.0,0.0,0.0,66160.0,131312.0,197472.0,0.0,2097152.0,1048576.0,1048576.0,2097152.0,0.0,16384.0,64,0,0,1024.0,512.0,1536.0,1536.0,1045.0,533.0,1557.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1025.0,513.0,1537.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1027.0,515.0,1539.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1027.0,593.0,1617.0,1616.0,1024.0,512.0,1536.0,1536.0,1026.0,514.0,1538.0,1536.0,1024.0,512.0,1536.0,1536.0,1027.0,515.0,1539.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1027.0,593.0,1617.0,1616.0,1024.0,512.0,1536.0,1536.0,1026.0,514.0,1538.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1045.0,533.0,1557.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1025.0,513.0,1537.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1045.0,533.0,1557.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1025.0,513.0,1537.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1026.0,514.0,1538.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1027.0,593.0,1617.0,1616.0,1024.0,512.0,1536.0,1536.0,1027.0,515.0,1539.0,1536.0,1024.0,512.0,1536.0,1536.0,1027.0,515.0,1539.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1027.0,593.0,1617.0,1616.0,1024.0,512.0,1536.0,1536.0,1028.0,516.0,1540.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1045.0,533.0,1557.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1024Line truncated
+1,60633,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",0,2717875.0,0.0,0.0,65536.0,60576.0,160.0,4800.0,32768.0,64,0,0,0.0,512.0,41267.0,0.0,0.0,512.0,41267.0,0.0,0.0,512.0,41267.0,0.0,0.0,512.0,41267.0,0.0,0.0,512.0,41267.0,0.0,0.0,512.0,41267.0,0.0,0.0,512.0,41267.0,0.0,0.0,512.0,41267.0,0.0,0.0,512.0,41267.0,0.0,0.0,512.0,41267.0,0.0,0.0,512.0,41267.0,0.0,0.0,512.0,41267.0,0.0,0.0,512.0,41267.0,0.0,0.0,512.0,41267.0,0.0,0.0,512.0,41267.0,0.0,0.0,512.0,41267.0,0.0,0.0,512.0,39310.0,0.0,0.0,512.0,39310.0,0.0,0.0,512.0,39310.0,0.0,0.0,512.0,39310.0,0.0,0.0,512.0,39310.0,0.0,0.0,512.0,39310.0,0.0,0.0,512.0,39310.0,0.0,0.0,512.0,39310.0,0.0,0.0,512.0,39310.0,0.0,0.0,512.0,39310.0,0.0,0.0,512.0,39310.0,0.0,0.0,512.0,39310.0,0.0,0.0,512.0,39310.0,0.0,0.0,512.0,39310.0,0.0,0.0,512.0,39310.0,0.0,0.0,512.0,39310.0,0.0,0.0,512.0,58306.0,0.0,0.0,512.0,58306.0,0.0,0.0,512.0,58306.0,0.0,0.0,512.0,58306.0,0.0,0.0,512.0,58306.0,0.0,0.0,512.0,58306.0,0.0,0.0,512.0,58306.0,0.0,0.0,512.0,58306.0,0.0,0.0,512.0,58306.0,0.0,0.0,512.0,58306.0,0.0,0.0,512.0,58306.0,0.0,0.0,512.0,58306.0,0.0,0.0,512.0,58306.0,0.0,0.0,512.0,58306.0,0.0,0.0,512.0,58306.0,0.0,0.0,512.0,58306.0,0.0,0.0,512.0,67668.0,0.0,0.0,512.0,67668.0,0.0,0.0,512.0,67668.0,0.0,0.0,512.0,67668.0,0.0,0.0,512.0,67668.0,0.0,0.0,512.0,67668.0,0.0,0.0,512.0,67668.0,0.0,0.0,512.0,67668.0,0.0,0.0,512.0,67668.0,0.0,0.0,512.0,67668.0,0.0,0.0,512.0,67668.0,0.0,0.0,512.0,67668.0,0.0,0.0,512.0,67668.0,0.0,0.0,512.0,67668.0,0.0,0.0,512.0,67668.0,0.0,0.0,512.0,67668.0,0.0,0.0,512.0,80565.0,0.0,0.0,512.0,80565.0,0.0,0.0,512.0,80565.0,0.0,0.0,512.0,80565.0,0.0,0.0,512.0,80565.0,0.0,0.0,512.0,80565.0,0.0,0.0,512.0,80565.0,0.0,0.0,512.0,80565.0,0.0,0.0,512.0,80565.0,0.0,0.0,512.0,80565.0,0.0,0.0,512.0,80565.0,0.0,0.0,512.0,80565.0,0.0,0.0,512.0,80565.0,0.0,0.0,512.0,80565.0,0.0,0.0,512.0,80565.0,0.0,0.0,512.0,80565.0,0.0,0.0,512.0,87811.0,0.0,0.0,512.0,87811.0,0.0,0.0,512.0,87811.0,0.0,0.0,512.0,87811.0,0.0,0.0,512.0,87811.0,0.0,0.0,512.0,87811.0,0.0,0.0,512.0,87811.0,0.0,0.0,512.0,87811.0,0.0,0.0,512.0,87811.0,0.0,0.0,512.0,87811.0,0.0,0.0,512.0,87811.0,0.0,0.0,512.0,87811.0,0.0,0.0,512.0,87811.0,0.0,0.0,512.0,87811.0,0.0,0.0,512.0,87811.0,0.0,0.0,512.0,87811.0,0.0,0.0,512.0,94017.0,0.0,0.0,512.0,94017.0,0.0,0.0,512.0,94017.0,0.0,0.0,512.0,94017.0,0.0,0.0,512.0,94017.0,0.0,0.0,512.0,94017.0,0.0,0.0,512.0,94017.0,0.0,0.0,512.0,94017.0,0.0,0.0,512.0,94017.0,0.0,0.0,512.0,94017.0,0.0,0.0,512.0,94017.0,0.0,0.0,512.0,94017.0,0.0,0.0,512.0,94017.0,0.0,0.0,512.0,94017.0,0.0,0.0,512.0,94017.0,0.0,0.0,512.0,94017.0,0.0,0.0,512.0,102435.0,0.0,0.0,512.0,102435.0,0.0,0.0,512.0,102435.0,0.0,0.0,512.0,102435.0,0.0,0.0,512.0,102435.0,0.0,0.0,512.0,102435.0,0.0,0.0,512.0,102435.0,0.0,0.0,512.0,102435.0,0.0,0.0,512.0,102435.0,0.0,0.0,512.0,102435.0,0.0,0.0,512.0,102435.0,0.0,0.0,512.0,102435.0,0.0,0.0,512.0,102435.0,0.0,0.0,512.0,102435.0,0.0,0.0,512.0,102435.0,0.0,0.0,512.0,102435.0,0.0,64,0,0.0,0.0,1048576.0,0.0,0.0,0.0,0.0,0.0,0.0,32768.0,0.0,16384.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,64,0,131072.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,16384.0,0.0,0.0,36999854.0,54472781.0,143534.0,0.0,0.0,65536.0,131072.0,64,0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,49153.0,32634.0,1994534.0,7058.0,0.0,247119.0,0.0,0.0,65536.0,131310.0,196846.0,0.0,2097152.0,1048576.0,1048576.0,2097152.0,0.0,16384.0,64,0,0,1024.0,512.0,1536.0,1536.0,1046.0,534.0,1558.0,1536.0,1025.0,513.0,1537.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1025.0,513.0,1537.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1027.0,515.0,1539.0,1536.0,1025.0,513.0,1537.0,1536.0,1025.0,513.0,1537.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1028.0,516.0,1540.0,1536.0,1024.0,512.0,1536.0,1536.0,1027.0,515.0,1539.0,1536.0,1025.0,513.0,1537.0,1536.0,1025.0,513.0,1537.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1028.0,516.0,1540.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1046.0,534.0,1558.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1025.0,513.0,1537.0,1536.0,1024.0,512.0,1536.0,1536.0,1025.0,513.0,1537.0,1536.0,1024.0,512.0,1536.0,1536.0,1046.0,534.0,1558.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1025.0,513.0,1537.0,1536.0,1024.0,512.0,1536.0,1536.0,1025.0,513.0,1537.0,1536.0,1026.0,514.0,1538.0,1536.0,1025.0,513.0,1537.0,1536.0,1025.0,513.0,1537.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1029.0,517.0,1541.0,1536.0,1024.0,512.0,1536.0,1536.0,1026.0,514.0,1538.0,1536.0,1025.0,513.0,1537.0,1536.0,1025.0,513.0,1537.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1027.0,515.0,1539.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1046.0,534.0,1558.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,102Line truncated
+2,60633,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",0,2778714.0,0.0,0.0,65536.0,60576.0,160.0,4800.0,32768.0,64,0,0,0.0,512.0,41501.0,0.0,0.0,512.0,41501.0,0.0,0.0,512.0,41501.0,0.0,0.0,512.0,41501.0,0.0,0.0,512.0,41501.0,0.0,0.0,512.0,41501.0,0.0,0.0,512.0,41501.0,0.0,0.0,512.0,41501.0,0.0,0.0,512.0,41501.0,0.0,0.0,512.0,41501.0,0.0,0.0,512.0,41501.0,0.0,0.0,512.0,41501.0,0.0,0.0,512.0,41501.0,0.0,0.0,512.0,41501.0,0.0,0.0,512.0,41501.0,0.0,0.0,512.0,41501.0,0.0,0.0,512.0,31392.0,0.0,0.0,512.0,31392.0,0.0,0.0,512.0,31392.0,0.0,0.0,512.0,31392.0,0.0,0.0,512.0,31392.0,0.0,0.0,512.0,31392.0,0.0,0.0,512.0,31392.0,0.0,0.0,512.0,31392.0,0.0,0.0,512.0,31392.0,0.0,0.0,512.0,31392.0,0.0,0.0,512.0,31392.0,0.0,0.0,512.0,31392.0,0.0,0.0,512.0,31392.0,0.0,0.0,512.0,31392.0,0.0,0.0,512.0,31392.0,0.0,0.0,512.0,31392.0,0.0,0.0,512.0,49245.0,0.0,0.0,512.0,49245.0,0.0,0.0,512.0,49245.0,0.0,0.0,512.0,49245.0,0.0,0.0,512.0,49245.0,0.0,0.0,512.0,49245.0,0.0,0.0,512.0,49245.0,0.0,0.0,512.0,49245.0,0.0,0.0,512.0,49245.0,0.0,0.0,512.0,49245.0,0.0,0.0,512.0,49245.0,0.0,0.0,512.0,49245.0,0.0,0.0,512.0,49245.0,0.0,0.0,512.0,49245.0,0.0,0.0,512.0,49245.0,0.0,0.0,512.0,49245.0,0.0,0.0,512.0,59302.0,0.0,0.0,512.0,59302.0,0.0,0.0,512.0,59302.0,0.0,0.0,512.0,59302.0,0.0,0.0,512.0,59302.0,0.0,0.0,512.0,59302.0,0.0,0.0,512.0,59302.0,0.0,0.0,512.0,59302.0,0.0,0.0,512.0,59302.0,0.0,0.0,512.0,59302.0,0.0,0.0,512.0,59302.0,0.0,0.0,512.0,59302.0,0.0,0.0,512.0,59302.0,0.0,0.0,512.0,59302.0,0.0,0.0,512.0,59302.0,0.0,0.0,512.0,59302.0,0.0,0.0,512.0,70114.0,0.0,0.0,512.0,70114.0,0.0,0.0,512.0,70114.0,0.0,0.0,512.0,70114.0,0.0,0.0,512.0,70114.0,0.0,0.0,512.0,70114.0,0.0,0.0,512.0,70114.0,0.0,0.0,512.0,70114.0,0.0,0.0,512.0,70114.0,0.0,0.0,512.0,70114.0,0.0,0.0,512.0,70114.0,0.0,0.0,512.0,70114.0,0.0,0.0,512.0,70114.0,0.0,0.0,512.0,70114.0,0.0,0.0,512.0,70114.0,0.0,0.0,512.0,70114.0,0.0,0.0,512.0,81366.0,0.0,0.0,512.0,81366.0,0.0,0.0,512.0,81366.0,0.0,0.0,512.0,81366.0,0.0,0.0,512.0,81366.0,0.0,0.0,512.0,81366.0,0.0,0.0,512.0,81366.0,0.0,0.0,512.0,81366.0,0.0,0.0,512.0,81366.0,0.0,0.0,512.0,81366.0,0.0,0.0,512.0,81366.0,0.0,0.0,512.0,81366.0,0.0,0.0,512.0,81366.0,0.0,0.0,512.0,81366.0,0.0,0.0,512.0,81366.0,0.0,0.0,512.0,81366.0,0.0,0.0,512.0,86554.0,0.0,0.0,512.0,86554.0,0.0,0.0,512.0,86554.0,0.0,0.0,512.0,86554.0,0.0,0.0,512.0,86554.0,0.0,0.0,512.0,86554.0,0.0,0.0,512.0,86554.0,0.0,0.0,512.0,86554.0,0.0,0.0,512.0,86554.0,0.0,0.0,512.0,86554.0,0.0,0.0,512.0,86554.0,0.0,0.0,512.0,86554.0,0.0,0.0,512.0,86554.0,0.0,0.0,512.0,86554.0,0.0,0.0,512.0,86554.0,0.0,0.0,512.0,86554.0,0.0,0.0,512.0,94906.0,0.0,0.0,512.0,94906.0,0.0,0.0,512.0,94906.0,0.0,0.0,512.0,94906.0,0.0,0.0,512.0,94906.0,0.0,0.0,512.0,94906.0,0.0,0.0,512.0,94906.0,0.0,0.0,512.0,94906.0,0.0,0.0,512.0,94906.0,0.0,0.0,512.0,94906.0,0.0,0.0,512.0,94906.0,0.0,0.0,512.0,94906.0,0.0,0.0,512.0,94906.0,0.0,0.0,512.0,94906.0,0.0,0.0,512.0,94906.0,0.0,0.0,512.0,94906.0,0.0,64,0,0.0,0.0,1048576.0,0.0,0.0,0.0,0.0,0.0,0.0,32768.0,0.0,16384.0,0.0,0.0,29.0,0.0,0.0,0.0,0.0,0.0,64,0,131072.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,16384.0,0.0,0.0,39638500.0,54197098.0,134372.0,0.0,0.0,65536.0,131072.0,64,0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,44053.0,31345.0,2013879.0,7232.0,0.0,282732.0,0.0,0.0,65536.0,131310.0,196846.0,0.0,2097152.0,1048576.0,1048576.0,2097152.0,0.0,16384.0,64,0,0,1024.0,512.0,1536.0,1536.0,1046.0,534.0,1558.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1025.0,513.0,1537.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1028.0,516.0,1540.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1025.0,513.0,1537.0,1536.0,1024.0,512.0,1536.0,1536.0,1026.0,514.0,1538.0,1536.0,1024.0,512.0,1536.0,1536.0,1027.0,515.0,1539.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1025.0,513.0,1537.0,1536.0,1024.0,512.0,1536.0,1536.0,1028.0,516.0,1540.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1046.0,534.0,1558.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1025.0,513.0,1537.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1046.0,534.0,1558.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1025.0,513.0,1537.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1027.0,515.0,1539.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1025.0,513.0,1537.0,1536.0,1024.0,512.0,1536.0,1536.0,1026.0,514.0,1538.0,1536.0,1024.0,512.0,1536.0,1536.0,1028.0,516.0,1540.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1025.0,513.0,1537.0,1536.0,1024.0,512.0,1536.0,1536.0,1028.0,516.0,1540.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1046.0,534.0,1558.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.0,1536.0,1024.0,512.0,1536.Line truncated
@@ -0,0 +1,2 @@
+workload_name,command,ip_blocks,timestamp,version,hostname,cpu_model,sbios,linux_distro,linux_kernel_version,amd_gpu_kernel_version,cpu_memory,gpu_memory,rocm_version,vbios,compute_partition,memory_partition,gpu_model,gpu_arch,gpu_l1,gpu_l2,cu_per_gpu,simd_per_cu,se_per_gpu,wave_size,workgroup_max_size,max_waves_per_cu,max_sclk,max_mclk,cur_sclk,cur_mclk,total_l2_chan,lds_banks_per_cu,sqc_per_gpu,pipes_per_gpu,hbm_bw,num_xcd
+dispatch_inv,./tests/vcopy -n 1048576 -b 256 -i 3,SQ|LDS|SQC|TA|TD|TCP|TCC|SPI|CPC|CPF,Wed 29 May 2024 11:57:01 AM  (CDT),2,splinter-126-wr-c6,AMD Ryzen 9 7950X 16-Core Processor,"American Megatrends International, LLC.VS2683299N.FD",Ubuntu 22.04.4 LTS,5.18.2-mi300-build-140423-ubuntu-22.04+,,114656528,,6.2.0-13611,113-MI3SRIOV-001,SPX,NPS1,MI300X_A1,gfx942,32,4096,304,4,32,64,1024,32,2100,1300,2100,1300,128,32,160,4,5324.8,8
@@ -0,0 +1,4 @@
+Dispatch_ID,GPU_ID,Queue_ID,PID,TID,Grid_Size,Workgroup_Size,LDS_Per_Workgroup,Scratch_Per_Workitem,Arch_VGPR,Accum_VGPR,SGPR,Wave_Size,Kernel_Name,Start_Timestamp,End_Timestamp,Correlation_ID
+1,60633,1,960575,960575,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",716011730095458,716011730117977,0
+2,60633,1,960575,960575,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",716011730139495,716011730153215,0
+3,60633,1,960575,960575,1048576,256,0,0,4,4,16,64,"vecCopy(double*, double*, double*, int, int) (.kd)",716011730173414,716011730187774,0