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GFX12: Update addrlib

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Updated address lib to mesa amd-temp-gfx12 branch.
Commit: 6e5244bd3184f0720197270a10e031b5ecd5fe75

Signed-off-by: David Belanger <david.belanger@amd.com>
Change-Id: Icaead4f38c5f3019c375116070b1f97a927f09b0
Signed-off-by: Chris Freehill <cfreehil@amd.com>
This commit is contained in:
David Belanger
2024-02-02 11:06:06 -05:00
committed by Chris Freehill
parent 7a3bf30769
commit bb02f4e9a7
41 changed files with 5329 additions and 1159 deletions
Download Patch File Download Diff File Expand all files Collapse all files
runtime/hsa-runtime/image/addrlib/src/amdgpu_asic_addr.h
+77 -90
View File
@@ -2,24 +2,7 @@
************************************************************************************************************************
*
* Copyright (C) 2017-2022 Advanced Micro Devices, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE
* SPDX-License-Identifier: MIT
*
***********************************************************************************************************************/
@@ -33,24 +16,23 @@
#define AMDGPU_VENDOR_IS_AMD(v) ((v == ATI_VENDOR_ID) || (v == AMD_VENDOR_ID))
#define FAMILY_UNKNOWN 0x00
#define FAMILY_TN 0x69
#define FAMILY_SI 0x6E
#define FAMILY_CI 0x78
#define FAMILY_KV 0x7D
#define FAMILY_VI 0x82
#define FAMILY_POLARIS 0x82
#define FAMILY_CZ 0x87
#define FAMILY_AI 0x8D
#define FAMILY_RV 0x8E
#define FAMILY_NV 0x8F
#define FAMILY_VGH 0x90
#define FAMILY_GFX1100 0x91
#define FAMILY_GFX1103 0x94
#define FAMILY_TN 0x69 //# 105 / Trinity APUs
#define FAMILY_SI 0x6E //# 110 / Southern Islands: Tahiti, Pitcairn, CapeVerde, Oland, Hainan
#define FAMILY_CI 0x78 //# 120 / Sea Islands: Bonaire, Hawaii
#define FAMILY_KV 0x7D //# 125 / Kaveri APUs: Spectre, Spooky, Kalindi, Godavari
#define FAMILY_VI 0x82 //# 130 / Volcanic Islands: Iceland, Tonga, Fiji
#define FAMILY_CZ 0x87 //# 135 / Carrizo APUs: Carrizo, Stoney
#define FAMILY_AI 0x8D //# 141 / Vega: 10, 20
#define FAMILY_RV 0x8E //# 142 / Raven
#define FAMILY_NV 0x8F //# 143 / Navi: 10
#define FAMILY_VGH 0x90 //# 144 / Van Gogh
#define FAMILY_NV3 0x91 //# 145 / Navi: 3x
#define FAMILY_GFX1150 0x96
#define FAMILY_RMB 0x92
#define FAMILY_GC_10_3_6 0x95
#define FAMILY_GC_10_3_7 0x97
#define FAMILY_GFX1103 0x94
#define FAMILY_RMB 0x92 //# 146 / Rembrandt
#define FAMILY_RPL 0x95 //# 149 / Raphael
#define FAMILY_MDN 0x97 //# 151 / Mendocino
#define FAMILY_GFX12 0x98
// AMDGPU_FAMILY_IS(familyId, familyName)
#define FAMILY_IS(f, fn) (f == FAMILY_##fn)
@@ -64,70 +46,72 @@
#define FAMILY_IS_AI(f) FAMILY_IS(f, AI)
#define FAMILY_IS_RV(f) FAMILY_IS(f, RV)
#define FAMILY_IS_NV(f) FAMILY_IS(f, NV)
#define FAMILY_IS_NV3(f) FAMILY_IS(f, NV3)
#define FAMILY_IS_RMB(f) FAMILY_IS(f, RMB)
#define FAMILY_IS_GFX1100(f) FAMILY_IS(f, GFX1100)
#define FAMILY_IS_GFX1103(f) FAMILY_IS(f, GFX1103)
#define FAMILY_IS_GFX1150(f) FAMILY_IS(f, GFX1150)
#define FAMILY_IS_GFX12(f) FAMILY_IS(f, GFX12)
#define AMDGPU_UNKNOWN 0xFF
#define AMDGPU_TAHITI_RANGE 0x05, 0x14
#define AMDGPU_PITCAIRN_RANGE 0x15, 0x28
#define AMDGPU_CAPEVERDE_RANGE 0x29, 0x3C
#define AMDGPU_OLAND_RANGE 0x3C, 0x46
#define AMDGPU_HAINAN_RANGE 0x46, 0xFF
#define AMDGPU_TAHITI_RANGE 0x05, 0x14 //# 5 <= x < 20
#define AMDGPU_PITCAIRN_RANGE 0x15, 0x28 //# 21 <= x < 40
#define AMDGPU_CAPEVERDE_RANGE 0x29, 0x3C //# 41 <= x < 60
#define AMDGPU_OLAND_RANGE 0x3C, 0x46 //# 60 <= x < 70
#define AMDGPU_HAINAN_RANGE 0x46, 0xFF //# 70 <= x < max
#define AMDGPU_BONAIRE_RANGE 0x14, 0x28
#define AMDGPU_HAWAII_RANGE 0x28, 0x3C
#define AMDGPU_BONAIRE_RANGE 0x14, 0x28 //# 20 <= x < 40
#define AMDGPU_HAWAII_RANGE 0x28, 0x3C //# 40 <= x < 60
#define AMDGPU_SPECTRE_RANGE 0x01, 0x41
#define AMDGPU_SPOOKY_RANGE 0x41, 0x81
#define AMDGPU_KALINDI_RANGE 0x81, 0xA1
#define AMDGPU_GODAVARI_RANGE 0xA1, 0xFF
#define AMDGPU_SPECTRE_RANGE 0x01, 0x41 //# 1 <= x < 65
#define AMDGPU_SPOOKY_RANGE 0x41, 0x81 //# 65 <= x < 129
#define AMDGPU_KALINDI_RANGE 0x81, 0xA1 //# 129 <= x < 161
#define AMDGPU_GODAVARI_RANGE 0xA1, 0xFF //# 161 <= x < max
#define AMDGPU_ICELAND_RANGE 0x01, 0x14
#define AMDGPU_TONGA_RANGE 0x14, 0x28
#define AMDGPU_FIJI_RANGE 0x3C, 0x50
#define AMDGPU_ICELAND_RANGE 0x01, 0x14 //# 1 <= x < 20
#define AMDGPU_TONGA_RANGE 0x14, 0x28 //# 20 <= x < 40
#define AMDGPU_FIJI_RANGE 0x3C, 0x50 //# 60 <= x < 80
#define AMDGPU_POLARIS10_RANGE 0x50, 0x5A
#define AMDGPU_POLARIS11_RANGE 0x5A, 0x64
#define AMDGPU_POLARIS12_RANGE 0x64, 0x6E
#define AMDGPU_VEGAM_RANGE 0x6E, 0xFF
#define AMDGPU_POLARIS10_RANGE 0x50, 0x5A //# 80 <= x < 90
#define AMDGPU_POLARIS11_RANGE 0x5A, 0x64 //# 90 <= x < 100
#define AMDGPU_POLARIS12_RANGE 0x64, 0x6E //# 100 <= x < 110
#define AMDGPU_VEGAM_RANGE 0x6E, 0xFF //# 110 <= x < max
#define AMDGPU_CARRIZO_RANGE 0x01, 0x21
#define AMDGPU_STONEY_RANGE 0x61, 0xFF
#define AMDGPU_CARRIZO_RANGE 0x01, 0x21 //# 1 <= x < 33
#define AMDGPU_BRISTOL_RANGE 0x10, 0x21 //# 16 <= x < 33
#define AMDGPU_STONEY_RANGE 0x61, 0xFF //# 97 <= x < max
#define AMDGPU_VEGA10_RANGE 0x01, 0x14
#define AMDGPU_VEGA12_RANGE 0x14, 0x28
#define AMDGPU_VEGA20_RANGE 0x28, 0x32
#define AMDGPU_ARCTURUS_RANGE 0x32, 0x3C
#define AMDGPU_ALDEBARAN_RANGE 0x3C, 0xFF
#define AMDGPU_VEGA10_RANGE 0x01, 0x14 //# 1 <= x < 20
#define AMDGPU_VEGA12_RANGE 0x14, 0x28 //# 20 <= x < 40
#define AMDGPU_VEGA20_RANGE 0x28, 0xFF //# 40 <= x < max
#define AMDGPU_RAVEN_RANGE 0x01, 0x81
#define AMDGPU_RAVEN2_RANGE 0x81, 0x91
#define AMDGPU_RENOIR_RANGE 0x91, 0xFF
#define AMDGPU_RAVEN_RANGE 0x01, 0x81 //# 1 <= x < 129
#define AMDGPU_RAVEN2_RANGE 0x81, 0x90 //# 129 <= x < 144
#define AMDGPU_RENOIR_RANGE 0x91, 0xFF //# 145 <= x < max
#define AMDGPU_NAVI10_RANGE 0x01, 0x0A
#define AMDGPU_NAVI12_RANGE 0x0A, 0x14
#define AMDGPU_NAVI14_RANGE 0x14, 0x28
#define AMDGPU_NAVI21_RANGE 0x28, 0x32
#define AMDGPU_NAVI22_RANGE 0x32, 0x3C
#define AMDGPU_NAVI23_RANGE 0x3C, 0x46
#define AMDGPU_NAVI24_RANGE 0x46, 0x50
#define AMDGPU_NAVI10_RANGE 0x01, 0x0A //# 1 <= x < 10
#define AMDGPU_NAVI12_RANGE 0x0A, 0x14 //# 10 <= x < 20
#define AMDGPU_NAVI14_RANGE 0x14, 0x28 //# 20 <= x < 40
#define AMDGPU_NAVI21_RANGE 0x28, 0x32 //# 40 <= x < 50
#define AMDGPU_NAVI22_RANGE 0x32, 0x3C //# 50 <= x < 60
#define AMDGPU_NAVI23_RANGE 0x3C, 0x46 //# 60 <= x < 70
#define AMDGPU_NAVI24_RANGE 0x46, 0x50 //# 70 <= x < 80
#define AMDGPU_VANGOGH_RANGE 0x01, 0xFF
#define AMDGPU_VANGOGH_RANGE 0x01, 0xFF //# 1 <= x < max
#define AMDGPU_GFX1100_RANGE 0x01, 0x10
#define AMDGPU_GFX1101_RANGE 0x20, 0xFF
#define AMDGPU_GFX1102_RANGE 0x10, 0x20
#define AMDGPU_GFX1103_RANGE 0x01, 0xFF
#define AMDGPU_GFX1150_RANGE 0x01, 0xFF
#define AMDGPU_NAVI31_RANGE 0x01, 0x10 //# 01 <= x < 16
#define AMDGPU_NAVI32_RANGE 0x20, 0xFF //# 32 <= x < 255
#define AMDGPU_NAVI33_RANGE 0x10, 0x20 //# 16 <= x < 32
#define AMDGPU_GFX1103_R1_RANGE 0x01, 0x80 //# 1 <= x < 128
#define AMDGPU_GFX1103_R2_RANGE 0x80, 0xC0 //# 128 <= x < 192
#define AMDGPU_REMBRANDT_RANGE 0x01, 0xFF
#define AMDGPU_GFX1150_RANGE 0x01, 0xFF //# 1 <= x < max
#define AMDGPU_GFX1036_RANGE 0x01, 0xFF
#define AMDGPU_REMBRANDT_RANGE 0x01, 0xFF //# 01 <= x < 255
#define AMDGPU_GFX1037_RANGE 0x01, 0xFF
#define AMDGPU_RAPHAEL_RANGE 0x01, 0xFF //# 1 <= x < max
#define AMDGPU_MENDOCINO_RANGE 0x01, 0xFF //# 1 <= x < max
#define AMDGPU_GFX12_TBD1_RANGE 0x40, 0xFF //# 64 <= x < max
#define AMDGPU_EXPAND_FIX(x) x
#define AMDGPU_RANGE_HELPER(val, min, max) ((val >= min) && (val < max))
@@ -160,6 +144,7 @@
#define ASICREV_IS_VEGAM_P(r) ASICREV_IS(r, VEGAM)
#define ASICREV_IS_CARRIZO(r) ASICREV_IS(r, CARRIZO)
#define ASICREV_IS_CARRIZO_BRISTOL(r) ASICREV_IS(r, BRISTOL)
#define ASICREV_IS_STONEY(r) ASICREV_IS(r, STONEY)
#define ASICREV_IS_VEGA10_M(r) ASICREV_IS(r, VEGA10)
@@ -167,8 +152,6 @@
#define ASICREV_IS_VEGA12_P(r) ASICREV_IS(r, VEGA12)
#define ASICREV_IS_VEGA12_p(r) ASICREV_IS(r, VEGA12)
#define ASICREV_IS_VEGA20_P(r) ASICREV_IS(r, VEGA20)
#define ASICREV_IS_ARCTURUS(r) ASICREV_IS(r, ARCTURUS)
#define ASICREV_IS_ALDEBARAN(r) ASICREV_IS(r, ALDEBARAN)
#define ASICREV_IS_RAVEN(r) ASICREV_IS(r, RAVEN)
#define ASICREV_IS_RAVEN2(r) ASICREV_IS(r, RAVEN2)
@@ -190,16 +173,20 @@
#define ASICREV_IS_VANGOGH(r) ASICREV_IS(r, VANGOGH)
#define ASICREV_IS_GFX1100(r) ASICREV_IS(r, GFX1100)
#define ASICREV_IS_GFX1101(r) ASICREV_IS(r, GFX1101)
#define ASICREV_IS_GFX1102(r) ASICREV_IS(r, GFX1102)
#define ASICREV_IS_GFX1103(r) ASICREV_IS(r, GFX1103)
#define ASICREV_IS_NAVI31_P(r) ASICREV_IS(r, NAVI31)
#define ASICREV_IS_NAVI32_P(r) ASICREV_IS(r, NAVI32)
#define ASICREV_IS_NAVI33_P(r) ASICREV_IS(r, NAVI33)
#define ASICREV_IS_GFX1150(r) ASICREV_IS(r, GFX1150)
#define ASICREV_IS_GFX1103_R1(r) ASICREV_IS(r, GFX1103_R1)
#define ASICREV_IS_GFX1103_R2(r) ASICREV_IS(r, GFX1103_R2)
#define ASICREV_IS_GFX1150(r) ASICREV_IS(r, GFX1150)
#define ASICREV_IS_REMBRANDT(r) ASICREV_IS(r, REMBRANDT)
#define ASICREV_IS_GFX1036(r) ASICREV_IS(r, GFX1036)
#define ASICREV_IS_RAPHAEL(r) ASICREV_IS(r, RAPHAEL)
#define ASICREV_IS_GFX1037(r) ASICREV_IS(r, GFX1037)
#define ASICREV_IS_MENDOCINO(r) ASICREV_IS(r, MENDOCINO)
#define ASICREV_IS_GFX12_TBD1_P(r) ASICREV_IS(r, GFX12_TBD1)
#endif // _AMDGPU_ASIC_ADDR_H