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Fix miscellaneous warnings flagged by Clang

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Change-Id: I85a45cb3b44e4379b31bcc56af061fd1571f2af5


[ROCm/ROCR-Runtime commit: c30c25bd30]
This commit is contained in:
Jay Cornwall
2016-10-26 19:24:48 -05:00
parent 1b76d435b4
commit c6bfeda697
11 ha cambiato i file con 127 aggiunte e 141 eliminazioni
Scarica il file Patch Scarica il file Diff Expand all files Collapse all files
projects/rocr-runtime/runtime/hsa-runtime/core/inc/amd_aql_queue.h
+57 -64
Vedi File
@@ -70,43 +70,43 @@ class AqlQueue : public core::Queue, public core::Signal {
bool IsValid() const { return valid_; }
/// @brief Queue interfaces
hsa_status_t Inactivate();
hsa_status_t Inactivate() override;
/// @brief Atomically reads the Read index of with Acquire semantics
///
/// @return uint64_t Value of read index
uint64_t LoadReadIndexAcquire();
uint64_t LoadReadIndexAcquire() override;
/// @brief Atomically reads the Read index of with Relaxed semantics
///
/// @return uint64_t Value of read index
uint64_t LoadReadIndexRelaxed();
uint64_t LoadReadIndexRelaxed() override;
/// @brief Atomically reads the Write index of with Acquire semantics
///
/// @return uint64_t Value of write index
uint64_t LoadWriteIndexAcquire();
uint64_t LoadWriteIndexAcquire() override;
/// @brief Atomically reads the Write index of with Relaxed semantics
///
/// @return uint64_t Value of write index
uint64_t LoadWriteIndexRelaxed();
uint64_t LoadWriteIndexRelaxed() override;
/// @brief This operation is illegal
void StoreReadIndexRelaxed(uint64_t value) { assert(false); }
void StoreReadIndexRelaxed(uint64_t value) override { assert(false); }
/// @brief This operation is illegal
void StoreReadIndexRelease(uint64_t value) { assert(false); }
void StoreReadIndexRelease(uint64_t value) override { assert(false); }
/// @brief Atomically writes the Write index of with Relaxed semantics
///
/// @param value New value of write index to update with
void StoreWriteIndexRelaxed(uint64_t value);
void StoreWriteIndexRelaxed(uint64_t value) override;
/// @brief Atomically writes the Write index of with Release semantics
///
/// @param value New value of write index to update with
void StoreWriteIndexRelease(uint64_t value);
void StoreWriteIndexRelease(uint64_t value) override;
/// @brief Compares and swaps Write index using Acquire and Release semantics
///
@@ -115,7 +115,7 @@ class AqlQueue : public core::Queue, public core::Signal {
/// @param value Value of new write index
///
/// @return uint64_t Value of write index before the update
uint64_t CasWriteIndexAcqRel(uint64_t expected, uint64_t value);
uint64_t CasWriteIndexAcqRel(uint64_t expected, uint64_t value) override;
/// @brief Compares and swaps Write index using Acquire semantics
///
@@ -124,7 +124,7 @@ class AqlQueue : public core::Queue, public core::Signal {
/// @param value Value of new write index
///
/// @return uint64_t Value of write index before the update
uint64_t CasWriteIndexAcquire(uint64_t expected, uint64_t value);
uint64_t CasWriteIndexAcquire(uint64_t expected, uint64_t value) override;
/// @brief Compares and swaps Write index using Relaxed semantics
///
@@ -133,7 +133,7 @@ class AqlQueue : public core::Queue, public core::Signal {
/// @param value Value of new write index
///
/// @return uint64_t Value of write index before the update
uint64_t CasWriteIndexRelaxed(uint64_t expected, uint64_t value);
uint64_t CasWriteIndexRelaxed(uint64_t expected, uint64_t value) override;
/// @brief Compares and swaps Write index using Release semantics
///
@@ -142,35 +142,35 @@ class AqlQueue : public core::Queue, public core::Signal {
/// @param value Value of new write index
///
/// @return uint64_t Value of write index before the update
uint64_t CasWriteIndexRelease(uint64_t expected, uint64_t value);
uint64_t CasWriteIndexRelease(uint64_t expected, uint64_t value) override;
/// @brief Updates the Write index using Acquire and Release semantics
///
/// @param value Value of new write index
///
/// @return uint64_t Value of write index before the update
uint64_t AddWriteIndexAcqRel(uint64_t value);
uint64_t AddWriteIndexAcqRel(uint64_t value) override;
/// @brief Updates the Write index using Acquire semantics
///
/// @param value Value of new write index
///
/// @return uint64_t Value of write index before the update
uint64_t AddWriteIndexAcquire(uint64_t value);
uint64_t AddWriteIndexAcquire(uint64_t value) override;
/// @brief Updates the Write index using Relaxed semantics
///
/// @param value Value of new write index
///
/// @return uint64_t Value of write index before the update
uint64_t AddWriteIndexRelaxed(uint64_t value);
uint64_t AddWriteIndexRelaxed(uint64_t value) override;
/// @brief Updates the Write index using Release semantics
///
/// @param value Value of new write index
///
/// @return uint64_t Value of write index before the update
uint64_t AddWriteIndexRelease(uint64_t value);
uint64_t AddWriteIndexRelease(uint64_t value) override;
/// @brief Set CU Masking
///
@@ -179,166 +179,159 @@ class AqlQueue : public core::Queue, public core::Signal {
/// @param cu_mask pointer to cu mask
///
/// @return hsa_status_t
hsa_status_t SetCUMasking(const uint32_t num_cu_mask_count,
const uint32_t* cu_mask);
hsa_status_t SetCUMasking(const uint32_t num_cu_mask_count, const uint32_t* cu_mask) override;
// @brief Submits a block of PM4 and waits until it has been executed.
void ExecutePM4(uint32_t* cmd_data, size_t cmd_size_b) override;
/// @brief This operation is illegal
hsa_signal_value_t LoadRelaxed() {
hsa_signal_value_t LoadRelaxed() override {
assert(false);
return 0;
}
/// @brief This operation is illegal
hsa_signal_value_t LoadAcquire() {
hsa_signal_value_t LoadAcquire() override {
assert(false);
return 0;
}
/// @brief Update signal value using Relaxed semantics
void StoreRelaxed(hsa_signal_value_t value);
void StoreRelaxed(hsa_signal_value_t value) override;
/// @brief Update signal value using Release semantics
void StoreRelease(hsa_signal_value_t value);
void StoreRelease(hsa_signal_value_t value) override;
/// @brief This operation is illegal
hsa_signal_value_t WaitRelaxed(hsa_signal_condition_t condition,
hsa_signal_value_t compare_value,
uint64_t timeout, hsa_wait_state_t wait_hint) {
hsa_signal_value_t WaitRelaxed(hsa_signal_condition_t condition, hsa_signal_value_t compare_value,
uint64_t timeout, hsa_wait_state_t wait_hint) override {
assert(false);
return 0;
}
/// @brief This operation is illegal
hsa_signal_value_t WaitAcquire(hsa_signal_condition_t condition,
hsa_signal_value_t compare_value,
uint64_t timeout, hsa_wait_state_t wait_hint) {
hsa_signal_value_t WaitAcquire(hsa_signal_condition_t condition, hsa_signal_value_t compare_value,
uint64_t timeout, hsa_wait_state_t wait_hint) override {
assert(false);
return 0;
}
/// @brief This operation is illegal
void AndRelaxed(hsa_signal_value_t value) { assert(false); }
void AndRelaxed(hsa_signal_value_t value) override { assert(false); }
/// @brief This operation is illegal
void AndAcquire(hsa_signal_value_t value) { assert(false); }
void AndAcquire(hsa_signal_value_t value) override { assert(false); }
/// @brief This operation is illegal
void AndRelease(hsa_signal_value_t value) { assert(false); }
void AndRelease(hsa_signal_value_t value) override { assert(false); }
/// @brief This operation is illegal
void AndAcqRel(hsa_signal_value_t value) { assert(false); }
void AndAcqRel(hsa_signal_value_t value) override { assert(false); }
/// @brief This operation is illegal
void OrRelaxed(hsa_signal_value_t value) { assert(false); }
void OrRelaxed(hsa_signal_value_t value) override { assert(false); }
/// @brief This operation is illegal
void OrAcquire(hsa_signal_value_t value) { assert(false); }
void OrAcquire(hsa_signal_value_t value) override { assert(false); }
/// @brief This operation is illegal
void OrRelease(hsa_signal_value_t value) { assert(false); }
void OrRelease(hsa_signal_value_t value) override { assert(false); }
/// @brief This operation is illegal
void OrAcqRel(hsa_signal_value_t value) { assert(false); }
void OrAcqRel(hsa_signal_value_t value) override { assert(false); }
/// @brief This operation is illegal
void XorRelaxed(hsa_signal_value_t value) { assert(false); }
void XorRelaxed(hsa_signal_value_t value) override { assert(false); }
/// @brief This operation is illegal
void XorAcquire(hsa_signal_value_t value) { assert(false); }
void XorAcquire(hsa_signal_value_t value) override { assert(false); }
/// @brief This operation is illegal
void XorRelease(hsa_signal_value_t value) { assert(false); }
void XorRelease(hsa_signal_value_t value) override { assert(false); }
/// @brief This operation is illegal
void XorAcqRel(hsa_signal_value_t value) { assert(false); }
void XorAcqRel(hsa_signal_value_t value) override { assert(false); }
/// @brief This operation is illegal
void AddRelaxed(hsa_signal_value_t value) { assert(false); }
void AddRelaxed(hsa_signal_value_t value) override { assert(false); }
/// @brief This operation is illegal
void AddAcquire(hsa_signal_value_t value) { assert(false); }
void AddAcquire(hsa_signal_value_t value) override { assert(false); }
/// @brief This operation is illegal
void AddRelease(hsa_signal_value_t value) { assert(false); }
void AddRelease(hsa_signal_value_t value) override { assert(false); }
/// @brief This operation is illegal
void AddAcqRel(hsa_signal_value_t value) { assert(false); }
void AddAcqRel(hsa_signal_value_t value) override { assert(false); }
/// @brief This operation is illegal
void SubRelaxed(hsa_signal_value_t value) { assert(false); }
void SubRelaxed(hsa_signal_value_t value) override { assert(false); }
/// @brief This operation is illegal
void SubAcquire(hsa_signal_value_t value) { assert(false); }
void SubAcquire(hsa_signal_value_t value) override { assert(false); }
/// @brief This operation is illegal
void SubRelease(hsa_signal_value_t value) { assert(false); }
void SubRelease(hsa_signal_value_t value) override { assert(false); }
/// @brief This operation is illegal
void SubAcqRel(hsa_signal_value_t value) { assert(false); }
void SubAcqRel(hsa_signal_value_t value) override { assert(false); }
/// @brief This operation is illegal
hsa_signal_value_t ExchRelaxed(hsa_signal_value_t value) {
hsa_signal_value_t ExchRelaxed(hsa_signal_value_t value) override {
assert(false);
return 0;
}
/// @brief This operation is illegal
hsa_signal_value_t ExchAcquire(hsa_signal_value_t value) {
hsa_signal_value_t ExchAcquire(hsa_signal_value_t value) override {
assert(false);
return 0;
}
/// @brief This operation is illegal
hsa_signal_value_t ExchRelease(hsa_signal_value_t value) {
hsa_signal_value_t ExchRelease(hsa_signal_value_t value) override {
assert(false);
return 0;
}
/// @brief This operation is illegal
hsa_signal_value_t ExchAcqRel(hsa_signal_value_t value) {
hsa_signal_value_t ExchAcqRel(hsa_signal_value_t value) override {
assert(false);
return 0;
}
/// @brief This operation is illegal
hsa_signal_value_t CasRelaxed(hsa_signal_value_t expected,
hsa_signal_value_t value) {
hsa_signal_value_t CasRelaxed(hsa_signal_value_t expected, hsa_signal_value_t value) override {
assert(false);
return 0;
}
/// @brief This operation is illegal
hsa_signal_value_t CasAcquire(hsa_signal_value_t expected,
hsa_signal_value_t value) {
hsa_signal_value_t CasAcquire(hsa_signal_value_t expected, hsa_signal_value_t value) override {
assert(false);
return 0;
}
/// @brief This operation is illegal
hsa_signal_value_t CasRelease(hsa_signal_value_t expected,
hsa_signal_value_t value) {
hsa_signal_value_t CasRelease(hsa_signal_value_t expected, hsa_signal_value_t value) override {
assert(false);
return 0;
}
/// @brief This operation is illegal
hsa_signal_value_t CasAcqRel(hsa_signal_value_t expected,
hsa_signal_value_t value) {
hsa_signal_value_t CasAcqRel(hsa_signal_value_t expected, hsa_signal_value_t value) override {
assert(false);
return 0;
}
/// @brief This operation is illegal
hsa_signal_value_t* ValueLocation() const {
hsa_signal_value_t* ValueLocation() const override {
assert(false);
return NULL;
}
/// @brief This operation is illegal
HsaEvent* EopEvent() {
HsaEvent* EopEvent() override {
assert(false);
return NULL;
}
@@ -350,7 +343,7 @@ class AqlQueue : public core::Queue, public core::Signal {
void operator delete(void*, void*) {}
protected:
bool _IsA(rtti_t id) const { return id == &rtti_id_; }
bool _IsA(rtti_t id) const override { return id == &rtti_id_; }
private:
uint32_t ComputeRingBufferMinPkts();
projects/rocr-runtime/runtime/hsa-runtime/core/inc/amd_loader_context.hpp
+9 -13
Vedi File
@@ -69,23 +69,19 @@ public:
bool SegmentFreeze(amdgpu_hsa_elf_segment_t segment, hsa_agent_t agent, void* seg, size_t size) override;
bool ImageExtensionSupported();
bool ImageExtensionSupported() override;
hsa_status_t ImageCreate(
hsa_agent_t agent,
hsa_access_permission_t image_permission,
const hsa_ext_image_descriptor_t *image_descriptor,
const void *image_data,
hsa_ext_image_t *image_handle);
hsa_status_t ImageCreate(hsa_agent_t agent, hsa_access_permission_t image_permission,
const hsa_ext_image_descriptor_t* image_descriptor,
const void* image_data, hsa_ext_image_t* image_handle) override;
hsa_status_t ImageDestroy(hsa_agent_t agent, hsa_ext_image_t image_handle);
hsa_status_t ImageDestroy(hsa_agent_t agent, hsa_ext_image_t image_handle) override;
hsa_status_t SamplerCreate(
hsa_agent_t agent,
const hsa_ext_sampler_descriptor_t *sampler_descriptor,
hsa_ext_sampler_t *sampler_handle);
hsa_status_t SamplerCreate(hsa_agent_t agent,
const hsa_ext_sampler_descriptor_t* sampler_descriptor,
hsa_ext_sampler_t* sampler_handle) override;
hsa_status_t SamplerDestroy(hsa_agent_t agent, hsa_ext_sampler_t sampler_handle);
hsa_status_t SamplerDestroy(hsa_agent_t agent, hsa_ext_sampler_t sampler_handle) override;
private:
LoaderContext(const LoaderContext&);
projects/rocr-runtime/runtime/hsa-runtime/core/inc/host_queue.h
+18 -19
Vedi File
@@ -56,90 +56,89 @@ class HostQueue : public Queue {
~HostQueue();
hsa_status_t Inactivate() { return HSA_STATUS_SUCCESS; }
hsa_status_t Inactivate() override { return HSA_STATUS_SUCCESS; }
uint64_t LoadReadIndexAcquire() {
uint64_t LoadReadIndexAcquire() override {
return atomic::Load(&amd_queue_.read_dispatch_id,
std::memory_order_acquire);
}
uint64_t LoadReadIndexRelaxed() {
uint64_t LoadReadIndexRelaxed() override {
return atomic::Load(&amd_queue_.read_dispatch_id,
std::memory_order_relaxed);
}
uint64_t LoadWriteIndexAcquire() {
uint64_t LoadWriteIndexAcquire() override {
return atomic::Load(&amd_queue_.write_dispatch_id,
std::memory_order_acquire);
}
uint64_t LoadWriteIndexRelaxed() {
uint64_t LoadWriteIndexRelaxed() override {
return atomic::Load(&amd_queue_.write_dispatch_id,
std::memory_order_relaxed);
}
void StoreReadIndexRelaxed(uint64_t value) {
void StoreReadIndexRelaxed(uint64_t value) override {
atomic::Store(&amd_queue_.read_dispatch_id, value,
std::memory_order_relaxed);
}
void StoreReadIndexRelease(uint64_t value) {
void StoreReadIndexRelease(uint64_t value) override {
atomic::Store(&amd_queue_.read_dispatch_id, value,
std::memory_order_release);
}
void StoreWriteIndexRelaxed(uint64_t value) {
void StoreWriteIndexRelaxed(uint64_t value) override {
atomic::Store(&amd_queue_.write_dispatch_id, value,
std::memory_order_relaxed);
}
void StoreWriteIndexRelease(uint64_t value) {
void StoreWriteIndexRelease(uint64_t value) override {
atomic::Store(&amd_queue_.write_dispatch_id, value,
std::memory_order_release);
}
uint64_t CasWriteIndexAcqRel(uint64_t expected, uint64_t value) {
uint64_t CasWriteIndexAcqRel(uint64_t expected, uint64_t value) override {
return atomic::Cas(&amd_queue_.write_dispatch_id, value, expected,
std::memory_order_acq_rel);
}
uint64_t CasWriteIndexAcquire(uint64_t expected, uint64_t value) {
uint64_t CasWriteIndexAcquire(uint64_t expected, uint64_t value) override {
return atomic::Cas(&amd_queue_.write_dispatch_id, value, expected,
std::memory_order_acquire);
}
uint64_t CasWriteIndexRelaxed(uint64_t expected, uint64_t value) {
uint64_t CasWriteIndexRelaxed(uint64_t expected, uint64_t value) override {
return atomic::Cas(&amd_queue_.write_dispatch_id, value, expected,
std::memory_order_relaxed);
}
uint64_t CasWriteIndexRelease(uint64_t expected, uint64_t value) {
uint64_t CasWriteIndexRelease(uint64_t expected, uint64_t value) override {
return atomic::Cas(&amd_queue_.write_dispatch_id, value, expected,
std::memory_order_release);
}
uint64_t AddWriteIndexAcqRel(uint64_t value) {
uint64_t AddWriteIndexAcqRel(uint64_t value) override {
return atomic::Add(&amd_queue_.write_dispatch_id, value,
std::memory_order_acq_rel);
}
uint64_t AddWriteIndexAcquire(uint64_t value) {
uint64_t AddWriteIndexAcquire(uint64_t value) override {
return atomic::Add(&amd_queue_.write_dispatch_id, value,
std::memory_order_acquire);
}
uint64_t AddWriteIndexRelaxed(uint64_t value) {
uint64_t AddWriteIndexRelaxed(uint64_t value) override {
return atomic::Add(&amd_queue_.write_dispatch_id, value,
std::memory_order_relaxed);
}
uint64_t AddWriteIndexRelease(uint64_t value) {
uint64_t AddWriteIndexRelease(uint64_t value) override {
return atomic::Add(&amd_queue_.write_dispatch_id, value,
std::memory_order_release);
}
hsa_status_t SetCUMasking(const uint32_t num_cu_mask_count,
const uint32_t* cu_mask) {
hsa_status_t SetCUMasking(const uint32_t num_cu_mask_count, const uint32_t* cu_mask) override {
return HSA_STATUS_ERROR;
}
projects/rocr-runtime/runtime/hsa-runtime/core/runtime/amd_aql_queue.cpp
+5 -7
Vedi File
@@ -217,12 +217,10 @@ AqlQueue::AqlQueue(GpuAgent* agent, size_t req_size_pkts, HSAuint32 node_id,
}
}
assert(amd_queue_.group_segment_aperture_base_hi != NULL &&
"No group region found.");
assert(amd_queue_.group_segment_aperture_base_hi != 0 && "No group region found.");
if (core::Runtime::runtime_singleton_->flag().check_flat_scratch()) {
assert(amd_queue_.private_segment_aperture_base_hi != NULL &&
"No private region found.");
assert(amd_queue_.private_segment_aperture_base_hi != 0 && "No private region found.");
}
MAKE_NAMED_SCOPE_GUARD(EventGuard, [&]() {
@@ -783,8 +781,8 @@ void AqlQueue::ExecutePM4(uint32_t* cmd_data, size_t cmd_size_b) {
uint32_t slot_idx = uint32_t(write_idx % public_handle()->size);
constexpr uint32_t slot_size_b = 0x40;
uint32_t* queue_slot = (uint32_t*)uintptr_t(public_handle()->base_address +
(slot_idx * slot_size_b));
uint32_t* queue_slot =
(uint32_t*)(uintptr_t(public_handle()->base_address) + (slot_idx * slot_size_b));
// Copy client PM4 command into IB.
assert(cmd_size_b < pm4_ib_size_b_ && "PM4 exceeds IB size");
@@ -913,7 +911,7 @@ void AqlQueue::InitScratchSRD() {
uint32_t(queue_scratch_.size_per_thread);
// Set concurrent wavefront limits only when scratch is being used.
COMPUTE_TMPRING_SIZE tmpring_size = {0};
COMPUTE_TMPRING_SIZE tmpring_size = {};
if (queue_scratch_.size == 0) {
amd_queue_.compute_tmpring_size = tmpring_size.u32All;
return;
projects/rocr-runtime/runtime/hsa-runtime/core/runtime/hsa.cpp
+4 -3
Vedi File
@@ -299,9 +299,10 @@ static size_t get_extension_table_length(uint16_t extension, uint16_t major, uin
std::string name;
size_t size;
};
static sizes_t sizes[] = {"hsa_ext_images_1_00_pfn_t", sizeof(hsa_ext_images_1_00_pfn_t),
"hsa_ext_finalizer_1_00_pfn_t", sizeof(hsa_ext_finalizer_1_00_pfn_t),
"hsa_ven_amd_loader_1_00_pfn_t", sizeof(hsa_ven_amd_loader_1_00_pfn_t)};
static sizes_t sizes[] = {
{"hsa_ext_images_1_00_pfn_t", sizeof(hsa_ext_images_1_00_pfn_t)},
{"hsa_ext_finalizer_1_00_pfn_t", sizeof(hsa_ext_finalizer_1_00_pfn_t)},
{"hsa_ven_amd_loader_1_00_pfn_t", sizeof(hsa_ven_amd_loader_1_00_pfn_t)}};
static const size_t num_tables = sizeof(sizes) / sizeof(sizes_t);
if (minor > 99) return 0;
projects/rocr-runtime/runtime/hsa-runtime/core/runtime/runtime.cpp
+1 -1
Vedi File
@@ -65,7 +65,7 @@
#define HSA_VERSION_MAJOR 1
#define HSA_VERSION_MINOR 1
const char rocrbuildid[] = "ROCR BUILD ID: " STRING(ROCR_BUILD_ID);
const char rocrbuildid[] __attribute__((unused)) = "ROCR BUILD ID: " STRING(ROCR_BUILD_ID);
namespace core {
bool g_use_interrupt_wait = true;
projects/rocr-runtime/runtime/hsa-runtime/core/util/utils.h
-1
Vedi File
@@ -64,7 +64,6 @@ typedef uint64_t uint64;
#endif
#define __forceinline __inline__ __attribute__((always_inline))
static __forceinline void __debugbreak() { __builtin_trap(); }
#define __declspec(x) __attribute__((x))
#undef __stdcall
#define __stdcall // __attribute__((__stdcall__))
projects/rocr-runtime/runtime/hsa-runtime/libamdhsacode/amd_elf_image.cpp
+14 -14
Vedi File
@@ -423,9 +423,9 @@ namespace amd {
RelocationSection* relocationSection(SymbolTable* symtab = 0) override;
Segment* segment() override { return seg; }
RelocationSection* asRelocationSection() override { return 0; }
bool setMemSize(uint64_t s) { memsize_ = s; return true; }
bool setMemSize(uint64_t s) override { memsize_ = s; return true; }
uint64_t memSize() const override { return memsize_ ? memsize_ : size(); }
bool setAlign(uint64_t a) { align_ = a; return true; }
bool setAlign(uint64_t a) override { align_ = a; return true; }
uint64_t memAlign() const override { return align_ ? align_ : addralign(); }
protected:
@@ -474,7 +474,7 @@ namespace amd {
bool push(const char* name, uint32_t shtype, uint64_t shflags);
bool pullData() override;
const char* addString(const std::string& s) override;
size_t addString1(const std::string& s);
size_t addString1(const std::string& s) override;
const char* getString(size_t ndx) override;
size_t getStringIndex(const char* name) override;
@@ -510,12 +510,12 @@ namespace amd {
uint32_t index() override { return eindex / sizeof(GElf_Rela); }
uint32_t type() override { return GELF_ST_TYPE(Sym()->st_info); }
uint32_t binding() { return GELF_ST_BIND(Sym()->st_info); }
uint64_t size() { return Sym()->st_size; }
uint64_t value() { return Sym()->st_value; }
unsigned char other() { return Sym()->st_other; }
uint32_t binding() override { return GELF_ST_BIND(Sym()->st_info); }
uint64_t size() override { return Sym()->st_size; }
uint64_t value() override { return Sym()->st_value; }
unsigned char other() override { return Sym()->st_other; }
std::string name() override;
Section* section();
Section* section() override;
void setValue(uint64_t value) override { Sym()->st_value = value; }
void setSize(uint64_t size) override { Sym()->st_size = size; }
@@ -665,8 +665,8 @@ namespace amd {
bool initNew(uint16_t machine, uint16_t type, uint8_t os_abi = 0, uint8_t abi_version = 0, uint32_t e_flags = 0) override;
bool loadFromFile(const std::string& filename) override;
bool saveToFile(const std::string& filename) override;
bool initFromBuffer(const void* buffer, size_t size);
bool initAsBuffer(const void* buffer, size_t size);
bool initFromBuffer(const void* buffer, size_t size) override;
bool initAsBuffer(const void* buffer, size_t size) override;
bool close();
bool writeTo(const std::string& filename) override;
bool copyToBuffer(void** buf, size_t* size = 0) override;
@@ -683,9 +683,9 @@ namespace amd {
uint16_t Machine() override { return ehdr.e_machine; }
uint16_t Type() override { return ehdr.e_type; }
GElfStringTable* shstrtab();
GElfStringTable* strtab();
GElfSymbolTable* getSymtab(uint16_t index)
GElfStringTable* shstrtab() override;
GElfStringTable* strtab() override;
GElfSymbolTable* getSymtab(uint16_t index) override
{
return static_cast<GElfSymbolTable*>(section(index));
}
@@ -694,7 +694,7 @@ namespace amd {
GElfStringTable* getStringTable(uint16_t index) override;
GElfSymbolTable* addSymbolTable(const std::string& name, StringTable* stab = 0) override;
GElfSymbolTable* symtab();
GElfSymbolTable* symtab() override;
GElfSegment* segment(size_t i) override { return segments[i].get(); }
Segment* segmentByVAddr(uint64_t vaddr) override;
projects/rocr-runtime/runtime/hsa-runtime/libamdhsacode/amd_options.hpp
+3 -3
Vedi File
@@ -283,7 +283,7 @@ private:
/// @brief Not copy-assignable.
ValueOption& operator=(const ValueOption &o);
bool ProcessTokens(std::list<std::string> &tokens);
bool ProcessTokens(std::list<std::string> &tokens) override;
T value_;
};
@@ -340,7 +340,7 @@ private:
/// @brief Not copy-assignable.
ChoiceOption& operator =(const ChoiceOption&);
bool ProcessTokens(std::list<std::string> &tokens);
bool ProcessTokens(std::list<std::string> &tokens) override;
std::unordered_set<std::string> choices_;
std::string value_;
@@ -370,7 +370,7 @@ private:
/// @brief Not copy-assignable.
NoArgOption& operator=(const NoArgOption &o);
bool ProcessTokens(std::list<std::string> &tokens) {
bool ProcessTokens(std::list<std::string> &tokens) override {
assert(0 == name_.compare(tokens.front()) && "option name is mismatched");
if (1 == tokens.size()) {
tokens.pop_front();
projects/rocr-runtime/runtime/hsa-runtime/loader/executable.hpp
+11 -11
Vedi File
@@ -112,7 +112,7 @@ protected:
, is_definition(_is_definition)
, address(_address) {}
virtual bool GetInfo(hsa_symbol_info32_t symbol_info, void *value);
virtual bool GetInfo(hsa_symbol_info32_t symbol_info, void *value) override;
private:
SymbolImpl(const SymbolImpl &s);
@@ -361,23 +361,23 @@ public:
~ExecutableImpl();
hsa_status_t GetInfo(hsa_executable_info_t executable_info, void *value);
hsa_status_t GetInfo(hsa_executable_info_t executable_info, void *value) override;
hsa_status_t DefineProgramExternalVariable(
const char *name, void *address);
const char *name, void *address) override;
hsa_status_t DefineAgentExternalVariable(
const char *name,
hsa_agent_t agent,
hsa_variable_segment_t segment,
void *address);
void *address) override;
hsa_status_t LoadCodeObject(
hsa_agent_t agent,
hsa_code_object_t code_object,
const char *options,
hsa_loaded_code_object_t *loaded_code_object,
bool load_legacy = true);
bool load_legacy = true) override;
hsa_status_t LoadCodeObject(
hsa_agent_t agent,
@@ -385,11 +385,11 @@ public:
size_t code_object_size,
const char *options,
hsa_loaded_code_object_t *loaded_code_object,
bool load_legacy = true);
bool load_legacy = true) override;
hsa_status_t Freeze(const char *options);
hsa_status_t Freeze(const char *options) override;
hsa_status_t Validate(uint32_t *result) {
hsa_status_t Validate(uint32_t *result) override {
amd::hsa::common::ReaderLockGuard<amd::hsa::common::ReaderWriterLock> reader_lock(rw_lock_);
assert(result);
*result = 0;
@@ -405,7 +405,7 @@ public:
const hsa_agent_t *agent) override;
hsa_status_t IterateSymbols(
iterate_symbols_f callback, void *data);
iterate_symbols_f callback, void *data) override;
/// @since hsa v1.1.
hsa_status_t IterateAgentSymbols(
@@ -427,7 +427,7 @@ public:
hsa_status_t (*callback)(
hsa_loaded_code_object_t loaded_code_object,
void *data),
void *data);
void *data) override;
size_t GetNumSegmentDescriptors() override;
@@ -501,7 +501,7 @@ public:
AmdHsaCodeLoader(Context* context_)
: context(context_) { assert(context); }
Context* GetContext() const { return context; }
Context* GetContext() const override { return context; }
Executable* CreateExecutable(
hsa_profile_t profile,
projects/rocr-runtime/runtime/hsa-runtime/loader/loaders.hpp
+5 -5
Vedi File
@@ -83,25 +83,25 @@ namespace loader {
bool SegmentFreeze(amdgpu_hsa_elf_segment_t segment, hsa_agent_t agent, void* seg, size_t size) override;
bool ImageExtensionSupported();
bool ImageExtensionSupported() override;
hsa_status_t ImageCreate(
hsa_agent_t agent,
hsa_access_permission_t image_permission,
const hsa_ext_image_descriptor_t *image_descriptor,
const void *image_data,
hsa_ext_image_t *image_handle);
hsa_ext_image_t *image_handle) override;
hsa_status_t ImageDestroy(
hsa_agent_t agent, hsa_ext_image_t image_handle);
hsa_agent_t agent, hsa_ext_image_t image_handle) override;
hsa_status_t SamplerCreate(
hsa_agent_t agent,
const hsa_ext_sampler_descriptor_t *sampler_descriptor,
hsa_ext_sampler_t *sampler_handle);
hsa_ext_sampler_t *sampler_handle) override;
hsa_status_t SamplerDestroy(
hsa_agent_t agent, hsa_ext_sampler_t sampler_handle);
hsa_agent_t agent, hsa_ext_sampler_t sampler_handle) override;
};
}
}