SWDEV-461717 - Increase CB alignment and size

- Gfx12 TCC cacheline size is 256B, Increase to have alignment
compatible. Eventually this needs to be replaced with what the query
returns.

Change-Id: I545929446c4faa3f26872a6290b3a89657888596


[ROCm/clr commit: bb01b4c3b4]

projects/clr/rocclr/device/rocm/rocblit.hpp

@@ -576,8 +576,8 @@ class KernelBlitManager : public DmaBlitManager {
                           const device::Memory* dev_mem = nullptr,
                           bool writeVAImmediate = false) const;
 
-  static constexpr uint32_t kCBSize = 0x80;
-  static constexpr size_t   kCBAlignment = 0x80;
+  static constexpr uint32_t kCBSize = 0x100;
+  static constexpr size_t   kCBAlignment = 0x100;
 
   inline uint32_t NumBlitKernels() {
     return (dev().info().imageSupport_) ? BlitTotal : BlitLinearTotal;