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wsl/hsakmt: clean up namespace

Bläddra i källkod 
Signed-off-by: Longlong Yao <Longlong.Yao@amd.com>
Reviewed-by: lyndonli <Lyndon.Li@amd.com>
Reviewed-by: Flora Cui <flora.cui@amd.com>
Part-of: <http://10.67.69.192/wsl/libhsakmt/-/merge_requests/7>
This commit is contained in:
Longlong Yao
2024-09-10 08:16:11 -07:00
committad av Frank Min
förälder 79a63cf292
incheckning ccb3950068
31 ändrade filer med 139 tillägg och 139 borttagningar
Download Patch File Download Diff File Expand all files Collapse all files
inc/wddm/cmd_util.h
+4 -4
Visa fil
@@ -10,8 +10,8 @@
#include "inc/pm4_cmds.h"
#include "util/utils.h"
namespace rocr {
namespace core {
namespace wsl {
namespace thunk {
struct DispatchInfo {
uint8_t major;
@@ -71,7 +71,7 @@ public:
uint64_t srcData = 1);
};
} // namespace core
} // namespace rocr
} // namespace thunk
} // namespace wsl
#endif
inc/wddm/device.h
+4 -4
Visa fil
@@ -58,8 +58,8 @@
#include "inc/wddm/gpu_memory.h"
#include "inc/wddm/cmd_util.h"
namespace rocr {
namespace core {
namespace wsl {
namespace thunk {
//class Queue;
class WDDMQueue;
@@ -239,7 +239,7 @@ private:
NTSTATUS WDDMGetAdapters(D3DKMT_ADAPTERINFO *&adapters, int &num_adapters);
} // namespace core
} // namespace rocr
} // namespace thunk
} // namespace wsl
#endif
inc/wddm/gpu_memory.h
+4 -4
Visa fil
@@ -50,8 +50,8 @@
#include "inc/wddm/thunks.h"
#include "inc/rocr_proxy/rocr_proxy.h"
namespace rocr {
namespace core {
namespace wsl {
namespace thunk {
class WDDMDevice;
@@ -212,7 +212,7 @@ private:
DISALLOW_COPY_AND_ASSIGN(GpuMemory);
};
} // namespace core
} // namespace rocr
} // namespace thunk
} // namespace wsl
#endif
inc/wddm/queue.h
+4 -4
Visa fil
@@ -52,8 +52,8 @@
#include "hsa-runtime/inc/amd_hsa_signal.h"
#include "inc/wddm/cmd_util.h"
namespace rocr {
namespace core {
namespace wsl {
namespace thunk {
class Queue;
class WDDMDevice;
@@ -278,7 +278,7 @@ private:
uint64_t ib_start_addr;
};
}
}
} // namespace thunk
} // namespace wsl
#endif
inc/wddm/thunks.h
+5 -5
Visa fil
@@ -46,8 +46,8 @@
#include "inc/wddm/status.h"
#include "inc/wddm/types.h"
namespace rocr {
namespace core {
namespace wsl {
namespace thunk {
inline ErrorCode TranslateNtStatus(NTSTATUS status) {
switch (status) {
@@ -71,7 +71,7 @@ inline ErrorCode TranslateNtStatus(NTSTATUS status) {
return ErrorCode::Unknown;
}
namespace thunk {
namespace d3dthunk {
typedef D3DKMT_CREATEALLOCATION CreateAllocationArgs;
typedef D3DKMT_CREATECONTEXT CreateContextArgs;
@@ -225,8 +225,8 @@ inline ErrorCode OpenResourceFromNtHandle(D3DKMT_OPENRESOURCEFROMNTHANDLE *args)
return TranslateNtStatus(D3DKMTOpenResourceFromNtHandle(args));
}
} // namespace d3dthunk
} // namespace thunk
} // namespace core
} // namespace rocr
} // namespace wsl
#endif // _ROCR_CORE_INC_WDDM_THUNKS_H_
inc/wddm/va_mgr.h
+4 -4
Visa fil
@@ -5,8 +5,8 @@
#include <map>
#include "util/utils.h"
namespace rocr {
namespace core {
namespace wsl {
namespace thunk {
class VaMgr {
public:
@@ -81,6 +81,6 @@ private:
DISALLOW_COPY_AND_ASSIGN(VaMgr);
};
} // namespace core
} // namespace rocr
} // namespace thunk
} // namespace wsl
#endif // VA_MGR_H_
libdrm.cpp
+3 -3
Visa fil
@@ -51,7 +51,7 @@ HSAKMT_STATUS HSAKMTAPI hsaKmtGetAMDGPUDeviceHandle(
HSAuint32 NodeId, HsaAMDGPUDeviceHandle *DeviceHandle) {
CHECK_DXG_OPEN();
rocr::core::WDDMDevice *pDevice = get_wddmdev(NodeId);
wsl::thunk::WDDMDevice *pDevice = get_wddmdev(NodeId);
if (pDevice != nullptr) {
*DeviceHandle = reinterpret_cast<HsaAMDGPUDeviceHandle>(pDevice);
return HSAKMT_STATUS_SUCCESS;
@@ -61,8 +61,8 @@ HSAKMT_STATUS HSAKMTAPI hsaKmtGetAMDGPUDeviceHandle(
HSAKMTAPI int hsaKmtamdgpu_query_gpu_info(void *dev,
struct amdgpu_gpu_info *info) {
rocr::core::WDDMDevice *pDevice =
reinterpret_cast<rocr::core::WDDMDevice *>(dev);
wsl::thunk::WDDMDevice *pDevice =
reinterpret_cast<wsl::thunk::WDDMDevice *>(dev);
memset(info, 0, sizeof(*info));
info->gpu_counter_freq = pDevice->GPUCounterFrequency() / 1000ull;
return 0;
libhsakmt.h
+1 -1
Visa fil
@@ -34,7 +34,7 @@
#include "inc/wddm/types.h"
#include "inc/wddm/device.h"
rocr::core::WDDMDevice* get_wddmdev(uint32_t node_id);
wsl::thunk::WDDMDevice* get_wddmdev(uint32_t node_id);
extern unsigned long dxg_open_count;
extern bool hsakmt_forked;
memory.cpp
+17 -17
Visa fil
@@ -38,7 +38,7 @@ struct Allocation {
Allocation()
: handle(0), cpu_addr(0), gpu_addr(0), size(0), userptr(false),
user_data(nullptr), size_requested(0), node_id(0), mem_flags_value(0) {}
Allocation(rocr::core::GpuMemoryHandle handle_arg, void *cpu_addr_arg,
Allocation(wsl::thunk::GpuMemoryHandle handle_arg, void *cpu_addr_arg,
uint64_t gpu_addr_arg, size_t size_arg, bool userptr_arg = false,
void *user_data_arg = nullptr, size_t user_size_arg = 0,
HSAuint32 node_id_arg = 0, HSAuint32 mem_flags_value_arg = 0)
@@ -47,7 +47,7 @@ struct Allocation {
size_requested(user_size_arg), node_id(node_id_arg),
mem_flags_value(mem_flags_value_arg) {}
rocr::core::GpuMemoryHandle handle;
wsl::thunk::GpuMemoryHandle handle;
void *cpu_addr;
uint64_t gpu_addr;
bool userptr;
@@ -105,7 +105,7 @@ bool isSystemMemoryAvailable(HSAuint64 SizeInBytes) {
return SizeInBytes <= info.freeram;
}
bool isLocalMemoryAvailable(rocr::core::WDDMDevice *dev,
bool isLocalMemoryAvailable(wsl::thunk::WDDMDevice *dev,
HSAuint64 SizeInBytes) {
return SizeInBytes <= dev->VramAvail();
}
@@ -126,12 +126,12 @@ HSAKMT_STATUS HSAKMTAPI hsaKmtAllocMemoryAlign(HSAuint32 PreferredNode,
} else
*MemoryAddress = nullptr;
rocr::core::WDDMDevice *dev = get_wddmdev(1);
wsl::thunk::WDDMDevice *dev = get_wddmdev(1);
if (!dev)
return HSAKMT_STATUS_ERROR;
rocr::core::GpuMemory *gpu_mem = nullptr;
rocr::core::GpuMemoryCreateInfo create_info{};
wsl::thunk::GpuMemory *gpu_mem = nullptr;
wsl::thunk::GpuMemoryCreateInfo create_info{};
create_info.size = SizeInBytes;
if (!MemFlags.ui32.NonPaged || zfb_support || MemFlags.ui32.GTTAccess) {
@@ -177,7 +177,7 @@ HSAKMT_STATUS HSAKMTAPI hsaKmtFreeMemory(void *MemoryAddress,
if (!MemoryAddress)
return HSAKMT_STATUS_INVALID_PARAMETER;
rocr::core::GpuMemory *gpu_mem = nullptr;
wsl::thunk::GpuMemory *gpu_mem = nullptr;
{
std::lock_guard<std::mutex> gard(allocation_map_lock_);
auto it = allocation_map_.find(MemoryAddress);
@@ -185,7 +185,7 @@ HSAKMT_STATUS HSAKMTAPI hsaKmtFreeMemory(void *MemoryAddress,
return HSAKMT_STATUS_ERROR;
}
gpu_mem = rocr::core::GpuMemory::Convert(it->second.handle);
gpu_mem = wsl::thunk::GpuMemory::Convert(it->second.handle);
allocation_map_.erase(it);
}
@@ -201,7 +201,7 @@ HSAKMT_STATUS HSAKMTAPI hsaKmtAvailableMemory(HSAuint32 Node,
if (!AvailableBytes)
return HSAKMT_STATUS_INVALID_PARAMETER;
rocr::core::WDDMDevice *dev = get_wddmdev(Node);
wsl::thunk::WDDMDevice *dev = get_wddmdev(Node);
if (!dev)
return HSAKMT_STATUS_ERROR;
@@ -342,9 +342,9 @@ HSAKMT_STATUS HSAKMTAPI hsaKmtMapMemoryToGPU(void *MemoryAddress,
return HSAKMT_STATUS_ERROR;
}
uint64_t start = rocr::AlignDown((uint64_t)MemoryAddress, 4096);
uint64_t start = wsl::AlignDown((uint64_t)MemoryAddress, 4096);
uint64_t end =
rocr::AlignUp((uint64_t)MemoryAddress + MemorySizeInBytes, 4096);
wsl::AlignUp((uint64_t)MemoryAddress + MemorySizeInBytes, 4096);
void *aligned_ptr = (void *)start;
size_t aligned_size = end - start;
@@ -376,14 +376,14 @@ HSAKMT_STATUS HSAKMTAPI hsaKmtMapMemoryToGPU(void *MemoryAddress,
}
}
rocr::core::WDDMDevice *dev = get_wddmdev(1);
wsl::thunk::WDDMDevice *dev = get_wddmdev(1);
if (!dev)
return HSAKMT_STATUS_ERROR;
rocr::core::GpuMemory *gpu_mem = nullptr;
rocr::core::GpuMemoryHandle handle = 0;
wsl::thunk::GpuMemory *gpu_mem = nullptr;
wsl::thunk::GpuMemoryHandle handle = 0;
uint64_t addr;
rocr::core::GpuMemoryCreateInfo create_info{};
wsl::thunk::GpuMemoryCreateInfo create_info{};
create_info.domain = rocr_proxy::kUserMemory;
create_info.size = aligned_size;
create_info.user_ptr = aligned_ptr;
@@ -428,7 +428,7 @@ HSAKMT_STATUS HSAKMTAPI hsaKmtUnmapMemoryToGPU(void *MemoryAddress) {
pr_debug("[%s] address %p\n", __func__, MemoryAddress);
rocr::core::GpuMemoryHandle handle = nullptr;
wsl::thunk::GpuMemoryHandle handle = nullptr;
{
std::lock_guard<std::mutex> gard(allocation_map_lock_);
auto it = allocation_map_.find(MemoryAddress);
@@ -445,7 +445,7 @@ HSAKMT_STATUS HSAKMTAPI hsaKmtUnmapMemoryToGPU(void *MemoryAddress) {
allocation_map_.erase((void *)it->second.gpu_addr);
allocation_map_.erase(it);
}
auto gpu_mem = rocr::core::GpuMemory::Convert(handle);
auto gpu_mem = wsl::thunk::GpuMemory::Convert(handle);
delete gpu_mem;
return HSAKMT_STATUS_SUCCESS;
queues.cpp
+7 -7
Visa fil
@@ -51,7 +51,7 @@ HSAKMT_STATUS HSAKMTAPI hsaKmtCreateQueue(
Priority > HSA_QUEUE_PRIORITY_MAXIMUM)
return HSAKMT_STATUS_INVALID_PARAMETER;
rocr::core::WDDMDevice *device_ = get_wddmdev(NodeId);
wsl::thunk::WDDMDevice *device_ = get_wddmdev(NodeId);
assert(device_);
switch (Type) {
@@ -61,7 +61,7 @@ HSAKMT_STATUS HSAKMTAPI hsaKmtCreateQueue(
uint32_t cmdbuf_size = device_->GetCmdbufSize();
uint32_t queue_engine = device_->GetComputeEngine();
bool use_hws = device_->IsHwsEnabled(queue_engine);
auto queue_ = new rocr::core::ComputeQueue(
auto queue_ = new wsl::thunk::ComputeQueue(
device_, QueueAddress, pkg_num,
reinterpret_cast<std::atomic<uint64_t> *>(QueueResource->Queue_write_ptr_aql),
reinterpret_cast<std::atomic<uint64_t> *>(QueueResource->Queue_read_ptr_aql),
@@ -91,7 +91,7 @@ HSAKMT_STATUS HSAKMTAPI hsaKmtUpdateQueue(
Priority > HSA_QUEUE_PRIORITY_MAXIMUM)
return HSAKMT_STATUS_INVALID_PARAMETER;
auto queue_ = reinterpret_cast<rocr::core::ComputeQueue *>(QueueId);
auto queue_ = reinterpret_cast<wsl::thunk::ComputeQueue *>(QueueId);
if (!queue_)
return HSAKMT_STATUS_INVALID_PARAMETER;
@@ -101,7 +101,7 @@ HSAKMT_STATUS HSAKMTAPI hsaKmtUpdateQueue(
HSAKMT_STATUS HSAKMTAPI hsaKmtDestroyQueue(HSA_QUEUEID QueueId) {
CHECK_DXG_OPEN();
auto queue_ = reinterpret_cast<rocr::core::ComputeQueue *>(QueueId);
auto queue_ = reinterpret_cast<wsl::thunk::ComputeQueue *>(QueueId);
if (!queue_)
return HSAKMT_STATUS_INVALID_PARAMETER;
@@ -115,7 +115,7 @@ HSAKMT_STATUS HSAKMTAPI hsaKmtSetQueueCUMask(HSA_QUEUEID QueueId,
HSAuint32 *QueueCUMask) {
CHECK_DXG_OPEN();
auto queue_ = reinterpret_cast<rocr::core::ComputeQueue *>(QueueId);
auto queue_ = reinterpret_cast<wsl::thunk::ComputeQueue *>(QueueId);
if (!queue_)
return HSAKMT_STATUS_INVALID_PARAMETER;
@@ -154,7 +154,7 @@ HSAKMT_STATUS HSAKMTAPI hsaKmtAllocQueueGWS(HSA_QUEUEID QueueId, HSAuint32 nGWS,
HSAuint32 *firstGWS) {
CHECK_DXG_OPEN();
auto queue_ = reinterpret_cast<rocr::core::ComputeQueue *>(QueueId);
auto queue_ = reinterpret_cast<wsl::thunk::ComputeQueue *>(QueueId);
if (!queue_)
return HSAKMT_STATUS_INVALID_PARAMETER;
@@ -165,7 +165,7 @@ HSAKMT_STATUS HSAKMTAPI hsaKmtAllocQueueGWS(HSA_QUEUEID QueueId, HSAuint32 nGWS,
HSAKMT_STATUS HSAKMTAPI hsaKmtQueueRingDoorbell(HSA_QUEUEID QueueId) {
CHECK_DXG_OPEN();
auto queue_ = reinterpret_cast<rocr::core::ComputeQueue *>(QueueId);
auto queue_ = reinterpret_cast<wsl::thunk::ComputeQueue *>(QueueId);
if (!queue_)
return HSAKMT_STATUS_INVALID_PARAMETER;
time.cpp
+1 -1
Visa fil
@@ -37,7 +37,7 @@ HSAKMT_STATUS HSAKMTAPI hsaKmtGetClockCounters(HSAuint32 NodeId,
std::memset(Counters, 0, sizeof(*Counters));
rocr::core::WDDMDevice *device_ = get_wddmdev(NodeId);
wsl::thunk::WDDMDevice *device_ = get_wddmdev(NodeId);
assert(device_);
device_->GetClockCounters(&Counters->GPUClockCounter, nullptr);
topology.cpp
+11 -11
Visa fil
@@ -64,7 +64,7 @@ typedef struct {
static HsaSystemProperties *g_system;
static node_props_t *g_props;
static std::vector<rocr::core::WDDMDevice *> wdevices_;
static std::vector<wsl::thunk::WDDMDevice *> wdevices_;
static uint32_t wdevice_num_;
static uint32_t num_sysfs_nodes;
@@ -355,7 +355,7 @@ static int get_cpu_cache_info(const char *prefix, struct proc_cpuinfo *cpuinfo,
}
static HSAKMT_STATUS topology_map_node_id(uint32_t node_id,
rocr::core::WDDMDevice *&device) {
wsl::thunk::WDDMDevice *&device) {
uint32_t idx = node_id;
if ((!wdevices_.size()) || (!node_id) || (node_id >= num_sysfs_nodes))
return HSAKMT_STATUS_NOT_SUPPORTED;
@@ -374,7 +374,7 @@ HSAKMT_STATUS topology_sysfs_get_system_props(HsaSystemProperties *props) {
D3DKMT_ADAPTERINFO *adapters;
int num_adapters;
if (rocr::core::WDDMGetAdapters(adapters, num_adapters) != STATUS_SUCCESS) {
if (wsl::thunk::WDDMGetAdapters(adapters, num_adapters) != STATUS_SUCCESS) {
pr_err("Failed to get adapters\n");
ret = HSAKMT_STATUS_ERROR;
goto err;
@@ -387,7 +387,7 @@ HSAKMT_STATUS topology_sysfs_get_system_props(HsaSystemProperties *props) {
wdevices_.clear();
for (uint32_t i = 0; i < num_adapters; i++) {
rocr::core::WDDMDevice *device = new rocr::core::WDDMDevice(
wsl::thunk::WDDMDevice *device = new wsl::thunk::WDDMDevice(
adapters[i].hAdapter, adapters[i].AdapterLuid);
assert(device && "Create WDDM Device fail");
wdevices_.push_back(device);
@@ -644,7 +644,7 @@ static HSAKMT_STATUS topology_sysfs_get_node_props(uint32_t node_id,
}
/* gpu node */
rocr::core::WDDMDevice *device;
wsl::thunk::WDDMDevice *device;
ret = topology_map_node_id(node_id, device);
if (ret != HSAKMT_STATUS_SUCCESS)
return ret;
@@ -756,7 +756,7 @@ static HSAKMT_STATUS topology_sysfs_get_mem_props(uint32_t node_id,
return HSAKMT_STATUS_SUCCESS;
}
rocr::core::WDDMDevice *device;
wsl::thunk::WDDMDevice *device;
ret = topology_map_node_id(node_id, device);
if (ret != HSAKMT_STATUS_SUCCESS)
return ret;
@@ -955,7 +955,7 @@ static HSAKMT_STATUS topology_sysfs_get_iolink_props(uint32_t node_id,
uint32_t iolink_id,
HsaIoLinkProperties *props,
bool p2pLink) {
rocr::core::WDDMDevice *device;
wsl::thunk::WDDMDevice *device;
topology_map_node_id(node_id, device);
std::memset(props, 0, sizeof(*props));
@@ -1216,7 +1216,7 @@ HSAKMT_STATUS topology_take_snapshot(void) {
goto err;
}
for (i = 0; i < sys_props.NumNodes; i++) {
rocr::core::WDDMDevice *device_;
wsl::thunk::WDDMDevice *device_;
topology_map_node_id(i, device_);
ret = topology_sysfs_get_node_props(i, &temp_props[i].node, &p2p_links,
@@ -1518,7 +1518,7 @@ hsaKmtGetNodeMemoryProperties(HSAuint32 NodeId, HSAuint32 NumBanks,
}
/* The following memory banks does not apply to CPU only node */
rocr::core::WDDMDevice *device_ = get_wddmdev(NodeId);
wsl::thunk::WDDMDevice *device_ = get_wddmdev(NodeId);
if (device_ == nullptr)
goto out;
@@ -1690,9 +1690,9 @@ HSAKMT_STATUS validate_nodeid_array(uint32_t **gpu_id_array,
uint32_t get_num_sysfs_nodes(void) { return num_sysfs_nodes; }
rocr::core::WDDMDevice *get_wddmdev(uint32_t node_id) {
wsl::thunk::WDDMDevice *get_wddmdev(uint32_t node_id) {
if ((!wdevices_.size()) || (!node_id) || (node_id >= num_sysfs_nodes))
return nullptr;
return wdevices_[node_id - 1];
}
}
util/atomic_helpers.h
+2 -2
Visa fil
@@ -64,7 +64,7 @@
#endif
#endif
namespace rocr {
namespace wsl {
namespace atomic {
static constexpr int c11ToBuiltInFlags(std::memory_order order)
@@ -506,7 +506,7 @@ static __forceinline T
return ret;
}
} // namespace atomic
} // namespace rocr
} // namespace wsl
#ifdef X64_ORDER_WC
#undef X64_ORDER_WC
util/flag.cpp
+2 -2
Visa fil
@@ -50,7 +50,7 @@
#include <algorithm>
#include <locale>
namespace rocr {
namespace wsl {
FILE* log_file = stderr;
uint8_t log_flags[8];
@@ -223,4 +223,4 @@ void Flag::parse_masks(std::string& var, uint32_t maxGpu, uint32_t maxCU) {
}
}
} // namespace rocr
} // namespace wsl
util/flag.h
+2 -2
Visa fil
@@ -52,7 +52,7 @@
#include "core/util/os.h"
#include "core/util/utils.h"
namespace rocr {
namespace wsl {
class Flag {
public:
@@ -355,6 +355,6 @@ class Flag {
DISALLOW_COPY_AND_ASSIGN(Flag);
};
} // namespace rocr
} // namespace wsl
#endif // header guard
util/lazy_ptr.h
+2 -2
Visa fil
@@ -50,7 +50,7 @@
#include "core/util/locks.h"
#include "core/util/utils.h"
namespace rocr {
namespace wsl {
/*
* Wrapper for a std::unique_ptr that initializes its object at first use.
@@ -150,6 +150,6 @@ template <typename T> class lazy_ptr {
};
} // namespace rocr
} // namespace wsl
#endif // HSA_RUNTIME_CORE_UTIL_LAZY_PTR_H_
util/lnx/os_linux.cpp
+2 -2
Visa fil
@@ -65,7 +65,7 @@
#include <cpuid.h>
#endif
namespace rocr {
namespace wsl {
namespace os {
struct ThreadArgs {
@@ -766,6 +766,6 @@ bool ParseCpuID(cpuid_t* cpuinfo) {
}
} // namespace os
} // namespace rocr
} // namespace wsl
#endif
util/locks.h
+2 -2
Visa fil
@@ -48,7 +48,7 @@
#include "utils.h"
#include "os.h"
namespace rocr {
namespace wsl {
class HybridMutex {
public:
@@ -285,6 +285,6 @@ template <class LockType> class ScopedAcquire {
DISALLOW_COPY_AND_ASSIGN(ScopedAcquire);
};
} // namespace rocr
} // namespace wsl
#endif // HSA_RUNTIME_CORE_SUTIL_LOCKS_H_
util/os.h
+2 -2
Visa fil
@@ -49,7 +49,7 @@
#include <vector>
#include "utils.h"
namespace rocr {
namespace wsl {
namespace os {
typedef void* LibHandle;
typedef void* Semaphore;
@@ -322,6 +322,6 @@ typedef struct cpuid_s {
bool ParseCpuID(cpuid_t* cpuinfo);
} // namespace os
} // namespace rocr
} // namespace wsl
#endif // HSA_RUNTIME_CORE_UTIL_OS_H_
util/simple_heap.h
+2 -2
Visa fil
@@ -53,7 +53,7 @@
#include "core/util/utils.h"
namespace rocr {
namespace wsl {
template <typename Allocator> class SimpleHeap {
private:
@@ -358,6 +358,6 @@ template <typename Allocator> class SimpleHeap {
}
};
} // namespace rocr
} // namespace wsl
#endif // HSA_RUNTME_CORE_UTIL_SIMPLE_HEAP_H_
util/small_heap.cpp
+2 -2
Visa fil
@@ -42,7 +42,7 @@
#include "small_heap.h"
namespace rocr {
namespace wsl {
// Inserts node into freelist after place.
// Assumes node will not be an end of the list (list has guard nodes).
@@ -182,4 +182,4 @@ void* SmallHeap::alloc_high(size_t bytes) {
return nullptr;
}
} // namespace rocr
} // namespace wsl
util/small_heap.h
+2 -2
Visa fil
@@ -52,7 +52,7 @@
#include "utils.h"
namespace rocr {
namespace wsl {
class SmallHeap {
private:
@@ -126,6 +126,6 @@ class SmallHeap {
void* high_split() const { return *high.begin(); }
};
} // namespace rocr
} // namespace wsl
#endif
util/timer.cpp
+2 -2
Visa fil
@@ -42,7 +42,7 @@
#include "core/util/timer.h"
namespace rocr {
namespace wsl {
namespace timer {
accurate_clock::init::init() {
@@ -108,4 +108,4 @@ double fast_clock::period_ps;
fast_clock::raw_frequency fast_clock::freq;
fast_clock::init fast_clock::fast_clock_init;
} // namespace timer
} // namespace rocr
} // namespace wsl
util/timer.h
+2 -2
Visa fil
@@ -49,7 +49,7 @@
#include <time.h>
#include <type_traits>
namespace rocr {
namespace wsl {
namespace timer {
// Needed to patch around a mixed arithmetic bug in MSVC's duration_cast as of
@@ -168,6 +168,6 @@ class fast_clock {
static init fast_clock_init;
};
} // namespace timer
} // namespace rocr
} // namespace wsl
#endif
util/utils.h
+3 -3
Visa fil
@@ -57,7 +57,7 @@
#include <sstream>
#include <thread>
namespace rocr {
namespace wsl {
extern FILE* log_file;
extern uint8_t log_flags[8];
@@ -154,7 +154,7 @@ static __forceinline unsigned long long int strtoull(const char* str,
#define LogPrint(flag, format, ...) \
do { \
if (hsa_flag_isset64(log_flags, flag)) \
rocr::log_printf(__FILENAME__, __LINE__, format, ##__VA_ARGS__); \
wsl::log_printf(__FILENAME__, __LINE__, format, ##__VA_ARGS__); \
} while (false);
@@ -354,7 +354,7 @@ static __forceinline std::string& rtrim(std::string& s) {
static __forceinline std::string& trim(std::string& s) { return ltrim(rtrim(s)); }
} // namespace rocr
} // namespace wsl
template <uint32_t lowBit, uint32_t highBit, typename T>
static __forceinline uint32_t BitSelect(T p) {
util/win/os_win.cpp
+2 -2
Visa fil
@@ -57,7 +57,7 @@
#undef Yield
#undef CreateMutex
namespace rocr {
namespace wsl {
namespace os {
static_assert(sizeof(LibHandle) == sizeof(HMODULE),
@@ -322,6 +322,6 @@ bool ParseCpuID(cpuid_t* cpuinfo) {
}
} // namespace os
} // namespace rocr
} // namespace wsl
#endif
wddm/cmd_util.cpp
+4 -4
Visa fil
@@ -2,8 +2,8 @@
#include "inc/wddm/cmd_util.h"
namespace rocr {
namespace core {
namespace wsl {
namespace thunk {
/*
* Builds a COPY_DATA packet that copies data.
@@ -277,5 +277,5 @@ size_t CmdUtil::BuildAtomicMem(
return sizeof(atom);
}
} // namespace core
} // namespace rocr
} // namespace thunk
} // namespace wsl
wddm/device.cpp
+10 -10
Visa fil
@@ -53,8 +53,8 @@
#include "inc/wddm/device.h"
#include "inc/wddm/queue.h"
namespace rocr {
namespace core {
namespace wsl {
namespace thunk {
const uint32_t WDDMDevice::cmdbuf_aql_frame_num_ = 0x1000;
@@ -294,7 +294,7 @@ bool WDDMDevice::ReserveLocalHeapSpace(void) {
sys_va[i] = (uint64_t)ptr;
if (thunk::ReserveGpuVirtualAddress(
if (d3dthunk::ReserveGpuVirtualAddress(
adapter_, local_heap_space_size_,
(uint64_t)ptr,
(uint64_t)ptr + sys_va_size, &local_va) == ErrorCode::Success) {
@@ -337,7 +337,7 @@ bool WDDMDevice::ReserveLocalHeapSpace(void) {
}
bool WDDMDevice::FreeLocalHeapSpace(void) {
thunk::FreeGpuVirtualAddress(adapter_, local_heap_space_start_, local_heap_space_size_);
d3dthunk::FreeGpuVirtualAddress(adapter_, local_heap_space_start_, local_heap_space_size_);
void *cpu = (void *)local_heap_space_start_;
return munmap(cpu, local_heap_space_size_) == 0;
}
@@ -377,7 +377,7 @@ ErrorCode WDDMDevice::ReserveGpuVirtualAddress(const rocr_proxy::AllocDomain dom
if (domain == rocr_proxy::kSystem) {
code = thunk::ReserveGpuVirtualAddress(adapter_, size,
code = d3dthunk::ReserveGpuVirtualAddress(adapter_, size,
system_heap_space_start_,
system_heap_space_start_ + system_heap_space_size_,
&gpu_addr);
@@ -385,7 +385,7 @@ ErrorCode WDDMDevice::ReserveGpuVirtualAddress(const rocr_proxy::AllocDomain dom
return code;
if (!CommitSystemHeapSpace((void*)gpu_addr, size, lock)) {
thunk::FreeGpuVirtualAddress(adapter_, gpu_addr, size);
d3dthunk::FreeGpuVirtualAddress(adapter_, gpu_addr, size);
code = ErrorCode::SyscallFail;
}
} else {
@@ -411,12 +411,12 @@ ErrorCode WDDMDevice::FreeGpuVirtualAddress(const rocr_proxy::AllocDomain domain
DecommitSystemHeapSpace((void *)gpu_addr, size);
thunk::FreeGpuVirtualAddressArgs free_args{};
d3dthunk::FreeGpuVirtualAddressArgs free_args{};
free_args.hAdapter = adapter_;
free_args.BaseAddress = gpu_addr;
free_args.Size = size;
code = thunk::FreeGpuVirtualAddress(&free_args);
code = d3dthunk::FreeGpuVirtualAddress(&free_args);
} else {
local_va_mgr_->Free(gpu_addr);
}
@@ -875,5 +875,5 @@ bool WDDMDevice::SubmitToHwQueue(WDDMQueue *queue, uint64_t command_addr,
return true;
}
} // namespace core
} // namespace rocr
} // namespace thunk
} // namespace wsl
wddm/gpu_memory.cpp
+23 -23
Visa fil
@@ -6,11 +6,11 @@
using namespace std;
namespace rocr {
namespace core {
namespace wsl {
namespace thunk {
size_t GpuMemory::CalcChunkNumbers(gpusize size) {
const auto chunk_size = core::WDDMDevice::GpuMemoryChunkSize;
const auto chunk_size = WDDMDevice::GpuMemoryChunkSize;
return (size + chunk_size - 1) / chunk_size;
}
@@ -123,13 +123,13 @@ ErrorCode GpuMemory::UnmapGpuVirtualAddress(const gpusize addr, const gpusize si
auto map_addr = addr;
auto map_size = size;
while (offset >= core::WDDMDevice::GpuMemoryChunkSize) {
offset -= core::WDDMDevice::GpuMemoryChunkSize;
while (offset >= WDDMDevice::GpuMemoryChunkSize) {
offset -= WDDMDevice::GpuMemoryChunkSize;
i += 1;
}
while (map_size > 0) {
auto block_size = std::min(map_size, core::WDDMDevice::GpuMemoryChunkSize);
auto block_size = std::min(map_size, WDDMDevice::GpuMemoryChunkSize);
D3DDDI_MAPGPUVIRTUALADDRESS args{};
@@ -139,7 +139,7 @@ ErrorCode GpuMemory::UnmapGpuVirtualAddress(const gpusize addr, const gpusize si
args.SizeInPages = block_size / 0x1000;
args.Protection.NoAccess = 1;
code = thunk::MapGpuVirtualAddress(&args);
code = d3dthunk::MapGpuVirtualAddress(&args);
if (code == ErrorCode::NotReady)
device_->UpdatePageFence(args.PagingFenceValue);
@@ -163,8 +163,8 @@ ErrorCode GpuMemory::MapGpuVirtualAddress(const gpusize addr, const gpusize size
auto map_size = size;
const size_t _4K = 0x1000;
while (offset >= core::WDDMDevice::GpuMemoryChunkSize) {
offset -= core::WDDMDevice::GpuMemoryChunkSize;
while (offset >= WDDMDevice::GpuMemoryChunkSize) {
offset -= WDDMDevice::GpuMemoryChunkSize;
i += 1;
}
const size_t first_chunk = i;
@@ -174,7 +174,7 @@ ErrorCode GpuMemory::MapGpuVirtualAddress(const gpusize addr, const gpusize size
* 2. visible vram can not be cpu mapped when command submission or after gpu mapped
*/
while (map_size > 0) {
auto block_size = std::min(map_size, core::WDDMDevice::GpuMemoryChunkSize);
auto block_size = std::min(map_size, WDDMDevice::GpuMemoryChunkSize);
D3DDDI_MAPGPUVIRTUALADDRESS args{};
@@ -185,7 +185,7 @@ ErrorCode GpuMemory::MapGpuVirtualAddress(const gpusize addr, const gpusize size
args.SizeInPages = block_size / _4K;
args.Protection.Write = 1;
code = thunk::MapGpuVirtualAddress(&args);
code = d3dthunk::MapGpuVirtualAddress(&args);
if (code != ErrorCode::Success) {
if (code == ErrorCode::NotReady) {
@@ -208,7 +208,7 @@ ErrorCode GpuMemory::MapGpuVirtualAddress(const gpusize addr, const gpusize size
map_addr = addr;
map_size = size;
for (size_t j = first_chunk; j < i; j++) {
auto block_size = std::min(map_size, core::WDDMDevice::GpuMemoryChunkSize);
auto block_size = std::min(map_size, WDDMDevice::GpuMemoryChunkSize);
D3DDDI_MAPGPUVIRTUALADDRESS args{};
@@ -219,7 +219,7 @@ ErrorCode GpuMemory::MapGpuVirtualAddress(const gpusize addr, const gpusize size
args.SizeInPages = block_size / _4K;
args.Protection.NoAccess = 1;
auto unmap_code = thunk::MapGpuVirtualAddress(&args);
auto unmap_code = d3dthunk::MapGpuVirtualAddress(&args);
if (unmap_code == ErrorCode::NotReady)
device_->UpdatePageFence(args.PagingFenceValue);
@@ -274,7 +274,7 @@ ErrorCode GpuMemory::CreatePhysicalMemory() {
for (size_t i = 0; i < num_allocations; i++) {
void* priv_data = (void*)((char*)priv_drv_data + priv_drv_data_size * i);
size_t block_size = std::min(size, core::WDDMDevice::GpuMemoryChunkSize);
size_t block_size = std::min(size, WDDMDevice::GpuMemoryChunkSize);
if (IsUserMemory() || IsSystem()) {
rocr_proxy::SetAllocationInfo(priv_data, block_size, desc_.domain, 0, desc_.mem_flags, desc_.engine_flag, device_info);
@@ -314,7 +314,7 @@ ErrorCode GpuMemory::CreatePhysicalMemory() {
args.Flags.CreateResource = 1;
}
auto status = thunk::CreateAllocation(&args);
auto status = d3dthunk::CreateAllocation(&args);
if (status == ErrorCode::Success) {
for (size_t i = 0; i < num_allocations; i++)
alloc_handles_ptr_[i] = alloc_info[i].hAllocation;
@@ -331,7 +331,7 @@ ErrorCode GpuMemory::FreePhysicalMemory() {
if (alloc_handles_ptr_ == nullptr || (NumChunks() == 1 && *alloc_handles_ptr_ == 0))
return code;
code = thunk::DestroyAllocation(device_->DeviceHandle(),
code = d3dthunk::DestroyAllocation(device_->DeviceHandle(),
resource_,
NumChunks(),
alloc_handles_ptr_);
@@ -350,7 +350,7 @@ ErrorCode GpuMemory::MakeResident() {
args.AllocationList = alloc_handles_ptr_;
args.Flags.CantTrimFurther = 1;
auto code = thunk::MakeResident(&args);
auto code = d3dthunk::MakeResident(&args);
if (code == ErrorCode::NotReady) {
const auto fence_value = args.PagingFenceValue;
device_->UpdatePageFence(fence_value);
@@ -366,12 +366,12 @@ ErrorCode GpuMemory::Evict() {
args.NumAllocations = NumChunks();
args.AllocationList = alloc_handles_ptr_;
return thunk::Evict(&args);
return d3dthunk::Evict(&args);
}
ErrorCode GpuMemory::ExportPhysicalHandle(int* dmabuf_fd, uint32_t flags) {
if (IsShared())
return thunk::ShareObjects(num_allocations_, resource_, flags, dmabuf_fd);
return d3dthunk::ShareObjects(num_allocations_, resource_, flags, dmabuf_fd);
else
return ErrorCode::UnSupported;
}
@@ -386,7 +386,7 @@ ErrorCode GpuMemory::ImportPhysicalHandle(int dmabuf_fd) {
memset(&query_args, 0, sizeof(query_args));
query_args.hDevice = device_->DeviceHandle();
query_args.hNtHandle = reinterpret_cast<HANDLE>(dmabuf_fd);
auto ret = thunk::QueryResourceInfoFromNtHandle(&query_args);
auto ret = d3dthunk::QueryResourceInfoFromNtHandle(&query_args);
if (ret != ErrorCode::Success) {
debug_print("%s query resource info from nt handle failed %d\n", __FUNCTION__, static_cast<int>(ret));
return ErrorCode::InvalidateParams;
@@ -435,7 +435,7 @@ ErrorCode GpuMemory::ImportPhysicalHandle(int dmabuf_fd) {
open_args.PrivateRuntimeDataSize = query_args.PrivateRuntimeDataSize;
open_args.pPrivateRuntimeData = reinterpret_cast<void*> (&shared_info);
ret = thunk::OpenResourceFromNtHandle(&open_args);
ret = d3dthunk::OpenResourceFromNtHandle(&open_args);
if (ret != ErrorCode::Success) {
ret = ErrorCode::InvalidateParams;
debug_print("%s open resource failed %d\n", __FUNCTION__, static_cast<int>(ret));
@@ -463,5 +463,5 @@ err_out:
return ret;
}
} // namespace code
} // namespace rocr
} // namespace thunk
} // namespace wsl
wddm/queue.cpp
+4 -4
Visa fil
@@ -48,8 +48,8 @@
#include "inc/registers.h"
#include "libhsakmt.h"
namespace rocr {
namespace core {
namespace wsl {
namespace thunk {
hsa_status_t WDDMQueue::SwsInit(void) {
if (!device->CreateSyncobj(&syncobj, &sync_addr))
@@ -985,5 +985,5 @@ hsa_status_t SDMAQueue::Submit(void) {
return HSA_STATUS_SUCCESS;
}
}
}
} // namespace thunk
} // namespace wsl
wddm/va_mgr.cpp
+4 -4
Visa fil
@@ -5,8 +5,8 @@
using namespace std;
namespace rocr {
namespace core {
namespace wsl {
namespace thunk {
VaMgr::VaMgr(uint64_t start, uint64_t size, uint64_t min_align) {
min_align_ = min_align;
@@ -159,5 +159,5 @@ void VaMgr::Free(uint64_t addr) {
set_free(frag_it->second, it);
}
} // namespace core
} // namespace rocr
} // namespace thunk
} // namespace wsl