Initiali support for CWSR on thunk

1. Add IOCTL defines to set trap handler
2. Add control stack size information on create queue argument.
3. Increase the total save&restore area size for carrizo to include the control stack size.

Signed-off-by: Shaoyun Liu <Shaoyun.liu@amd.com>

Change-Id: Iccf15e073b7db2519e96e7f7b46a89d57ab9a4df


[ROCm/ROCR-Runtime commit: 2d63ee7b8f]

projects/rocr-runtime/include/linux/kfd_ioctl.h

@@ -58,7 +58,8 @@ struct kfd_ioctl_create_queue_args {
 	uint64_t eop_buffer_address;	/* to KFD */
 	uint64_t eop_buffer_size;	/* to KFD */
 	uint64_t ctx_save_restore_address; /* to KFD */
-	uint64_t ctx_save_restore_size;	/* to KFD */
+	uint32_t ctx_save_restore_size;	/* to KFD */
+	uint32_t ctl_stack_size; 	/* to KFD */
 };
 
 struct kfd_ioctl_destroy_queue_args {
@@ -95,6 +96,13 @@ struct kfd_ioctl_set_memory_policy_args {
 	uint32_t pad;
 };
 
+struct kfd_ioctl_set_trap_handler_args {
+	uint64_t tba_addr;
+	uint64_t tma_addr;
+	uint32_t gpu_id;			/* to KFD */
+	uint32_t pad;
+};
+
 /*
  * All counters are monotonic. They are used for profiling of compute jobs.
  * The profiling is done by userspace.
@@ -379,7 +387,10 @@ struct kfd_ioctl_alloc_memory_of_gpu_new_args {
 		AMDKFD_IOWR(0x19, struct kfd_ioctl_alloc_memory_of_gpu_new_args)
 
 
+#define AMDKFD_IOC_SET_TRAP_HANDLER		\
+		AMDKFD_IOW(0x1a, struct kfd_ioctl_set_trap_handler_args)
+
 #define AMDKFD_COMMAND_START		0x01
-#define AMDKFD_COMMAND_END		0x20
+#define AMDKFD_COMMAND_END		0x1b
 
 #endif

projects/rocr-runtime/src/queues.c

@@ -49,18 +49,21 @@ struct device_info
 {
 	enum asic_family_type asic_family;
 	uint32_t ctx_save_restore_size;
+	uint32_t ctl_stack_size;
 	uint32_t eop_buffer_size;
 };
 
 struct device_info kaveri_device_info = {
 	.asic_family = CHIP_KAVERI,
 	.ctx_save_restore_size = 0,
+	.ctl_stack_size = 0,
 	.eop_buffer_size = 0,
 };
 
 struct device_info carrizo_device_info = {
 	.asic_family = CHIP_CARRIZO,
-	.ctx_save_restore_size = 2756608,
+	.ctx_save_restore_size = 2756608 + 4096,
+	.ctl_stack_size = 4096,
 	.eop_buffer_size = 4096,
 };
 
@@ -164,7 +167,6 @@ static void* allocate_exec_aligned_memory_cpu(uint32_t size, uint32_t align)
 		free(ptr);
 		return NULL;
 	}
-
 	memset(ptr, 0, size);
 	return ptr;
 }
@@ -260,6 +262,7 @@ static int handle_concrete_asic(struct device_info *dev_info, struct queue *q,
 		}
 		if (dev_info->ctx_save_restore_size > 0) {
 			args->ctx_save_restore_size = dev_info->ctx_save_restore_size;
+			args->ctl_stack_size = dev_info->ctl_stack_size;
 			q->ctx_save_restore =
 					allocate_exec_aligned_memory(dev_info->ctx_save_restore_size, PAGE_SIZE, dev_info->asic_family);
 			if (q->ctx_save_restore == NULL) {;
@@ -470,3 +473,35 @@ hsaKmtSetQueueCUMask(
 
 	return HSAKMT_STATUS_SUCCESS;
 }
+
+HSAKMT_STATUS
+HSAKMTAPI
+hsaKmtSetTrapHandler(
+	HSAuint32	Node,
+	void *TrapHandlerBaseAddress,
+	HSAuint64	TrapHandlerSizeInBytes,
+	void *TrapBufferBaseAddress,
+	HSAuint64 TrapBufferSizeInBytes
+)
+{
+	struct kfd_ioctl_set_trap_handler_args args;
+	HSAKMT_STATUS result;
+	uint32_t gpu_id;
+
+	CHECK_KFD_OPEN();
+
+	result = validate_nodeid(Node, &gpu_id);
+	if (result != HSAKMT_STATUS_SUCCESS)
+		return result;
+
+	memset(&args, 0, sizeof(args));
+
+	args.gpu_id = gpu_id;
+	args.tba_addr = (uintptr_t)TrapHandlerBaseAddress;
+	args.tma_addr = (uintptr_t)TrapBufferBaseAddress;
+
+	int err = kmtIoctl(kfd_fd, AMDKFD_IOC_SET_TRAP_HANDLER, &args);
+
+	return (err == -1) ? HSAKMT_STATUS_ERROR : HSAKMT_STATUS_SUCCESS;
+}
+