P4 to Git Change 2008906 by axie@axie-hip-vdi-pal2 on 2019/10/04 18:55:34

SWDEV-189650 - [HIP-CLANG][HIP/VDI/PAL] Hangs on test hip_threadfence_system
	1. In HIP + VDI + ROCm, allow SVM atomic in VEGA10 and later ASIC. GFX8 (Tonga) was enabled before.
	2. In HIP + VDI + PAL Linux driver, allow SVM atomic in VEGA10 and later ASIC.

	Tests:
	1. In HIP + VDI + ROCm, hip_threadfence_system test passed.
	2. In HIP + VDI + PAL + Linux , hip_threadfence_system test passed.
	3. OpenCL + PAL, clinfo and ocltest runtime test pass.
	4. OpenCL + ROCM, clinfo and ocltest runtime test pass.
	5. Windows 10, VEGA 10, clinfo and and ocltest runtime test pass. hip_threadfence_system test passed by skipping the test.

	Teamcity presubmission test:
	http://ocltc.amd.com:8111/viewModification.html?modId=127083&personal=true&tab=vcsModificationBuilds
	http://ocltc.amd.com:8111/viewModification.html?modId=127076&personal=true&tab=vcsModificationBuilds

	ReviewBoard: http://ocltc.amd.com/reviews/r/18077/

Affected files ...

... //depot/stg/opencl/drivers/opencl/api/hip/hip_memory.cpp#73 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/pal/paldevice.cpp#171 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/pal/palresource.cpp#80 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/pal/palresource.hpp#31 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/rocm/rocdevice.cpp#134 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/rocm/rocmemory.cpp#44 edit
... //depot/stg/opencl/drivers/opencl/runtime/utils/flags.hpp#320 edit
This commit is contained in:
foreman
2019-10-04 19:02:35 -04:00
vanhempi 3bfe682c3f
commit d3b6a9731c
6 muutettua tiedostoa jossa 69 lisäystä ja 10 poistoa
@@ -621,6 +621,13 @@ void NullDevice::fillDeviceInfo(const Pal::DeviceProperties& palProp,
if (settings().svmFineGrainSystem_) {
info_.svmCapabilities_ |= CL_DEVICE_SVM_FINE_GRAIN_SYSTEM;
}
if (IS_LINUX) {
// Report atomics capability based on GFX IP
// The atomic test failed in Windows OS.
if (amd::IS_HIP && ipLevel_ >= Pal::GfxIpLevel::GfxIp9) {
info_.svmCapabilities_ |= CL_DEVICE_SVM_ATOMICS;
}
}
// OpenCL2.0 device info fields
info_.maxWriteImageArgs_ = MaxReadWriteImage; //!< For compatibility
info_.maxReadWriteImageArgs_ = MaxReadWriteImage;
@@ -275,6 +275,7 @@ Resource::Resource(const Device& gpuDev, size_t size)
desc_.scratch_ = false;
desc_.isAllocExecute_ = false;
desc_.baseLevel_ = 0;
desc_.gl2CacheDisabled_ = false;
gpuDev.addResource(this);
}
@@ -311,7 +312,7 @@ Resource::Resource(const Device& gpuDev, size_t width, size_t height, size_t dep
desc_.scratch_ = false;
desc_.isAllocExecute_ = false;
desc_.baseLevel_ = 0;
desc_.gl2CacheDisabled_ = false;
switch (imageType) {
case CL_MEM_OBJECT_IMAGE2D:
desc_.dimSize_ = 2;
@@ -1194,6 +1195,9 @@ bool Resource::create(MemoryType memType, CreateParams* params, bool forceLinear
svmPtr = reinterpret_cast<Pal::gpusize>(params->owner_->getSvmPtr());
desc_.SVMRes_ = true;
svmPtr = (svmPtr == 1) ? 0 : svmPtr;
if (params->owner_->getMemFlags() & CL_MEM_SVM_ATOMICS) {
desc_.gl2CacheDisabled_ = true;
}
}
if (desc_.SVMRes_) {
return CreateSvm(params, svmPtr);
@@ -1958,6 +1962,23 @@ bool FineMemorySubAllocator::CreateChunk(const Pal::IGpuMemory* reserved_va) {
return false;
}
// ================================================================================================
bool FineUncachedMemorySubAllocator::CreateChunk(const Pal::IGpuMemory* reserved_va) {
Pal::SvmGpuMemoryCreateInfo createInfo = {};
createInfo.isUsedForKernel = false;
createInfo.size = device_->settings().subAllocationChunkSize_;
createInfo.alignment = MaxGpuAlignment;
createInfo.flags.useReservedGpuVa = (reserved_va != nullptr);
createInfo.pReservedGpuVaOwner = reserved_va;
createInfo.flags.gl2Uncached = true;
GpuMemoryReference* mem_ref = GpuMemoryReference::Create(*device_, createInfo);
if ((mem_ref != nullptr) && InitAllocator(mem_ref)) {
mem_ref->iMem()->Map(&mem_ref->cpuAddress_);
return mem_ref->cpuAddress_ != nullptr;
}
return false;
}
// ================================================================================================
MemorySubAllocator::~MemorySubAllocator() {
// Release memory heap for suballocations
@@ -2044,7 +2065,11 @@ bool ResourceCache::addGpuMemory(Resource::Descriptor* desc, GpuMemoryReference*
} else if ((desc->type_ == Resource::Local) && desc->SVMRes_) {
result = mem_sub_alloc_coarse_.Free(&lockCacheOps_, ref, offset);
} else if (desc->SVMRes_) {
result = mem_sub_alloc_fine_.Free(&lockCacheOps_, ref, offset);
if (desc->gl2CacheDisabled_) {
result = mem_sub_alloc_fine_uncached_.Free(&lockCacheOps_, ref, offset);
} else {
result = mem_sub_alloc_fine_.Free(&lockCacheOps_, ref, offset);
}
}
// If a resource was a suballocation, don't try to cache it
@@ -2095,7 +2120,11 @@ GpuMemoryReference* ResourceCache::findGpuMemory(Resource::Descriptor* desc, Pal
} else if ((desc->type_ == Resource::Local) && desc->SVMRes_) {
ref = mem_sub_alloc_coarse_.Allocate(size, alignment, reserved_va, offset);
} else if (desc->SVMRes_) {
ref = mem_sub_alloc_fine_.Allocate(size, alignment, reserved_va, offset);
if (desc->gl2CacheDisabled_) {
ref = mem_sub_alloc_fine_uncached_.Allocate(size, alignment, reserved_va, offset);
} else {
ref = mem_sub_alloc_fine_.Allocate(size, alignment, reserved_va, offset);
}
}
if (ref != nullptr) {
@@ -183,6 +183,7 @@ class Resource : public amd::HeapObject {
uint scratch_ : 1; //!< Scratch buffer
uint isAllocExecute_ : 1; //!< SVM resource allocation attribute for shader\cmdbuf
uint isDoppTexture_ : 1; //!< PAL resource is for a DOPP desktop texture
uint gl2CacheDisabled_ : 1;//!< PAL resource is allocated with GPU L2 cache disabled.
};
uint state_;
};
@@ -534,6 +535,12 @@ class FineMemorySubAllocator : public MemorySubAllocator {
bool CreateChunk(const Pal::IGpuMemory* reserved_va) override;
};
class FineUncachedMemorySubAllocator : public MemorySubAllocator {
public:
FineUncachedMemorySubAllocator(Device* device) : MemorySubAllocator(device) {}
bool CreateChunk(const Pal::IGpuMemory* reserved_va) override;
};
class ResourceCache : public amd::HeapObject {
public:
//! Default constructor
@@ -544,7 +551,8 @@ class ResourceCache : public amd::HeapObject {
cacheSizeLimit_(cacheSizeLimit),
mem_sub_alloc_local_(device),
mem_sub_alloc_coarse_(device),
mem_sub_alloc_fine_(device) {}
mem_sub_alloc_fine_(device),
mem_sub_alloc_fine_uncached_(device){}
//! Default destructor
~ResourceCache();
@@ -591,9 +599,10 @@ class ResourceCache : public amd::HeapObject {
//! PAL resource cache
std::list<std::pair<Resource::Descriptor*, GpuMemoryReference*> > resCache_;
MemorySubAllocator mem_sub_alloc_local_; //!< Allocator for suballocations in Local
CoarseMemorySubAllocator mem_sub_alloc_coarse_; //!< Allocator for suballocations in Coarse SVM
FineMemorySubAllocator mem_sub_alloc_fine_; //!< Allocator for suballocations in Fine SVM
MemorySubAllocator mem_sub_alloc_local_; //!< Allocator for suballocations in Local
CoarseMemorySubAllocator mem_sub_alloc_coarse_; //!< Allocator for suballocations in Coarse SVM
FineMemorySubAllocator mem_sub_alloc_fine_; //!< Allocator for suballocations in Fine SVM
FineUncachedMemorySubAllocator mem_sub_alloc_fine_uncached_; //!< Allocator for suballocations in Fine uncached SVM
};
/*@}*/ // namespace pal
@@ -1325,7 +1325,13 @@ bool Device::populateOCLDeviceConstants() {
if (agent_profile_ == HSA_PROFILE_FULL) {
info_.svmCapabilities_ |= CL_DEVICE_SVM_FINE_GRAIN_SYSTEM;
}
if (!settings().useLightning_) {
if (amd::IS_HIP) {
// Report atomics capability based on GFX IP, control on Hawaii
if (info_.hostUnifiedMemory_ || deviceInfo_.gfxipVersion_ >= 800) {
info_.svmCapabilities_ |= CL_DEVICE_SVM_ATOMICS;
}
}
else if (!settings().useLightning_) {
// Report atomics capability based on GFX IP, control on Hawaii
// and Vega10.
if (info_.hostUnifiedMemory_ ||
@@ -697,7 +697,12 @@ bool Buffer::create() {
if (owner()->getSvmPtr() == reinterpret_cast<void*>(1)) {
if (isFineGrain) {
deviceMemory_ = dev().hostAlloc(size(), 1, false);
if (memFlags & CL_MEM_SVM_ATOMICS) {
deviceMemory_ = dev().hostAlloc(size(), 1, true);
}
else {
deviceMemory_ = dev().hostAlloc(size(), 1, false);
}
flags_ |= HostMemoryDirectAccess;
} else {
deviceMemory_ = dev().deviceLocalAlloc(size());
+4 -1
Näytä tiedosto
@@ -204,7 +204,10 @@ release(uint, AMD_SERIALIZE_COPY, 0, \
"Serialize copies, 0x1 = Wait for completion before enqueue" \
"0x2 = Wait for completion after enqueue 0x3 = both") \
release(bool, PAL_ALWAYS_RESIDENT, false, \
"Force memory resources to become resident at allocation time")
"Force memory resources to become resident at allocation time") \
release(uint, HIP_HOST_COHERENT, 0, \
"Coherent memory in hipHostMalloc, 0x1 = memory is coherent with host"\
"0x0 = memory is not coherent between host and GPU")
namespace amd {