P4 to Git Change 2008906 by axie@axie-hip-vdi-pal2 on 2019/10/04 18:55:34
SWDEV-189650 - [HIP-CLANG][HIP/VDI/PAL] Hangs on test hip_threadfence_system 1. In HIP + VDI + ROCm, allow SVM atomic in VEGA10 and later ASIC. GFX8 (Tonga) was enabled before. 2. In HIP + VDI + PAL Linux driver, allow SVM atomic in VEGA10 and later ASIC. Tests: 1. In HIP + VDI + ROCm, hip_threadfence_system test passed. 2. In HIP + VDI + PAL + Linux , hip_threadfence_system test passed. 3. OpenCL + PAL, clinfo and ocltest runtime test pass. 4. OpenCL + ROCM, clinfo and ocltest runtime test pass. 5. Windows 10, VEGA 10, clinfo and and ocltest runtime test pass. hip_threadfence_system test passed by skipping the test. Teamcity presubmission test: http://ocltc.amd.com:8111/viewModification.html?modId=127083&personal=true&tab=vcsModificationBuilds http://ocltc.amd.com:8111/viewModification.html?modId=127076&personal=true&tab=vcsModificationBuilds ReviewBoard: http://ocltc.amd.com/reviews/r/18077/ Affected files ... ... //depot/stg/opencl/drivers/opencl/api/hip/hip_memory.cpp#73 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/pal/paldevice.cpp#171 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/pal/palresource.cpp#80 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/pal/palresource.hpp#31 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/rocm/rocdevice.cpp#134 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/rocm/rocmemory.cpp#44 edit ... //depot/stg/opencl/drivers/opencl/runtime/utils/flags.hpp#320 edit
This commit is contained in:
@@ -621,6 +621,13 @@ void NullDevice::fillDeviceInfo(const Pal::DeviceProperties& palProp,
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if (settings().svmFineGrainSystem_) {
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info_.svmCapabilities_ |= CL_DEVICE_SVM_FINE_GRAIN_SYSTEM;
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}
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if (IS_LINUX) {
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// Report atomics capability based on GFX IP
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// The atomic test failed in Windows OS.
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if (amd::IS_HIP && ipLevel_ >= Pal::GfxIpLevel::GfxIp9) {
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info_.svmCapabilities_ |= CL_DEVICE_SVM_ATOMICS;
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}
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}
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// OpenCL2.0 device info fields
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info_.maxWriteImageArgs_ = MaxReadWriteImage; //!< For compatibility
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info_.maxReadWriteImageArgs_ = MaxReadWriteImage;
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@@ -275,6 +275,7 @@ Resource::Resource(const Device& gpuDev, size_t size)
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desc_.scratch_ = false;
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desc_.isAllocExecute_ = false;
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desc_.baseLevel_ = 0;
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desc_.gl2CacheDisabled_ = false;
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gpuDev.addResource(this);
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}
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@@ -311,7 +312,7 @@ Resource::Resource(const Device& gpuDev, size_t width, size_t height, size_t dep
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desc_.scratch_ = false;
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desc_.isAllocExecute_ = false;
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desc_.baseLevel_ = 0;
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desc_.gl2CacheDisabled_ = false;
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switch (imageType) {
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case CL_MEM_OBJECT_IMAGE2D:
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desc_.dimSize_ = 2;
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@@ -1194,6 +1195,9 @@ bool Resource::create(MemoryType memType, CreateParams* params, bool forceLinear
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svmPtr = reinterpret_cast<Pal::gpusize>(params->owner_->getSvmPtr());
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desc_.SVMRes_ = true;
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svmPtr = (svmPtr == 1) ? 0 : svmPtr;
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if (params->owner_->getMemFlags() & CL_MEM_SVM_ATOMICS) {
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desc_.gl2CacheDisabled_ = true;
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}
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}
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if (desc_.SVMRes_) {
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return CreateSvm(params, svmPtr);
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@@ -1958,6 +1962,23 @@ bool FineMemorySubAllocator::CreateChunk(const Pal::IGpuMemory* reserved_va) {
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return false;
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}
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// ================================================================================================
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bool FineUncachedMemorySubAllocator::CreateChunk(const Pal::IGpuMemory* reserved_va) {
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Pal::SvmGpuMemoryCreateInfo createInfo = {};
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createInfo.isUsedForKernel = false;
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createInfo.size = device_->settings().subAllocationChunkSize_;
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createInfo.alignment = MaxGpuAlignment;
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createInfo.flags.useReservedGpuVa = (reserved_va != nullptr);
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createInfo.pReservedGpuVaOwner = reserved_va;
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createInfo.flags.gl2Uncached = true;
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GpuMemoryReference* mem_ref = GpuMemoryReference::Create(*device_, createInfo);
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if ((mem_ref != nullptr) && InitAllocator(mem_ref)) {
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mem_ref->iMem()->Map(&mem_ref->cpuAddress_);
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return mem_ref->cpuAddress_ != nullptr;
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}
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return false;
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}
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// ================================================================================================
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MemorySubAllocator::~MemorySubAllocator() {
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// Release memory heap for suballocations
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@@ -2044,7 +2065,11 @@ bool ResourceCache::addGpuMemory(Resource::Descriptor* desc, GpuMemoryReference*
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} else if ((desc->type_ == Resource::Local) && desc->SVMRes_) {
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result = mem_sub_alloc_coarse_.Free(&lockCacheOps_, ref, offset);
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} else if (desc->SVMRes_) {
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result = mem_sub_alloc_fine_.Free(&lockCacheOps_, ref, offset);
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if (desc->gl2CacheDisabled_) {
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result = mem_sub_alloc_fine_uncached_.Free(&lockCacheOps_, ref, offset);
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} else {
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result = mem_sub_alloc_fine_.Free(&lockCacheOps_, ref, offset);
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}
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}
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// If a resource was a suballocation, don't try to cache it
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@@ -2095,7 +2120,11 @@ GpuMemoryReference* ResourceCache::findGpuMemory(Resource::Descriptor* desc, Pal
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} else if ((desc->type_ == Resource::Local) && desc->SVMRes_) {
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ref = mem_sub_alloc_coarse_.Allocate(size, alignment, reserved_va, offset);
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} else if (desc->SVMRes_) {
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ref = mem_sub_alloc_fine_.Allocate(size, alignment, reserved_va, offset);
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if (desc->gl2CacheDisabled_) {
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ref = mem_sub_alloc_fine_uncached_.Allocate(size, alignment, reserved_va, offset);
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} else {
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ref = mem_sub_alloc_fine_.Allocate(size, alignment, reserved_va, offset);
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}
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}
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if (ref != nullptr) {
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@@ -183,6 +183,7 @@ class Resource : public amd::HeapObject {
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uint scratch_ : 1; //!< Scratch buffer
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uint isAllocExecute_ : 1; //!< SVM resource allocation attribute for shader\cmdbuf
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uint isDoppTexture_ : 1; //!< PAL resource is for a DOPP desktop texture
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uint gl2CacheDisabled_ : 1;//!< PAL resource is allocated with GPU L2 cache disabled.
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};
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uint state_;
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};
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@@ -534,6 +535,12 @@ class FineMemorySubAllocator : public MemorySubAllocator {
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bool CreateChunk(const Pal::IGpuMemory* reserved_va) override;
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};
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class FineUncachedMemorySubAllocator : public MemorySubAllocator {
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public:
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FineUncachedMemorySubAllocator(Device* device) : MemorySubAllocator(device) {}
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bool CreateChunk(const Pal::IGpuMemory* reserved_va) override;
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};
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class ResourceCache : public amd::HeapObject {
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public:
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//! Default constructor
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@@ -544,7 +551,8 @@ class ResourceCache : public amd::HeapObject {
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cacheSizeLimit_(cacheSizeLimit),
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mem_sub_alloc_local_(device),
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mem_sub_alloc_coarse_(device),
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mem_sub_alloc_fine_(device) {}
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mem_sub_alloc_fine_(device),
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mem_sub_alloc_fine_uncached_(device){}
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//! Default destructor
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~ResourceCache();
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@@ -591,9 +599,10 @@ class ResourceCache : public amd::HeapObject {
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//! PAL resource cache
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std::list<std::pair<Resource::Descriptor*, GpuMemoryReference*> > resCache_;
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MemorySubAllocator mem_sub_alloc_local_; //!< Allocator for suballocations in Local
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CoarseMemorySubAllocator mem_sub_alloc_coarse_; //!< Allocator for suballocations in Coarse SVM
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FineMemorySubAllocator mem_sub_alloc_fine_; //!< Allocator for suballocations in Fine SVM
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MemorySubAllocator mem_sub_alloc_local_; //!< Allocator for suballocations in Local
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CoarseMemorySubAllocator mem_sub_alloc_coarse_; //!< Allocator for suballocations in Coarse SVM
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FineMemorySubAllocator mem_sub_alloc_fine_; //!< Allocator for suballocations in Fine SVM
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FineUncachedMemorySubAllocator mem_sub_alloc_fine_uncached_; //!< Allocator for suballocations in Fine uncached SVM
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};
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/*@}*/ // namespace pal
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@@ -1325,7 +1325,13 @@ bool Device::populateOCLDeviceConstants() {
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if (agent_profile_ == HSA_PROFILE_FULL) {
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info_.svmCapabilities_ |= CL_DEVICE_SVM_FINE_GRAIN_SYSTEM;
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}
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if (!settings().useLightning_) {
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if (amd::IS_HIP) {
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// Report atomics capability based on GFX IP, control on Hawaii
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if (info_.hostUnifiedMemory_ || deviceInfo_.gfxipVersion_ >= 800) {
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info_.svmCapabilities_ |= CL_DEVICE_SVM_ATOMICS;
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}
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}
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else if (!settings().useLightning_) {
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// Report atomics capability based on GFX IP, control on Hawaii
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// and Vega10.
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if (info_.hostUnifiedMemory_ ||
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@@ -697,7 +697,12 @@ bool Buffer::create() {
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if (owner()->getSvmPtr() == reinterpret_cast<void*>(1)) {
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if (isFineGrain) {
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deviceMemory_ = dev().hostAlloc(size(), 1, false);
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if (memFlags & CL_MEM_SVM_ATOMICS) {
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deviceMemory_ = dev().hostAlloc(size(), 1, true);
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}
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else {
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deviceMemory_ = dev().hostAlloc(size(), 1, false);
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}
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flags_ |= HostMemoryDirectAccess;
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} else {
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deviceMemory_ = dev().deviceLocalAlloc(size());
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@@ -204,7 +204,10 @@ release(uint, AMD_SERIALIZE_COPY, 0, \
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"Serialize copies, 0x1 = Wait for completion before enqueue" \
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"0x2 = Wait for completion after enqueue 0x3 = both") \
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release(bool, PAL_ALWAYS_RESIDENT, false, \
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"Force memory resources to become resident at allocation time")
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"Force memory resources to become resident at allocation time") \
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release(uint, HIP_HOST_COHERENT, 0, \
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"Coherent memory in hipHostMalloc, 0x1 = memory is coherent with host"\
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"0x0 = memory is not coherent between host and GPU")
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namespace amd {
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