P4 to Git Change 1546657 by gandryey@gera-w8 on 2018/04/26 10:59:34
SWDEV-151739 - [CQE OCL][DTB][Perf][QR][DTB-BLOCKER][VEGA10] Upto 18% performance drop observed while running Video Composition test sub test of Compubench due to faulty CL#1544622
- Implement customized TS tracking for managed buffers. The common TS tracking mechanism saves the event of the last command, assuming SDMA and compute operations occur in order, but for managed buffers it's not the case. Also managed buffer doesn't have to validate TS for the parent resource.
Affected files ...
... //depot/stg/opencl/drivers/opencl/runtime/device/pal/palblit.cpp#21 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/pal/palconstbuf.cpp#11 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/pal/palconstbuf.hpp#9 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/pal/palmemory.hpp#6 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/pal/palresource.hpp#22 edit
[ROCm/clr commit: 79ba5904dc]
Этот коммит содержится в:
@@ -267,7 +267,7 @@ bool DmaBlitManager::writeMemoryStaged(const void* srcHost, Memory& dstMemory, M
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chunkSize = gpu().xferWrite().MaxSize();
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} else {
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chunkSize = std::min(amd::alignUp(xferSize / 4, 256), gpu().xferWrite().MaxSize());
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chunkSize = std::max(chunkSize, 128 * Ki);
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chunkSize = std::max(chunkSize, 64 * Ki);
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bool flushDMA = true;
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}
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@@ -11,32 +11,34 @@ namespace pal {
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// ================================================================================================
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ManagedBuffer::ManagedBuffer(VirtualGPU& gpu, uint32_t size)
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: gpu_(gpu)
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, buffers_(MaxNumberOfBuffers)
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, activeBuffer_(0)
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, size_(size)
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, wrtOffset_(0)
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, wrtAddress_(nullptr) {}
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: gpu_(gpu)
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, pool_(MaxNumberOfBuffers)
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, activeBuffer_(0)
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, size_(size)
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, wrtOffset_(0)
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, wrtAddress_(nullptr) {}
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// ================================================================================================
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void ManagedBuffer::release() {
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for (auto it : buffers_) {
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if ((it != nullptr) && (it->data() != nullptr)) {
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it->unmap(&gpu_);
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for (auto it : pool_) {
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if ((it.buf != nullptr) && (it.buf->data() != nullptr)) {
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it.buf->unmap(&gpu_);
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}
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delete it;
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delete it.buf;
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}
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}
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// ================================================================================================
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bool ManagedBuffer::create(Resource::MemoryType type) {
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for (uint i = 0; i < buffers_.size(); ++i) {
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buffers_[i] = new Memory(const_cast<pal::Device&>(gpu_.dev()), size_);
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if (nullptr == buffers_[i] || !buffers_[i]->create(type)) {
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for (uint i = 0; i < pool_.size(); ++i) {
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pool_[i].buf = new Memory(const_cast<pal::Device&>(gpu_.dev()), size_);
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if (nullptr == pool_[i].buf || !pool_[i].buf->create(type)) {
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LogPrintfError("We couldn't create HW constant buffer, size(%d)!", size_);
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return false;
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}
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void* wrtAddress = buffers_[i]->map(&gpu_);
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// Assign virtual gpu to the allocation. Buffer will be used only on a particular queue
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pool_[i].buf->memRef()->gpu_ = &gpu_;
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void* wrtAddress = pool_[i].buf->map(&gpu_);
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if (wrtAddress == nullptr) {
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LogPrintfError("We couldn't map HW constant buffer, size(%d)!", size_);
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return false;
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@@ -45,9 +47,9 @@ bool ManagedBuffer::create(Resource::MemoryType type) {
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uint dummy = 0;
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static constexpr bool Wait = true;
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// Write 0 for the buffer paging by VidMM
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buffers_[i]->writeRawData(gpu_, 0, sizeof(dummy), &dummy, Wait);
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pool_[i].buf->writeRawData(gpu_, 0, sizeof(dummy), &dummy, Wait);
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}
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wrtAddress_ = buffers_[activeBuffer_]->data();
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wrtAddress_ = pool_[activeBuffer_].buf->data();
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return true;
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}
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@@ -59,18 +61,22 @@ address ManagedBuffer::reserve(uint32_t size, uint64_t* gpu_address) {
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// Align reserve size on the vector's boundary
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uint32_t count = amd::alignUp(size, MemAlignment);
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// Save previous event
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pinGpuEvent();
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// Check if buffer has enough space for reservation
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if ((wrtOffset_ + count) > size_) {
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// Get the next buffer in the list
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++activeBuffer_;
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activeBuffer_ %= MaxNumberOfBuffers;
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// Make sure the buffer isn't busy
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buffers_[activeBuffer_]->wait(gpu_);
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wrtAddress_ = buffers_[activeBuffer_]->data();
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gpu().waitForEvent(&pool_[activeBuffer_].events[SdmaEngine]);
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gpu().waitForEvent(&pool_[activeBuffer_].events[MainEngine]);
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wrtAddress_ = pool_[activeBuffer_].buf->data();
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wrtOffset_ = 0;
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}
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*gpu_address = buffers_[activeBuffer_]->vmAddress() + wrtOffset_;
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*gpu_address = pool_[activeBuffer_].buf->vmAddress() + wrtOffset_;
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address cpu_address = wrtAddress_ + wrtOffset_;
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// Adjust the offset by the reserved size
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@@ -80,23 +86,17 @@ address ManagedBuffer::reserve(uint32_t size, uint64_t* gpu_address) {
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}
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// ================================================================================================
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Memory& ManagedBuffer::reserveAtTheTop(uint32_t size)
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{
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// Get the next buffer in the list
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++activeBuffer_;
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activeBuffer_ %= MaxNumberOfBuffers;
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// Make sure the buffer isn't busy
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buffers_[activeBuffer_]->wait(gpu_);
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wrtAddress_ = buffers_[activeBuffer_]->data();
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wrtOffset_ = 0;
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return *buffers_[activeBuffer_];
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void ManagedBuffer::pinGpuEvent() {
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GpuEvent* event = activeMemory()->getGpuEvent(gpu());
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pool_[activeBuffer_].events[event->engineId_] = *event;
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activeMemory()->setBusy(gpu(), GpuEvent::InvalidID);
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}
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// ================================================================================================
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ConstantBuffer::ConstantBuffer(ManagedBuffer& mbuf, uint32_t size)
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: mbuf_(mbuf)
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, sys_mem_copy_(nullptr)
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, size_(size)
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: mbuf_(mbuf)
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, sys_mem_copy_(nullptr)
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, size_(size)
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{}
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// ================================================================================================
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@@ -127,11 +127,11 @@ uint64_t ConstantBuffer::UploadDataToHw(uint32_t size) const {
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// ================================================================================================
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uint64_t ConstantBuffer::UploadDataToHw(const void* sysmem, uint32_t size) const {
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uint64_t vm_address;
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address cpu_address = mbuf_.reserve(size, &vm_address);
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// Update memory with new CB data
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memcpy(cpu_address, sysmem, size);
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return vm_address;
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uint64_t vm_address;
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address cpu_address = mbuf_.reserve(size, &vm_address);
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// Update memory with new CB data
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memcpy(cpu_address, sysmem, size);
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return vm_address;
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}
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// ================================================================================================
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@@ -30,9 +30,6 @@ class ManagedBuffer : public amd::EmbeddedObject {
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address reserve(uint32_t size, //!< real data size for upload
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uint64_t* gpu_address);
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//! Reserves memory at the top of the active buffer
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Memory& reserveAtTheTop(uint32_t size);
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//! Returns CB size
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uint32_t size() const { return size_; }
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@@ -40,14 +37,23 @@ class ManagedBuffer : public amd::EmbeddedObject {
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uint32_t wrtOffset() const { return wrtOffset_; }
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//! Returns active GPU buffer
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Memory* activeMemory() const { return buffers_[activeBuffer_]; }
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Memory* activeMemory() const { return pool_[activeBuffer_].buf; }
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uint64_t vmAddress() const { return buffers_[activeBuffer_]->vmAddress(); }
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//! Retruns VM address for the active buffer
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uint64_t vmAddress() const { return pool_[activeBuffer_].buf->vmAddress(); }
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//! Update the timestamp for the HW operation
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void pinGpuEvent();
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//! Returns VirtualGPU object this managed resource associated
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VirtualGPU& gpu() const { return gpu_; }
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private:
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struct TimeStampedBuffer {
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Memory* buf;
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GpuEvent events[AllEngines];
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};
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//! The maximum number of the managed buffers
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static constexpr uint32_t MaxNumberOfBuffers = 3;
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@@ -58,7 +64,7 @@ class ManagedBuffer : public amd::EmbeddedObject {
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ManagedBuffer& operator=(const ManagedBuffer&) = delete;
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VirtualGPU& gpu_; //!< Virtual GPU object
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std::vector<Memory*> buffers_; //!< Buffers for management
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std::vector<TimeStampedBuffer> pool_; //!< Buffers for management
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uint32_t activeBuffer_; //!< Current active buffer
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uint32_t size_; //!< Constant buffer size
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uint32_t wrtOffset_; //!< Current write offset
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@@ -145,6 +145,7 @@ class Memory : public device::Memory, public Resource {
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//! Quick view update for managed buffers. It should avoid expensive object allocations
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void updateView(Resource* view, size_t offset, size_t size) {
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size_ = size;
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flags_ |= HostMemoryDirectAccess;
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Resource::updateView(view, offset, size);
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}
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@@ -378,6 +378,7 @@ class Resource : public amd::HeapObject {
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memRef_->retain();
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desc_.width_ = amd::alignUp(size, Pal::Formats::BytesPerPixel(Pal::ChNumFormat::X32_Uint)) /
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Pal::Formats::BytesPerPixel(Pal::ChNumFormat::X32_Uint);
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setBusy(*memRef()->gpu_, GpuEvent::InvalidID);
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}
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}
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