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Add support for gfx909 and gfx90c

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Change-Id: I88158789cdda44a173e3ca26d2c96b8e0ea0e221


[ROCm/ROCR-Runtime commit: a97c14abea]
This commit is contained in:
Tony Tye
2021-04-08 16:55:07 +00:00
parent 2b25548eb0
commit e20cccb6e4
9 changed files with 44 additions and 18 deletions
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projects/rocr-runtime/rocrtst/suites/test_common/CMakeLists.txt
+2 -2
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@@ -54,7 +54,7 @@ set ( CPACK_DEBIAN_PACKAGE_HOMEPAGE "https://github.com/RadeonOpenCompute/ROCR-R
set ( CPACK_PACKAGE_HOMEPAGE_URL "https://github.com/RadeonOpenCompute/ROCR-Runtime" )
set(DEFAULT_TARGETS "gfx700;gfx701;gfx702;gfx801;gfx802;gfx803;gfx805;gfx810;gfx900;gfx902;gfx904;gfx906;gfx908;gfx90a;gfx1010;gfx1011;gfx1012;gfx1030;gfx1031;gfx1032;gfx1033")
set(DEFAULT_TARGETS "gfx700;gfx701;gfx702;gfx801;gfx802;gfx803;gfx805;gfx810;gfx900;gfx902;gfx904;gfx906;gfx908;gfx909;gfx90a;gfx90c;gfx1010;gfx1011;gfx1012;gfx1030;gfx1031;gfx1032;gfx1033")
#
# Currently support for Windows platform is not present
@@ -250,7 +250,7 @@ set(ROCRTST_LIBS ${ROCRTST_LIBS} hsa-runtime64::hsa-runtime64)
set(ROCRTST_LIBS ${ROCRTST_LIBS} rocm_smi${ONLY64STR})
# Set Name for rocrtst
# Set Name for rocrtst
MESSAGE(${ROCRTST_LIBS})
set(ROCRTST "rocrtst${ONLY64STR}")
projects/rocr-runtime/runtime/hsa-runtime/core/runtime/hsa.cpp
+6 -2
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@@ -1894,9 +1894,13 @@ static std::string ConvertOldTargetNameToNew(
NewName = "amdgcn-amd-amdhsa--gfx906";
xnack_supported = true;
}
else if (OldName == "AMD:AMDGPU:9:0:12") {
NewName = "amdgcn-amd-amdhsa--gfx90c";
xnack_supported = true;
}
else {
// Code object v2 only supports asics up to gfx906. Do NOT add handling
// of new asics into this if-else-if* block.
// Code object v2 only supports asics up to gfx906 plus gfx90c. Do NOT add
// handling of new asics into this if-else-if* block.
return "";
}
projects/rocr-runtime/runtime/hsa-runtime/core/runtime/isa.cpp
+6
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@@ -281,6 +281,9 @@ constexpr size_t hsa_name_size = 63;
ISAREG_ENTRY_GEN("gfx908:sramecc-:xnack+", 9, 0, 8, disabled, enabled)
ISAREG_ENTRY_GEN("gfx908:sramecc+:xnack-", 9, 0, 8, enabled, disabled)
ISAREG_ENTRY_GEN("gfx908:sramecc+:xnack+", 9, 0, 8, enabled, enabled)
ISAREG_ENTRY_GEN("gfx909", 9, 0, 9, unsupported, any)
ISAREG_ENTRY_GEN("gfx909:xnack-", 9, 0, 9, unsupported, disabled)
ISAREG_ENTRY_GEN("gfx909:xnack+", 9, 0, 9, unsupported, enabled)
ISAREG_ENTRY_GEN("gfx90a", 9, 0, 10, any, any)
ISAREG_ENTRY_GEN("gfx90a:xnack-", 9, 0, 10, any, disabled)
ISAREG_ENTRY_GEN("gfx90a:xnack+", 9, 0, 10, any, enabled)
@@ -290,6 +293,9 @@ constexpr size_t hsa_name_size = 63;
ISAREG_ENTRY_GEN("gfx90a:sramecc-:xnack+", 9, 0, 10, disabled, enabled)
ISAREG_ENTRY_GEN("gfx90a:sramecc+:xnack-", 9, 0, 10, enabled, disabled)
ISAREG_ENTRY_GEN("gfx90a:sramecc+:xnack+", 9, 0, 10, enabled, enabled)
ISAREG_ENTRY_GEN("gfx90c", 9, 0, 12, unsupported, any)
ISAREG_ENTRY_GEN("gfx90c:xnack-", 9, 0, 12, unsupported, disabled)
ISAREG_ENTRY_GEN("gfx90c:xnack+", 9, 0, 12, unsupported, enabled)
ISAREG_ENTRY_GEN("gfx1010", 10, 1, 0, unsupported, any)
ISAREG_ENTRY_GEN("gfx1010:xnack-", 10, 1, 0, unsupported, disabled)
ISAREG_ENTRY_GEN("gfx1010:xnack+", 10, 1, 0, unsupported, enabled)
projects/rocr-runtime/runtime/hsa-runtime/image/blit_kernel.cpp
+7 -1
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@@ -82,7 +82,9 @@ extern uint8_t ocl_blit_object_gfx902[];
extern uint8_t ocl_blit_object_gfx904[];
extern uint8_t ocl_blit_object_gfx906[];
extern uint8_t ocl_blit_object_gfx908[];
extern uint8_t ocl_blit_object_gfx909[];
extern uint8_t ocl_blit_object_gfx90a[];
extern uint8_t ocl_blit_object_gfx90c[];
extern uint8_t ocl_blit_object_gfx1010[];
extern uint8_t ocl_blit_object_gfx1011[];
extern uint8_t ocl_blit_object_gfx1012[];
@@ -862,7 +864,7 @@ hsa_status_t BlitKernel::ConvertImage(const Image& original_image,
(current_type == HSA_EXT_IMAGE_CHANNEL_TYPE_UNORM_SHORT_101010)) {
converted_order = HSA_EXT_IMAGE_CHANNEL_ORDER_R;
}
// For internal book keeping, depth isn't a HW type.
const hsa_ext_image_geometry_t current_geometry =
original_image.desc.geometry;
@@ -991,8 +993,12 @@ hsa_status_t BlitKernel::GetPatchedBlitObject(const char* agent_name,
*blit_code_object = ocl_blit_object_gfx906;
} else if (sname == "gfx908") {
*blit_code_object = ocl_blit_object_gfx908;
} else if (sname == "gfx909") {
*blit_code_object = ocl_blit_object_gfx909;
} else if (sname == "gfx90a") {
*blit_code_object = ocl_blit_object_gfx90a;
} else if (sname == "gfx90c") {
*blit_code_object = ocl_blit_object_gfx90c;
} else if (sname == "gfx1010") {
*blit_code_object = ocl_blit_object_gfx1010;
} else if (sname == "gfx1011") {
projects/rocr-runtime/runtime/hsa-runtime/image/blit_src/CMakeLists.txt
+1 -1
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@@ -69,7 +69,7 @@ endif()
# Determine the target devices if not specified
if (NOT DEFINED TARGET_DEVICES)
set (TARGET_DEVICES "gfx700;gfx701;gfx702;gfx801;gfx802;gfx803;gfx805;gfx810;gfx900;gfx902;gfx904;gfx906;gfx908;gfx90a;gfx1010;gfx1011;gfx1012;gfx1030;gfx1031;gfx1032;gfx1033")
set (TARGET_DEVICES "gfx700;gfx701;gfx702;gfx801;gfx802;gfx803;gfx805;gfx810;gfx900;gfx902;gfx904;gfx906;gfx908;gfx909;gfx90a;gfx90c;gfx1010;gfx1011;gfx1012;gfx1030;gfx1031;gfx1032;gfx1033")
endif()
set( TARGET_DEVICES ${TARGET_DEVICES} CACHE STRING "Build targets" FORCE )
projects/rocr-runtime/runtime/hsa-runtime/inc/amd_hsa_elf.h
+10 -8
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@@ -2,24 +2,24 @@
//
// The University of Illinois/NCSA
// Open Source License (NCSA)
//
//
// Copyright (c) 2014-2020, Advanced Micro Devices, Inc. All rights reserved.
//
//
// Developed by:
//
//
// AMD Research and AMD HSA Software Development
//
//
// Advanced Micro Devices, Inc.
//
//
// www.amd.com
//
//
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to
// deal with the Software without restriction, including without limitation
// the rights to use, copy, modify, merge, publish, distribute, sublicense,
// and/or sell copies of the Software, and to permit persons to whom the
// Software is furnished to do so, subject to the following conditions:
//
//
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimers.
// - Redistributions in binary form must reproduce the above copyright
@@ -29,7 +29,7 @@
// nor the names of its contributors may be used to endorse or promote
// products derived from this Software without specific prior written
// permission.
//
//
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
@@ -118,6 +118,8 @@ enum : unsigned {
EF_AMDGPU_MACH_AMDGCN_RESERVED_0X3D = 0x03d,
EF_AMDGPU_MACH_AMDGCN_RESERVED_0X3E = 0x03e,
EF_AMDGPU_MACH_AMDGCN_GFX90A = 0x03f,
EF_AMDGPU_MACH_AMDGCN_RESERVED_0X40 = 0x040,
EF_AMDGPU_MACH_AMDGCN_RESERVED_0X41 = 0x041,
// First/last AMDGCN-based processors.
EF_AMDGPU_MACH_AMDGCN_FIRST = EF_AMDGPU_MACH_AMDGCN_GFX600,
projects/rocr-runtime/runtime/hsa-runtime/libamdhsacode/amd_hsa_code.cpp
+4 -2
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@@ -623,9 +623,11 @@ namespace code {
mach = ELF::EF_AMDGPU_MACH_AMDGCN_GFX904;
else if (old_name == "AMD:AMDGPU:9:0:6" || old_name == "AMD:AMDGPU:9:0:7")
mach = ELF::EF_AMDGPU_MACH_AMDGCN_GFX906;
else if (old_name == "AMD:AMDGPU:9:0:12")
mach = ELF::EF_AMDGPU_MACH_AMDGCN_GFX90C;
else {
// Code object v2 only supports asics up to gfx906. Do NOT add handling
// of new asics into this if-else-if* block.
// Code object v2 only supports asics up to gfx906 plus gfx90c. Do NOT
// add handling of new asics into this if-else-if* block.
return "";
}
std::string name;
projects/rocr-runtime/runtime/hsa-runtime/loader/loaders.cpp
+7 -1
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@@ -93,7 +93,9 @@ namespace loader {
gfx904.handle = 0x904;
gfx906.handle = 0x906;
gfx908.handle = 0x908;
gfx909.handle = 0x909;
gfx90a.handle = 0x90a;
gfx90c.handle = 0x90c;
gfx1010.handle = 0x1010;
gfx1011.handle = 0x1011;
gfx1012.handle = 0x1012;
@@ -138,8 +140,12 @@ namespace loader {
return gfx906;
} else if (sname == "AMD:AMDGPU:9:0:8") {
return gfx908;
} else if (sname == "AMD:AMDGPU:9:0:A") {
} else if (sname == "AMD:AMDGPU:9:0:9") {
return gfx909;
} else if (sname == "AMD:AMDGPU:9:0:10") {
return gfx90a;
} else if (sname == "AMD:AMDGPU:9:0:12") {
return gfx90c;
} else if (sname == "AMD:AMDGPU:10:1:0") {
return gfx1010;
} else if (sname == "AMD:AMDGPU:10:1:1") {
projects/rocr-runtime/runtime/hsa-runtime/loader/loaders.hpp
+1 -1
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@@ -57,7 +57,7 @@ namespace loader {
hsa_isa_t invalid;
hsa_isa_t gfx700, gfx701, gfx702, gfx703, gfx704, gfx705;
hsa_isa_t gfx801, gfx802, gfx803, gfx805, gfx810;
hsa_isa_t gfx900, gfx902, gfx904, gfx906, gfx908, gfx90a;
hsa_isa_t gfx900, gfx902, gfx904, gfx906, gfx908, gfx909, gfx90a, gfx90c;
hsa_isa_t gfx1010, gfx1011, gfx1012, gfx1030, gfx1031, gfx1032, gfx1033;
std::ostream& out;
typedef std::set<void*> PointerSet;