P4 to Git Change 1332913 by gandryey@gera-w8 on 2016/10/27 16:30:43
SWDEV-95912 - OpenCL on PAL - RT Compute - Check for the queue properties before requesting the exclusive queues. Affected files ... ... //depot/stg/opencl/drivers/opencl/runtime/device/pal/paldevice.cpp#29 edit ... //depot/stg/opencl/drivers/opencl/runtime/device/pal/paldevice.hpp#12 edit
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@@ -183,7 +183,7 @@ NullDevice::create(Pal::AsicRevision asicRevision, Pal::GfxIpLevel ipLevel)
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}
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// Fill the device info structure
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fillDeviceInfo(properties, heaps, 4096, 1);
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fillDeviceInfo(properties, heaps, 4096, 1, 0);
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// Runtime doesn't know what local size could be on the real board
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info_.maxGlobalVariableSize_ = static_cast<size_t>(512 * Mi);
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@@ -212,7 +212,8 @@ void NullDevice::fillDeviceInfo(
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const Pal::DeviceProperties& palProp,
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const Pal::GpuMemoryHeapProperties heaps[Pal::GpuHeapCount],
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size_t maxTextureSize,
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uint numComputeRings)
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uint numComputeRings,
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uint numExclusiveComputeRings)
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{
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info_.type_ = CL_DEVICE_TYPE_GPU;
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info_.vendorId_ = palProp.vendorId;
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@@ -476,8 +477,7 @@ void NullDevice::fillDeviceInfo(
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info_.localMemBanks_ = hwInfo()->localMemBanks_;
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info_.gfxipVersion_ = hwInfo()->gfxipVersion_;
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info_.numAsyncQueues_ = numComputeRings;
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info_.numRTQueues_ =
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palProp.engineProperties[Pal::EngineTypeExclusiveCompute].engineCount - 1;
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info_.numRTQueues_ = numExclusiveComputeRings;
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info_.numRTCUs_ =
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palProp.engineProperties[Pal::EngineTypeExclusiveCompute].maxNumDedicatedCu;
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info_.threadTraceEnable_ = settings().threadTraceEnable_;
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@@ -615,6 +615,7 @@ Device::Device()
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, mapCache_(nullptr)
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, resourceCache_(nullptr)
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, numComputeEngines_(0)
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, numExclusiveComputeEngines_(0)
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, numDmaEngines_(0)
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, heapInitComplete_(false)
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, xferQueue_(nullptr)
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@@ -708,6 +709,18 @@ Device::create(Pal::IDevice* device)
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// Find the number of available engines
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numComputeEngines_ =
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properties().engineProperties[Pal::EngineTypeCompute].engineCount;
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if (properties().engineProperties[Pal::EngineTypeExclusiveCompute].
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maxNumDedicatedCu > 0) {
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for (uint i = 0; i < properties().engineProperties[
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Pal::EngineTypeExclusiveCompute].engineCount; ++i) {
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if (properties().engineProperties[
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Pal::EngineTypeExclusiveCompute].capabilities[i].rtCuHighCompute ||
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properties().engineProperties[
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Pal::EngineTypeExclusiveCompute].capabilities[i].rtCuMedCompute) {
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numExclusiveComputeEngines_++;
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}
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}
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}
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numDmaEngines_ =
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properties().engineProperties[Pal::EngineTypeDma].engineCount;
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@@ -730,12 +743,16 @@ Device::create(Pal::IDevice* device)
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finalizeInfo.requestedEngineCounts[Pal::EngineTypeCompute].engines =
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((1 << numComputeEngines_) - 1);
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// Request real time compute engines
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finalizeInfo.requestedEngineCounts[Pal::EngineTypeExclusiveCompute].engines = 3;
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finalizeInfo.requestedEngineCounts[Pal::EngineTypeExclusiveCompute].engines =
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((1 << numExclusiveComputeEngines_) - 1);
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// Request all SDMA engines
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finalizeInfo.requestedEngineCounts[Pal::EngineTypeDma].engines =
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(1 << numDmaEngines_) - 1;
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result = iDev()->Finalize(finalizeInfo);
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if (result != Pal::Result::Success) {
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return false;
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}
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}
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Pal::GpuMemoryHeapProperties heaps[Pal::GpuHeapCount];
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@@ -806,7 +823,7 @@ Device::create(Pal::IDevice* device)
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}
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// Fill the device info structure
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fillDeviceInfo(properties(), heaps, 16*Ki, numComputeEngines());
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fillDeviceInfo(properties(), heaps, 16*Ki, numComputeEngines(), numExclusiveComputeEngines());
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#ifdef DEBUG
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std::stringstream message;
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@@ -122,7 +122,8 @@ protected:
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const Pal::DeviceProperties& palProp,//!< PAL device properties
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const Pal::GpuMemoryHeapProperties heaps[Pal::GpuHeapCount],
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size_t maxTextureSize, //!< Maximum texture size supported in HW
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uint numComputeRings //!< Number of compute rings
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uint numComputeRings, //!< Number of compute rings
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uint numExclusiveComputeRings //!< Number of exclusive compute rings
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);
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};
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@@ -412,6 +413,9 @@ public:
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//! Returns the number of available compute rings
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uint numComputeEngines() const { return numComputeEngines_; }
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//! Returns the number of available compute rings
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uint numExclusiveComputeEngines() const { return numExclusiveComputeEngines_; }
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//! Returns the number of available DMA engines
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uint numDMAEngines() const { return numDmaEngines_; }
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@@ -548,6 +552,7 @@ private:
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std::vector<amd::Memory*>* mapCache_; //!< Map cache info structure
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ResourceCache* resourceCache_; //!< Resource cache
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uint numComputeEngines_; //!< The number of available compute engines
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uint numExclusiveComputeEngines_; //!< The number of available compute engines
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uint numDmaEngines_; //!< The number of available compute engines
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bool heapInitComplete_; //!< Keep track of initialization status of heap resources
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VirtualGPU* xferQueue_; //!< Transfer queue
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