P4 to Git Change 1727059 by asalmanp@asalmanp-ocl-stg on 2019/01/07 17:48:44

SWDEV-132899 - [OCL][GFX10] report number of WGP by default on gfx10 ASICs
	Both HSAIL/SC and LC compilers use WGP mode by default on gfx10 ASICs (i.e., COMPUTE_PGM_RSRC1.WGP_MODE is set to 1 by both compilers) therefore runtime should report number of WGP (i.e., CU/2) on gfx10 ASICs by default.
	The new environment variable (GPU_ENABLE_WGP_MODE = 0)  can be used to force CU mode on LC (i.e., -mcumode option) if it’s needed (HSAIL/SC doesn't have any compiler option for forcing the CU mode)

	Also, using the new environment variable (GPU_ENABLE_WAVE32_MODE) to control the wave32 mode on gfx10+.

	ReviewRequestURL = http://ocltc.amd.com/reviews/r/16435/diff/

Affected files ...

... //depot/stg/opencl/drivers/opencl/runtime/device/device.hpp#329 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/devprogram.cpp#27 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/pal/paldevice.cpp#121 edit
... //depot/stg/opencl/drivers/opencl/runtime/device/pal/palsettings.cpp#65 edit
... //depot/stg/opencl/drivers/opencl/runtime/utils/flags.hpp#301 edit

rocclr/runtime/utils/flags.hpp

@@ -169,8 +169,8 @@ release_on_stg(bool, PAL_DISABLE_SDMA, false,                                 \
         "1 = Disable SDMA for PAL")                                           \
 release(uint, PAL_RGP_DISP_COUNT, 50,                                         \
         "The number of dispatches for RGP capture with SQTT")                 \
-release(bool, GPU_FORCE_WAVE_SIZE_32, false,                                  \
-        "Forces WaveSize32 compilation in SC")                                \
+release(bool, GPU_ENABLE_WAVE32_MODE, true,                                   \
+        "Enables Wave32 compilation in HW if available")                                         \
 release(bool, GPU_ENABLE_LC, IS_LIGHTNING,                                    \
         "Enables LC path")                                                    \
 release(uint, GPU_MAX_COMMAND_BUFFERS, 8,                                     \
@@ -179,6 +179,8 @@ release(cstring, HIP_VISIBLE_DEVICES, "",
         "Only devices whose index is present in the sequence are visible to HIP")    \
 release(cstring, CUDA_VISIBLE_DEVICES, "",                                            \
         "Only devices whose index is present in the sequence are visible to HIP")    \
+release(bool, GPU_ENABLE_WGP_MODE, true,                                  \
+        "Enables WGP Mode in HW if available")                                      \
 
 namespace amd {