Expose HDP flush registers.

Exposed via agent info query.  Only valid if fine grain PCIe memory is enabled.

Change-Id: Ib4770901592ec047276458926a947737f9b93bb5


[ROCm/ROCR-Runtime commit: 06376e726b]

projects/rocr-runtime/runtime/hsa-runtime/core/inc/amd_gpu_agent.h

@@ -461,6 +461,9 @@ class GpuAgent : public GpuAgentInt {
   // @brief The GPU memory maximum frequency in MHz.
   uint32_t memory_max_frequency_;
 
+  // @brief HDP flush registers
+  hsa_amd_hdp_flush_t HDP_flush_ = {nullptr, nullptr};
+
  private:
   // @brief Query the driver to get the region list owned by this agent.
   void InitRegionList();

projects/rocr-runtime/runtime/hsa-runtime/core/runtime/amd_cpu_agent.cpp

@@ -353,6 +353,9 @@ hsa_status_t CpuAgent::GetInfo(hsa_agent_info_t attribute, void* value) const {
     case HSA_AMD_AGENT_INFO_NUM_SHADER_ARRAYS_PER_SE:
       *((uint32_t*)value) = properties_.NumArrays;
       break;
+    case HSA_AMD_AGENT_INFO_HDP_FLUSH:
+      *((hsa_amd_hdp_flush_t*)value) = {nullptr, nullptr};
+      break;
     default:
       return HSA_STATUS_ERROR_INVALID_ARGUMENT;
       break;

projects/rocr-runtime/runtime/hsa-runtime/core/runtime/amd_gpu_agent.cpp

@@ -316,6 +316,13 @@ void GpuAgent::InitRegionList() {
             memory_max_frequency_ = mem_props[mem_idx].MemoryClockMax;
           }
           break;
+        case HSA_HEAPTYPE_MMIO_REMAP:
+          if (core::Runtime::runtime_singleton_->flag().fine_grain_pcie()) {
+            // Remap offsets defined in kfd_ioctl.h
+            HDP_flush_.HDP_MEM_FLUSH_CNTL = (uint32_t*)mem_props[mem_idx].VirtualBaseAddress;
+            HDP_flush_.HDP_REG_FLUSH_CNTL = HDP_flush_.HDP_MEM_FLUSH_CNTL + 1;
+          }
+          break;
         default:
           continue;
       }
@@ -890,6 +897,9 @@ hsa_status_t GpuAgent::GetInfo(hsa_agent_info_t attribute, void* value) const {
     case HSA_AMD_AGENT_INFO_NUM_SHADER_ARRAYS_PER_SE:
       *((uint32_t*)value) = properties_.NumArrays;
       break;
+    case HSA_AMD_AGENT_INFO_HDP_FLUSH:
+      *((hsa_amd_hdp_flush_t*)value) = HDP_flush_;
+      break;
     default:
       return HSA_STATUS_ERROR_INVALID_ARGUMENT;
       break;

projects/rocr-runtime/runtime/hsa-runtime/core/runtime/hsa_ext_amd.cpp

@@ -961,6 +961,7 @@ hsa_status_t HSA_API hsa_amd_queue_set_priority(hsa_queue_t* queue,
   CATCH;
 }
 
+// For use by tools only - not in library export table.
 hsa_status_t hsa_amd_runtime_queue_create_register(hsa_amd_runtime_queue_notifier callback,
                                                    void* user_data) {
   TRY;

projects/rocr-runtime/runtime/hsa-runtime/inc/hsa_ext_amd.h

@@ -136,9 +136,20 @@ typedef enum hsa_amd_agent_info_s {
    * Number of Shader Arrays Per Shader Engines in Gpu
    * The type of this attribute is uint32_t.
    */
-  HSA_AMD_AGENT_INFO_NUM_SHADER_ARRAYS_PER_SE = 0xA00D
+  HSA_AMD_AGENT_INFO_NUM_SHADER_ARRAYS_PER_SE = 0xA00D,
+  /**
+   * Address of the HDP flush registers.  Use of these registers does not conform to the HSA memory
+   * model and should be treated with caution.
+   * The type of this attribute is hsa_amd_hdp_flush_t.
+   */
+  HSA_AMD_AGENT_INFO_HDP_FLUSH = 0xA00E
 } hsa_amd_agent_info_t;
 
+typedef struct hsa_amd_hdp_flush_s {
+  uint32_t* HDP_MEM_FLUSH_CNTL;
+  uint32_t* HDP_REG_FLUSH_CNTL;
+} hsa_amd_hdp_flush_t;
+
 /**
  * @brief Region attributes.
  */