Adding queue information queries

New hsa_amd_queue_get_info API to support: - HSA_AMD_QUEUE_INFO_AGENT: Agent that owns the underlying HW queue - HSA_AMD_QUEUE_INFO_DOORBELL_ID: KFD doorbell ID of the queue completion signal. Change-Id: I98842131bcbdd08552649791a5d43e578a615808 [ROCm/ROCR-Runtime commit: d6d5786051]
2023-12-08 00:14:12 +00:00
@@ -1298,6 +1298,11 @@ hsa_status_t HSA_API hsa_amd_agent_set_async_scratch_limit(hsa_agent_t agent, si
  return amdExtTable->hsa_amd_agent_set_async_scratch_limit_fn(agent, threshold);
 }

+hsa_status_t HSA_API hsa_amd_queue_get_info(hsa_queue_t* queue,
+                                            hsa_queue_info_attribute_t attribute, void* value) {
+  return amdExtTable->hsa_amd_queue_get_info_fn(queue, attribute, value);
+}
+
 // Tools only table interfaces.
 namespace rocr {

@@ -211,6 +211,9 @@ class AqlQueue : public core::Queue, private core::LocalSignal, public core::Doo
  /// @brief Update signal value using Release semantics
  void StoreRelease(hsa_signal_value_t value) override;

+  /// @brief Provide information about the queue
+  hsa_status_t GetInfo(hsa_queue_info_attribute_t attribute, void* value) override;
+
  /// @brief Enable use of GWS from this queue.
  hsa_status_t EnableGWS(int gws_slot_count);

@@ -159,6 +159,11 @@ class HostQueue : public Queue {
    assert(false && "HostQueue::ExecutePM4 is unimplemented");
  }

+  hsa_status_t GetInfo(hsa_queue_info_attribute_t attribute, void* value) override {
+    assert(false && "HostQueue::GetInfo is unimplemented");
+    return HSA_STATUS_ERROR_INVALID_QUEUE;
+  }
+
  void* operator new(size_t size) {
    return _aligned_malloc(size, HSA_QUEUE_ALIGN_BYTES);
  }
@@ -349,6 +349,10 @@ hsa_status_t hsa_amd_vmem_get_alloc_properties_from_handle(hsa_amd_vmem_alloc_ha
 // Mirrors Amd Extension Apis
 hsa_status_t HSA_API hsa_amd_agent_set_async_scratch_limit(hsa_agent_t agent, size_t threshold);

+// Mirrors Amd Extension Apis
+hsa_status_t hsa_amd_queue_get_info(hsa_queue_t* queue, hsa_queue_info_attribute_t attribute,
+                                    void* value);
+
 }  // namespace amd
 }  // namespace rocr

@@ -269,6 +269,9 @@ class InterceptQueue : public QueueProxy, private LocalSignal, public DoorbellSi
    StoreRelaxed(value);
  }

+  /// @brief Provide information about the queue
+  hsa_status_t GetInfo(hsa_queue_info_attribute_t attribute, void* value) override;
+
  static __forceinline bool IsType(core::Signal* signal) { return signal->IsType(&rtti_id_); }
  static __forceinline bool IsType(core::Queue* queue) { return queue->IsType(&rtti_id_); }

@@ -52,7 +52,7 @@
 #include "core/inc/memory_region.h"
 #include "core/util/utils.h"
 #include "inc/amd_hsa_queue.h"
-
+#include "inc/hsa_ext_amd.h"
 #include "hsakmt/hsakmt.h"

 namespace rocr {
@@ -370,6 +370,9 @@ class Queue : public Checked<0xFA3906A679F9DB49>, private LocalQueue {
                     (enabled != 0));
  }

+  /// @ brief Returns queue queries about the queue
+  virtual hsa_status_t GetInfo(hsa_queue_info_attribute_t attribute, void* value) = 0;
+
  /// @ brief Reports async queue errors to stderr if no other error handler was registered.
  static void DefaultErrorHandler(hsa_status_t status, hsa_queue_t* source, void* data);

@@ -535,6 +535,25 @@ void AqlQueue::StoreRelease(hsa_signal_value_t value) {
  StoreRelaxed(value);
 }

+hsa_status_t AqlQueue::GetInfo(hsa_queue_info_attribute_t attribute, void* value) {
+  switch (attribute) {
+    case HSA_AMD_QUEUE_INFO_AGENT:
+      *(reinterpret_cast<hsa_agent_t*>(value)) = agent_->public_handle();
+      break;
+    case HSA_AMD_QUEUE_INFO_DOORBELL_ID:
+      if (doorbell_type_ == 2)
+        // Hardware doorbell supports AQL semantics.
+        *(reinterpret_cast<uint64_t*>(value)) =
+            reinterpret_cast<uint64_t>(signal_.hardware_doorbell_ptr);
+      else
+        return HSA_STATUS_ERROR_INVALID_QUEUE;
+      break;
+    default:
+      return HSA_STATUS_ERROR_INVALID_ARGUMENT;
+  }
+  return HSA_STATUS_SUCCESS;
+}
+
 uint32_t AqlQueue::ComputeRingBufferMinPkts() {
  // From CP_HQD_PQ_CONTROL.QUEUE_SIZE specification:
  //   Size of the primary queue (PQ) will be: 2^(HQD_QUEUE_SIZE+1) DWs.
@@ -80,7 +80,7 @@ void HsaApiTable::Init() {
  // they can add preprocessor macros on the new functions

  constexpr size_t expected_core_api_table_size = 1016;
-  constexpr size_t expected_amd_ext_table_size = 560;
+  constexpr size_t expected_amd_ext_table_size = 568;
  constexpr size_t expected_image_ext_table_size = 120;
  constexpr size_t expected_finalizer_ext_table_size = 64;
  constexpr size_t expected_tools_table_size = 64;
@@ -464,6 +464,7 @@ void HsaApiTable::UpdateAmdExts() {
  amd_ext_api.hsa_amd_vmem_get_alloc_properties_from_handle_fn =
      AMD::hsa_amd_vmem_get_alloc_properties_from_handle;
  amd_ext_api.hsa_amd_agent_set_async_scratch_limit_fn = AMD::hsa_amd_agent_set_async_scratch_limit;
+  amd_ext_api.hsa_amd_queue_get_info_fn = AMD::hsa_amd_queue_get_info;
 }

 void HsaApiTable::UpdateTools() {
@@ -1388,5 +1388,17 @@ hsa_status_t HSA_API hsa_amd_agent_set_async_scratch_limit(hsa_agent_t _agent, s
  CATCH;
 }

+hsa_status_t HSA_API hsa_amd_queue_get_info(hsa_queue_t* _queue,
+                                            hsa_queue_info_attribute_t attribute, void* value) {
+  TRY;
+  IS_OPEN();
+
+  core::Queue* queue = core::Queue::Convert(_queue);
+  IS_VALID(queue);
+
+  return queue->GetInfo(attribute, value);
+  CATCH;
+}
+
 }   //  namespace amd
 }   //  namespace rocr
@@ -41,6 +41,7 @@
 ////////////////////////////////////////////////////////////////////////////////

 #include "core/inc/intercept_queue.h"
+#include "core/inc/amd_aql_queue.h"
 #include "core/util/utils.h"
 #include "inc/hsa_api_trace.h"

@@ -386,5 +387,18 @@ void InterceptQueue::StoreRelaxed(hsa_signal_value_t value) {
  atomic::Store(&amd_queue_.read_dispatch_id, next_packet_, std::memory_order_release);
 }

+hsa_status_t InterceptQueue::GetInfo(hsa_queue_info_attribute_t attribute, void* value) {
+  switch (attribute) {
+    case HSA_AMD_QUEUE_INFO_AGENT:
+    case HSA_AMD_QUEUE_INFO_DOORBELL_ID: {
+      if (!AMD::AqlQueue::IsType(wrapped.get())) return HSA_STATUS_ERROR_INVALID_QUEUE;
+
+      AMD::AqlQueue* aqlQueue = static_cast<AMD::AqlQueue*>(wrapped.get());
+      return aqlQueue->GetInfo(attribute, value);
+    }
+  }
+  return HSA_STATUS_ERROR_INVALID_ARGUMENT;
+}
+
 }  // namespace core
 }  // namespace rocr
@@ -259,7 +259,7 @@ global:
 	hsa_ven_amd_pcs_start;
 	hsa_ven_amd_pcs_stop;
 	hsa_ven_amd_pcs_flush;
-
+	hsa_amd_queue_get_info;
 local:
    *;
 };
@@ -263,6 +263,7 @@ struct AmdExtTable {
  decltype(hsa_amd_vmem_get_alloc_properties_from_handle)*
      hsa_amd_vmem_get_alloc_properties_from_handle_fn;
  decltype(hsa_amd_agent_set_async_scratch_limit)* hsa_amd_agent_set_async_scratch_limit_fn;
+  decltype(hsa_amd_queue_get_info)* hsa_amd_queue_get_info_fn;
 };

 // Table to export HSA Core Runtime Apis
@@ -58,7 +58,7 @@
 // Step Ids of the Api tables exported by Hsa Core Runtime
 #define HSA_API_TABLE_STEP_VERSION                  0x01
 #define HSA_CORE_API_TABLE_STEP_VERSION             0x00
-#define HSA_AMD_EXT_API_TABLE_STEP_VERSION          0x01
+#define HSA_AMD_EXT_API_TABLE_STEP_VERSION          0x02
 #define HSA_FINALIZER_API_TABLE_STEP_VERSION        0x00
 #define HSA_IMAGE_API_TABLE_STEP_VERSION            0x00
 #define HSA_AQLPROFILE_API_TABLE_STEP_VERSION       0x00
@@ -3090,6 +3090,22 @@ hsa_status_t hsa_amd_vmem_get_alloc_properties_from_handle(
 */
 hsa_status_t HSA_API hsa_amd_agent_set_async_scratch_limit(hsa_agent_t agent, size_t threshold);

+typedef enum {
+  /*
+   * Returns the agent that owns the underlying HW queue.
+   * The type of this attribute is hsa_agent_t.
+   */
+  HSA_AMD_QUEUE_INFO_AGENT,
+  /*
+   * Returns the doorbell ID of the completion signal of the queue
+   * The type of this attribute is uint64_t.
+   */
+  HSA_AMD_QUEUE_INFO_DOORBELL_ID,
+} hsa_queue_info_attribute_t;
+
+hsa_status_t hsa_amd_queue_get_info(hsa_queue_t* queue, hsa_queue_info_attribute_t attribute,
+                                    void* value);
+
 #ifdef __cplusplus
 }  // end extern "C" block
 #endif