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Adding GFXIP and kernel code object

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Change-Id: Ieb2dfea8d9e909efac583f541730d77b7d0c9679


[ROCm/ROCR-Runtime commit: da831502ab]
Этот коммит содержится в:
Evgeny
2017-06-12 17:06:52 -05:00
родитель 79a238eb78
Коммит f17287cec4
35 изменённых файлов: 345744 добавлений и 0 удалений
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projects/rocr-runtime/runtime/hsa-ext-aql-profile/gfxip/gfx8/features_bonaire.h
+1594
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projects/rocr-runtime/runtime/hsa-ext-aql-profile/gfxip/gfx8/features_hainan.h
+954
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@@ -0,0 +1,954 @@
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#define hainan____GPU_FEATURES_H__
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#define hainan__GPU__BIF__CLKBUF_PRESENT 1
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#define hainan__GPU__CHIP__TECHVER B .0.0
#define hainan__GPU__CHIP__TECHVER__B_0_0 1
#define hainan__TOOLS__GUTS__TECHNM tsmc28hp
#define hainan__TOOLS__GUTS__TECHNM__TSMC28HP 1
#define hainan__TOOLS__GUTS__MEMTECH 28nm
#define hainan__TOOLS__GUTS__MEMTECH__28NM 1
#define hainan__TOOLS__GUTS__LARRVENDOR AMD
#define hainan__TOOLS__GUTS__LARRVENDOR__AMD 1
#define hainan__TOOLS__GUTS__MEMFABTECH TSMC28
#define hainan__TOOLS__GUTS__MEMFABTECH__TSMC28 1
#define hainan__TOOLS__GUTS__MEMVENDOR Virage
#define hainan__TOOLS__GUTS__MEMVENDOR__VIRAGE 1
#define hainan__TOOLS__GUTS__MEMTYPE slow
#define hainan__TOOLS__GUTS__MEMTYPE__SLOW 1
#define hainan__TOOLS__GUTS__MEMVER 1_0
#define hainan__TOOLS__GUTS__MEMVER__1_0 1
#define hainan__TOOLS__GUTS__LARRTYPE default
#define hainan__TOOLS__GUTS__LARRTYPE__DEFAULT 1
#define hainan__TOOLS__GUTS__LARRVER 0_6han
#define hainan__TOOLS__GUTS__LARRVER__0_6HAN 1
#define hainan__TOOLS__GUTS__TECHVER B .0.0
#define hainan__TOOLS__GUTS__TECHVER__B_0_0 1
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#define hainan__GPU__CHIP__MEMTECH 28nm
#define hainan__GPU__CHIP__MEMTECH__28NM 1
#define hainan__GPU__CHIP__MEMVIEWVER 0_1
#define hainan__GPU__CHIP__MEMVIEWVER__0_1 1
#define hainan__GPU__CHIP__MEM virage
#define hainan__GPU__CHIP__MEM__VIRAGE 1
#define hainan__GPU__CHIP__MEMVENDOR Virage
#define hainan__GPU__CHIP__MEMVENDOR__VIRAGE 1
#define hainan__GPU__CHIP__SRAM_MEMFABTECH TSMC28
#define hainan__GPU__CHIP__SRAM_MEMFABTECH__TSMC28 1
#define hainan__GPU__CHIP__LARR_MEMWRAPPERVER 0_1
#define hainan__GPU__CHIP__LARR_MEMWRAPPERVER__0_1 1
#define hainan__GPU__CHIP__SRAM_MEMWRAPPERVER 0_1
#define hainan__GPU__CHIP__SRAM_MEMWRAPPERVER__0_1 1
#define hainan__GPU__CHIP__SRAM_TIMING slow
#define hainan__GPU__CHIP__SRAM_TIMING__SLOW 1
#define hainan__GPU__CHIP__SRAM_MEMVER 1_0_1
#define hainan__GPU__CHIP__SRAM_MEMVER__1_0_1 1
#define hainan__GPU__CHIP__LARRVENDOR AMD
#define hainan__GPU__CHIP__LARRVENDOR__AMD 1
#define hainan__GPU__CHIP__LARR_MEMFABTECH TSMC28
#define hainan__GPU__CHIP__LARR_MEMFABTECH__TSMC28 1
#define hainan__GPU__CHIP__LARR_TIMING default
#define hainan__GPU__CHIP__LARR_TIMING__DEFAULT 1
#define hainan__GPU__CHIP__LARR_MEMVER 0_6han
#define hainan__GPU__CHIP__LARR_MEMVER__0_6HAN 1
#define hainan__GPU__CHIP__MEMFABTECH TSMC28
#define hainan__GPU__CHIP__MEMFABTECH__TSMC28 1
#define hainan__GPU__CHIP__MEMVER 1_0
#define hainan__GPU__CHIP__MEMVER__1_0 1
#define hainan__GPU__CHIP__MEMTYPE slow
#define hainan__GPU__CHIP__MEMTYPE__SLOW 1
#define hainan__GPU__CHIP__LARRVER 0_6han
#define hainan__GPU__CHIP__LARRVER__0_6HAN 1
#define hainan__GPU__CHIP__LARRTYPE default
#define hainan__GPU__CHIP__LARRTYPE__DEFAULT 1
#define hainan__GPU__CHIP__TILES_PRESENT 0
#define hainan__GPU__CHIP__TILES_PRESENT__0 1
#define hainan__GPU__CHIP__SMSGCOUNT 2
#define hainan__GPU__CHIP__SMSGCOUNT__2 1
#define hainan__GPU__CHIP__SMSG_0_PRESENT 1
#define hainan__GPU__CHIP__SMSG_0_PRESENT__1 1
#define hainan__GPU__CHIP__SMSG_1_PRESENT 1
#define hainan__GPU__CHIP__SMSG_1_PRESENT__1 1
#define hainan__GPU__CHIP__SMSG_2_PRESENT 0
#define hainan__GPU__CHIP__SMSG_2_PRESENT__0 1
#define hainan__GPU__CHIP__SMSG_3_PRESENT 0
#define hainan__GPU__CHIP__SMSG_3_PRESENT__0 1
#define hainan__GPU__CHIP__SMSG_FOR_BL 1
#define hainan__GPU__CHIP__SMSG_FOR_BL__1 1
#define hainan__GPU__CHIP__SMSG_FOR_TR 0
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#define hainan__GPU__CHIP__TCB_DEPTH__512 1
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#define hainan__GPU__CHIP__XCLK_MHZ__25 1
#define hainan__GPU__LBIST__PRESENT 0
#define hainan__GPU__LBIST__PRESENT__0 1
#define hainan__GPU__CHIP__BACO 1
#define hainan__GPU__CHIP__BACO__1 1
#define hainan__GPU__CEC__PRESENT 1
#define hainan__GPU__CEC__PRESENT__1 1
#define hainan__GPU__CHIP__REAL_RDL_READY 1
#define hainan__GPU__CHIP__REAL_RDL_READY__1 1
#define hainan__GPU__CHIP__INFERRED_REPS 1
#define hainan__GPU__CHIP__INFERRED_REPS__1 1
#define hainan__GPU__CHIP__DRMDMA_POWERGATE 0
#define hainan__GPU__CHIP__DRMDMA_POWERGATE__0 1
#define hainan__GPU__CHIP__EDCMEM1 0
#define hainan__GPU__CHIP__EDCMEM1__0 1
#define hainan__GPU__CHIP__POWERGATE 0
#define hainan__GPU__CHIP__POWERGATE__0 1
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#define hainan__GPU__TMON0__LEFT_NUM_RDI__6 1
#define hainan__GPU__TMON0__RIGHT_NUM_RDI 6
#define hainan__GPU__TMON0__RIGHT_NUM_RDI__6 1
#define hainan__GPU__DFT__IBIZA_TMON 1
#define hainan__GPU__DFT__IBIZA_TMON__1 1
#define hainan__GPU__CHIP__MEM_POWER_CTRL 17
#define hainan__GPU__CHIP__MEM_POWER_CTRL__17 1
#define hainan__GPU__CHIP__MEM_POWER_CTRL_LS 0
#define hainan__GPU__CHIP__MEM_POWER_CTRL_LS__0 1
#define hainan__GPU__CHIP__MEM_POWER_CTRL_DS_D 1
#define hainan__GPU__CHIP__MEM_POWER_CTRL_DS_D__1 1
#define hainan__GPU__CHIP__MEM_POWER_CTRL_DS_M 2
#define hainan__GPU__CHIP__MEM_POWER_CTRL_DS_M__2 1
#define hainan__GPU__CHIP__MEM_POWER_CTRL_SD_D 3
#define hainan__GPU__CHIP__MEM_POWER_CTRL_SD_D__3 1
#define hainan__GPU__CHIP__MEM_POWER_CTRL_SD_M 4
#define hainan__GPU__CHIP__MEM_POWER_CTRL_SD_M__4 1
#define hainan__GPU__CHIP__MEM_POWER_CTRL_DS 5
#define hainan__GPU__CHIP__MEM_POWER_CTRL_DS__5 1
#define hainan__GPU__CHIP__MEM_POWER_CTRL_SD 6
#define hainan__GPU__CHIP__MEM_POWER_CTRL_SD__6 1
#define hainan__GPU__CHIP__MEM_POWER_CTRL_FISO 7
#define hainan__GPU__CHIP__MEM_POWER_CTRL_FISO__7 1
#define hainan__GPU__CHIP__MEM_POWER_CTRL_V_RM_START 8
#define hainan__GPU__CHIP__MEM_POWER_CTRL_V_RM_START__8 1
#define hainan__GPU__CHIP__MEM_POWER_CTRL_V_RM_END 16
#define hainan__GPU__CHIP__MEM_POWER_CTRL_V_RM_END__16 1
#define hainan__GPU__CHIP__MEM_POWER_CTRL_A_RM_START 8
#define hainan__GPU__CHIP__MEM_POWER_CTRL_A_RM_START__8 1
#define hainan__GPU__CHIP__MEM_POWER_CTRL_A_RM_END 30
#define hainan__GPU__CHIP__MEM_POWER_CTRL_A_RM_END__30 1
#define hainan__GPU__CHIP__MEM_POWER_CTRL_V_RM_RF_RME 8
#define hainan__GPU__CHIP__MEM_POWER_CTRL_V_RM_RF_RME__8 1
#define hainan__GPU__CHIP__MEM_POWER_CTRL_V_RM_RF_RM_START 9
#define hainan__GPU__CHIP__MEM_POWER_CTRL_V_RM_RF_RM_START__9 1
#define hainan__GPU__CHIP__MEM_POWER_CTRL_V_RM_RF_RM_END 10
#define hainan__GPU__CHIP__MEM_POWER_CTRL_V_RM_RF_RM_END__10 1
#define hainan__GPU__CHIP__MEM_POWER_CTRL_V_RM_PDP_RME 11
#define hainan__GPU__CHIP__MEM_POWER_CTRL_V_RM_PDP_RME__11 1
#define hainan__GPU__CHIP__MEM_POWER_CTRL_V_RM_PDP_RM_START 12
#define hainan__GPU__CHIP__MEM_POWER_CTRL_V_RM_PDP_RM_START__12 1
#define hainan__GPU__CHIP__MEM_POWER_CTRL_V_RM_PDP_RM_END 13
#define hainan__GPU__CHIP__MEM_POWER_CTRL_V_RM_PDP_RM_END__13 1
#define hainan__GPU__CHIP__MEM_POWER_CTRL_V_RM_HD_RME 14
#define hainan__GPU__CHIP__MEM_POWER_CTRL_V_RM_HD_RME__14 1
#define hainan__GPU__CHIP__MEM_POWER_CTRL_V_RM_HD_RM_START 15
#define hainan__GPU__CHIP__MEM_POWER_CTRL_V_RM_HD_RM_START__15 1
#define hainan__GPU__CHIP__MEM_POWER_CTRL_V_RM_HD_RM_END 16
#define hainan__GPU__CHIP__MEM_POWER_CTRL_V_RM_HD_RM_END__16 1
#define hainan__GPU__CHIP__MEM_POWER_CTRL_A_RM_RF_RME 8
#define hainan__GPU__CHIP__MEM_POWER_CTRL_A_RM_RF_RME__8 1
#define hainan__GPU__CHIP__MEM_POWER_CTRL_A_RM_RF_RM_START 9
#define hainan__GPU__CHIP__MEM_POWER_CTRL_A_RM_RF_RM_START__9 1
#define hainan__GPU__CHIP__MEM_POWER_CTRL_A_RM_RF_RM_END 17
#define hainan__GPU__CHIP__MEM_POWER_CTRL_A_RM_RF_RM_END__17 1
#define hainan__GPU__CHIP__MEM_POWER_CTRL_A_RM_PDP_RME 18
#define hainan__GPU__CHIP__MEM_POWER_CTRL_A_RM_PDP_RME__18 1
#define hainan__GPU__CHIP__MEM_POWER_CTRL_A_RM_PDP_RM_START 19
#define hainan__GPU__CHIP__MEM_POWER_CTRL_A_RM_PDP_RM_START__19 1
#define hainan__GPU__CHIP__MEM_POWER_CTRL_A_RM_PDP_RM_END 30
#define hainan__GPU__CHIP__MEM_POWER_CTRL_A_RM_PDP_RM_END__30 1
#define hainan__GPU__TSS__NUM_TILES 5
#define hainan__GPU__TSS__NUM_TILES__5 1
#define hainan__GPU__TSS__TSS0_TILE 1
#define hainan__GPU__TSS__TSS0_TILE__1 1
#define hainan__GPU__TSS__TSS1_TILE 1
#define hainan__GPU__TSS__TSS1_TILE__1 1
#define hainan__GPU__TSS__TSS2_TILE 1
#define hainan__GPU__TSS__TSS2_TILE__1 1
#define hainan__GPU__TSS__TSS3_TILE 1
#define hainan__GPU__TSS__TSS3_TILE__1 1
#define hainan__GPU__TSS__TSS4_TILE 1
#define hainan__GPU__TSS__TSS4_TILE__1 1
#define hainan__GPU__TSS__TSS4_AS_ADC 1
#define hainan__GPU__TSS__TSS4_AS_ADC__1 1
#define hainan__GPU__RCU__PROGRAMMABLE_RMBITS 1
#define hainan__GPU__RCU__PROGRAMMABLE_RMBITS__1 1
#define hainan__GPU__CGTT_TILE__PDLY 1
#define hainan__GPU__CGTT_TILE__PDLY__1 1
#define hainan__GPU__PDLY_TILE__PDLY 1
#define hainan__GPU__PDLY_TILE__PDLY__1 1
#define hainan__GPU__PDLY_TILE__CLKGATE 0
#define hainan__GPU__PDLY_TILE__CLKGATE__0 1
#define hainan__GPU__CG__SMC_SCRATCH_REGS 1
#define hainan__GPU__CG__SMC_SCRATCH_REGS__1 1
#define hainan__GPU__CG__CG_DLL_PDNB 1
#define hainan__GPU__CG__CG_DLL_PDNB__1 1
#define hainan__GPU__SMU__USE_HW_VBI 1
#define hainan__GPU__SMU__USE_HW_VBI__1 1
#define hainan__GPU__SMU__NUM_CAC_MGR_4 1
#define hainan__GPU__SMU__NUM_CAC_MGR_4__1 1
#define hainan__GPU__PDMA__PRESENT 0
#define hainan__GPU__PDMA__PRESENT__0 1
#define hainan__GPU__DRMDMA__DUAL_DRMDMA_PRESENT 1
#define hainan__GPU__DRMDMA__DUAL_DRMDMA_PRESENT__1 1
#define hainan__GPU__DRM__BGAES_OFF 1
#define hainan__GPU__DRM__BGAES_OFF__1 1
#define hainan__GPU__DLB__SLEW 1
#define hainan__GPU__DLB__SLEW__1 1
#define hainan__GPU__ROM__EXT_CS_EN 1
#define hainan__GPU__ROM__EXT_CS_EN__1 1
#define hainan__GPU__CPL__GPIO_23_PRESENT 0
#define hainan__GPU__CPL__GPIO_23_PRESENT__0 1
#define hainan__GPU__CPL__GPIO_24_PRESENT 0
#define hainan__GPU__CPL__GPIO_24_PRESENT__0 1
#define hainan__GPU__CPL__GPIO_25_PRESENT 0
#define hainan__GPU__CPL__GPIO_25_PRESENT__0 1
#define hainan__GPU__CPL__GPIO_26_PRESENT 0
#define hainan__GPU__CPL__GPIO_26_PRESENT__0 1
#define hainan__GPU__CPL__GPIO_27_PRESENT 0
#define hainan__GPU__CPL__GPIO_27_PRESENT__0 1
#define hainan__GPU__CPL__MLPS_0_PRESENT 1
#define hainan__GPU__CPL__MLPS_0_PRESENT__1 1
#define hainan__GPU__CPL__MLPS_1_PRESENT 1
#define hainan__GPU__CPL__MLPS_1_PRESENT__1 1
#define hainan__GPU__CPL__MLPS_2_PRESENT 1
#define hainan__GPU__CPL__MLPS_2_PRESENT__1 1
#define hainan__GPU__CPL__MLPS_3_PRESENT 1
#define hainan__GPU__CPL__MLPS_3_PRESENT__1 1
#define hainan__GPU__CPL__SX_0_PRESENT 1
#define hainan__GPU__CPL__SX_0_PRESENT__1 1
#define hainan__GPU__SMC__TAP_FED_PRESENT 1
#define hainan__GPU__SMC__TAP_FED_PRESENT__1 1
#define hainan__GPU__CPL__PG_CODE_ENABLE 1
#define hainan__GPU__CPL__PG_CODE_ENABLE__1 1
#define hainan__GPU__CPL__PG_CODE_GPG 1
#define hainan__GPU__CPL__PG_CODE_GPG__1 1
#define hainan__GPU__AVP__MC_IF 1
#define hainan__GPU__AVP__MC_IF__1 1
#define hainan__GPU__AVP__UVD_RLC_CMC_IF 1
#define hainan__GPU__AVP__UVD_RLC_CMC_IF__1 1
#define hainan__GPU__DC__TMDS_LINK tmds_link_dual
#define hainan__GPU__DC__TMDS_LINK__TMDS_LINK_DUAL 1
#define hainan__GPU__DC__NUM_DDC_PAIRS 6
#define hainan__GPU__DC__NUM_DDC_PAIRS__6 1
#define hainan__GPU__DC__NUM_DDC_PAIRS__0_PRESENT 1
#define hainan__GPU__DC__NUM_DDC_PAIRS__1_PRESENT 1
#define hainan__GPU__DC__NUM_DDC_PAIRS__2_PRESENT 1
#define hainan__GPU__DC__NUM_DDC_PAIRS__3_PRESENT 1
#define hainan__GPU__DC__NUM_DDC_PAIRS__4_PRESENT 1
#define hainan__GPU__DC__NUM_DDC_PAIRS__5_PRESENT 1
#define hainan__GPU__DC__NUM_HPD 6
#define hainan__GPU__DC__NUM_HPD__6 1
#define hainan__GPU__DC__NUM_HPD__0_PRESENT 1
#define hainan__GPU__DC__NUM_HPD__1_PRESENT 1
#define hainan__GPU__DC__NUM_HPD__2_PRESENT 1
#define hainan__GPU__DC__NUM_HPD__3_PRESENT 1
#define hainan__GPU__DC__NUM_HPD__4_PRESENT 1
#define hainan__GPU__DC__NUM_HPD__5_PRESENT 1
#define hainan__GPU__DC__NUM_PIPE_PAIRS 3
#define hainan__GPU__DC__NUM_PIPE_PAIRS__3 1
#define hainan__GPU__DC__NUM_PIPE_PAIRS__0_PRESENT 1
#define hainan__GPU__DC__NUM_PIPE_PAIRS__1_PRESENT 1
#define hainan__GPU__DC__NUM_PIPE_PAIRS__2_PRESENT 1
#define hainan__GPU__DC__NUM_PIPES 6
#define hainan__GPU__DC__NUM_PIPES__6 1
#define hainan__GPU__DC__NUM_PIPES__0_PRESENT 1
#define hainan__GPU__DC__NUM_PIPES__1_PRESENT 1
#define hainan__GPU__DC__NUM_PIPES__2_PRESENT 1
#define hainan__GPU__DC__NUM_PIPES__3_PRESENT 1
#define hainan__GPU__DC__NUM_PIPES__4_PRESENT 1
#define hainan__GPU__DC__NUM_PIPES__5_PRESENT 1
#define hainan__GPU__DC__NUM_DIG 6
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#define hainan__GPU__DC__NUM_DIG__0_PRESENT 1
#define hainan__GPU__DC__NUM_DIG__1_PRESENT 1
#define hainan__GPU__DC__NUM_DIG__2_PRESENT 1
#define hainan__GPU__DC__NUM_DIG__3_PRESENT 1
#define hainan__GPU__DC__NUM_DIG__4_PRESENT 1
#define hainan__GPU__DC__NUM_DIG__5_PRESENT 1
#define hainan__GPU__DC__NUM_AUX 6
#define hainan__GPU__DC__NUM_AUX__6 1
#define hainan__GPU__DC__NUM_AUX__0_PRESENT 1
#define hainan__GPU__DC__NUM_AUX__1_PRESENT 1
#define hainan__GPU__DC__NUM_AUX__2_PRESENT 1
#define hainan__GPU__DC__NUM_AUX__3_PRESENT 1
#define hainan__GPU__DC__NUM_AUX__4_PRESENT 1
#define hainan__GPU__DC__NUM_AUX__5_PRESENT 1
#define hainan__GPU__DISPPLL__MACRO walden
#define hainan__GPU__DISPPLL__MACRO__WALDEN 1
#define hainan__GPU__TMDPA__MACRO walden
#define hainan__GPU__TMDPA__MACRO__WALDEN 1
#define hainan__GPU__TMDPB__MACRO walden
#define hainan__GPU__TMDPB__MACRO__WALDEN 1
#define hainan__GPU__LVTMDP__MACRO walden
#define hainan__GPU__LVTMDP__MACRO__WALDEN 1
#define hainan__GPU__DACA__MACRO walden
#define hainan__GPU__DACA__MACRO__WALDEN 1
#define hainan__GPU__DACB__MACRO walden
#define hainan__GPU__DACB__MACRO__WALDEN 1
#define hainan__GPU__DC__VIP_PRESENT 1
#define hainan__GPU__DC__VIP_PRESENT__1 1
#define hainan__GPU__DC__ABM_PRESENT 1
#define hainan__GPU__DC__ABM_PRESENT__1 1
#define hainan__GPU__DC__DMCU_PRESENT 1
#define hainan__GPU__DC__DMCU_PRESENT__1 1
#define hainan__GPU__DC__DVO_PRESENT 1
#define hainan__GPU__DC__DVO_PRESENT__1 1
#define hainan__GPU__DC__SDVO_PRESENT 1
#define hainan__GPU__DC__SDVO_PRESENT__1 1
#define hainan__GPU__DC__LVDS_PRESENT 1
#define hainan__GPU__DC__LVDS_PRESENT__1 1
#define hainan__GPU__UNIPHYAB__PRESENT 1
#define hainan__GPU__UNIPHYAB__PRESENT__1 1
#define hainan__GPU__UNIPHYCD__PRESENT 1
#define hainan__GPU__UNIPHYCD__PRESENT__1 1
#define hainan__GPU__UNIPHYEF__PRESENT 1
#define hainan__GPU__UNIPHYEF__PRESENT__1 1
#define hainan__GPU__UNIPHYAB__TYPE lvtmdp
#define hainan__GPU__UNIPHYAB__TYPE__LVTMDP 1
#define hainan__GPU__UNIPHYCD__TYPE tmdpa
#define hainan__GPU__UNIPHYCD__TYPE__TMDPA 1
#define hainan__GPU__UNIPHYEF__TYPE tmdpb
#define hainan__GPU__UNIPHYEF__TYPE__TMDPB 1
#define hainan__GPU__UNIPHYAB__LVTMDP 1
#define hainan__GPU__UNIPHYAB__LVTMDP__1 1
#define hainan__GPU__DC__DACA_PRESENT 1
#define hainan__GPU__DC__DACA_PRESENT__1 1
#define hainan__GPU__DC__DACB_PRESENT 1
#define hainan__GPU__DC__DACB_PRESENT__1 1
#define hainan__GPU__DC__TVOUT_PRESENT 1
#define hainan__GPU__DC__TVOUT_PRESENT__1 1
#define hainan__GPU__DC__MVP_PRESENT 1
#define hainan__GPU__DC__MVP_PRESENT__1 1
#define hainan__GPU__DC__DENTIST_INTERFACE_PRESENT 0
#define hainan__GPU__DC__DENTIST_INTERFACE_PRESENT__0 1
#define hainan__GPU__DC__DDC1AUX1 dual_mode
#define hainan__GPU__DC__DDC1AUX1__DUAL_MODE 1
#define hainan__GPU__DC__DDC2AUX2 dual_mode
#define hainan__GPU__DC__DDC2AUX2__DUAL_MODE 1
#define hainan__GPU__DC__DDC3AUX3 dual_mode
#define hainan__GPU__DC__DDC3AUX3__DUAL_MODE 1
#define hainan__GPU__DC__DDC4AUX4 dual_mode
#define hainan__GPU__DC__DDC4AUX4__DUAL_MODE 1
#define hainan__GPU__DC__DDC5AUX5 dual_mode
#define hainan__GPU__DC__DDC5AUX5__DUAL_MODE 1
#define hainan__GPU__DC__DDC6AUX6 dual_mode
#define hainan__GPU__DC__DDC6AUX6__DUAL_MODE 1
#define hainan__GPU__DC__AUX1_PRESENT 1
#define hainan__GPU__DC__AUX1_PRESENT__1 1
#define hainan__GPU__DC__AUX2_PRESENT 1
#define hainan__GPU__DC__AUX2_PRESENT__1 1
#define hainan__GPU__DC__AUX3_PRESENT 1
#define hainan__GPU__DC__AUX3_PRESENT__1 1
#define hainan__GPU__DC__AUX4_PRESENT 1
#define hainan__GPU__DC__AUX4_PRESENT__1 1
#define hainan__GPU__DC__AUX5_PRESENT 1
#define hainan__GPU__DC__AUX5_PRESENT__1 1
#define hainan__GPU__DC__AUX6_PRESENT 1
#define hainan__GPU__DC__AUX6_PRESENT__1 1
#define hainan__GPU__DC__DENTIST_PRESENT 0
#define hainan__GPU__DC__DENTIST_PRESENT__0 1
#define hainan__GPU__DC__GENERICA_PRESENT 1
#define hainan__GPU__DC__GENERICA_PRESENT__1 1
#define hainan__GPU__DC__GENERICB_PRESENT 1
#define hainan__GPU__DC__GENERICB_PRESENT__1 1
#define hainan__GPU__DC__GENERICC_PRESENT 1
#define hainan__GPU__DC__GENERICC_PRESENT__1 1
#define hainan__GPU__DC__GENERICD_PRESENT 1
#define hainan__GPU__DC__GENERICD_PRESENT__1 1
#define hainan__GPU__DC__GENERICE_PRESENT 1
#define hainan__GPU__DC__GENERICE_PRESENT__1 1
#define hainan__GPU__DC__GENERICF_PRESENT 1
#define hainan__GPU__DC__GENERICF_PRESENT__1 1
#define hainan__GPU__DC__GENERICG_PRESENT 1
#define hainan__GPU__DC__GENERICG_PRESENT__1 1
#define hainan__GPU__DC__BLON_TYPE 0
#define hainan__GPU__DC__BLON_TYPE__0 1
#define hainan__GPU__DC__NB_STUTTER_MODE_PRESENT 0
#define hainan__GPU__DC__NB_STUTTER_MODE_PRESENT__0 1
#define hainan__GPU__DC__PCIE_REFCLK_TEST_MODE_MUX_PRESENT 0
#define hainan__GPU__DC__PCIE_REFCLK_TEST_MODE_MUX_PRESENT__0 1
#define hainan__GPU__DC__REFCLK_TEST_MODE_MUX_PRESENT 0
#define hainan__GPU__DC__REFCLK_TEST_MODE_MUX_PRESENT__0 1
#define hainan__GPU__DC__PIXCLK_TEST_MODE_MUX_PRESENT 0
#define hainan__GPU__DC__PIXCLK_TEST_MODE_MUX_PRESENT__0 1
#define hainan__GPU__DC__SYMCLK_TEST_MODE_MUX_PRESENT 0
#define hainan__GPU__DC__SYMCLK_TEST_MODE_MUX_PRESENT__0 1
#define hainan__GPU__GC__NUM_SE 1
#define hainan__GPU__GC__NUM_SE__1 1
#define hainan__GPU__GC__NUM_SE__0_PRESENT 1
#define hainan__GPU__GC__NUM_SH_PER_SE 1
#define hainan__GPU__GC__NUM_SH_PER_SE__1 1
#define hainan__GPU__GC__NUM_SH_PER_SE__0_PRESENT 1
#define hainan__GPU__GC__NUM_RB_PER_SE 1
#define hainan__GPU__GC__NUM_RB_PER_SE__1 1
#define hainan__GPU__GC__NUM_RB_PER_SE__0_PRESENT 1
#define hainan__GPU__GC__NUM_CU_PER_SH 5
#define hainan__GPU__GC__NUM_CU_PER_SH__5 1
#define hainan__GPU__GC__NUM_CU_PER_SH__0_PRESENT 1
#define hainan__GPU__GC__NUM_CU_PER_SH__1_PRESENT 1
#define hainan__GPU__GC__NUM_CU_PER_SH__2_PRESENT 1
#define hainan__GPU__GC__NUM_CU_PER_SH__3_PRESENT 1
#define hainan__GPU__GC__NUM_CU_PER_SH__4_PRESENT 1
#define hainan__GPU__GC__WAVE_SIZE 64
#define hainan__GPU__GC__WAVE_SIZE__64 1
#define hainan__GPU__GC__NUM_CP_RINGS 3
#define hainan__GPU__GC__NUM_CP_RINGS__3 1
#define hainan__GPU__GC__NUM_CP_RINGS__0_PRESENT 1
#define hainan__GPU__GC__NUM_CP_RINGS__1_PRESENT 1
#define hainan__GPU__GC__NUM_CP_RINGS__2_PRESENT 1
#define hainan__GPU__GC__NUM_SC_PER_SE 1
#define hainan__GPU__GC__NUM_SC_PER_SE__1 1
#define hainan__GPU__GC__NUM_SC_PER_SE__0_PRESENT 1
#define hainan__GPU__GC__NUM_BCI_PER_SE 1
#define hainan__GPU__GC__NUM_BCI_PER_SE__1 1
#define hainan__GPU__GC__NUM_BCI_PER_SE__0_PRESENT 1
#define hainan__GPU__GC__NUM_RB_PER_SC 1
#define hainan__GPU__GC__NUM_RB_PER_SC__1 1
#define hainan__GPU__GC__NUM_RB_PER_SC__0_PRESENT 1
#define hainan__GPU__GC__NUM_RB_PER_PACKER 1
#define hainan__GPU__GC__NUM_RB_PER_PACKER__1 1
#define hainan__GPU__GC__NUM_RB_PER_PACKER__0_PRESENT 1
#define hainan__GPU__GC__NUM_PACKER_PER_SC 1
#define hainan__GPU__GC__NUM_PACKER_PER_SC__1 1
#define hainan__GPU__GC__NUM_PACKER_PER_SC__0_PRESENT 1
#define hainan__GPU__GC__NUM_DB_PER_PACKER 1
#define hainan__GPU__GC__NUM_DB_PER_PACKER__1 1
#define hainan__GPU__GC__NUM_DB_PER_PACKER__0_PRESENT 1
#define hainan__GPU__GC__NUM_PACKER_PER_SE 1
#define hainan__GPU__GC__NUM_PACKER_PER_SE__1 1
#define hainan__GPU__GC__NUM_PACKER_PER_SE__0_PRESENT 1
#define hainan__GPU__GC__NUM_RB_PER_SX 1
#define hainan__GPU__GC__NUM_RB_PER_SX__1 1
#define hainan__GPU__GC__NUM_RB_PER_SX__0_PRESENT 1
#define hainan__GPU__GC__NUM_CU_PER_SE 5
#define hainan__GPU__GC__NUM_CU_PER_SE__5 1
#define hainan__GPU__GC__NUM_CU_PER_SE__0_PRESENT 1
#define hainan__GPU__GC__NUM_CU_PER_SE__1_PRESENT 1
#define hainan__GPU__GC__NUM_CU_PER_SE__2_PRESENT 1
#define hainan__GPU__GC__NUM_CU_PER_SE__3_PRESENT 1
#define hainan__GPU__GC__NUM_CU_PER_SE__4_PRESENT 1
#define hainan__GPU__GC__MAX_NUMBER_WAVES 200
#define hainan__GPU__GC__MAX_NUMBER_WAVES__200 1
#define hainan__GPU__GC__MAX_NUMBER_WAVES_PER_PACKER 200
#define hainan__GPU__GC__MAX_NUMBER_WAVES_PER_PACKER__200 1
#define hainan__GPU__SQ__NUM_WAVES_PER_SIMD 10
#define hainan__GPU__SQ__NUM_WAVES_PER_SIMD__10 1
#define hainan__GPU__SQ__THREAD_GROUPS_PER_CU 16
#define hainan__GPU__SQ__THREAD_GROUPS_PER_CU__16 1
#define hainan__GPU__SQ__NUM_PERF_CNTRS 8
#define hainan__GPU__SQ__NUM_PERF_CNTRS__8 1
#define hainan__GPU__SQ__NUM_PERF_CNTRS__0_PRESENT 1
#define hainan__GPU__SQ__NUM_PERF_CNTRS__1_PRESENT 1
#define hainan__GPU__SQ__NUM_PERF_CNTRS__2_PRESENT 1
#define hainan__GPU__SQ__NUM_PERF_CNTRS__3_PRESENT 1
#define hainan__GPU__SQ__NUM_PERF_CNTRS__4_PRESENT 1
#define hainan__GPU__SQ__NUM_PERF_CNTRS__5_PRESENT 1
#define hainan__GPU__SQ__NUM_PERF_CNTRS__6_PRESENT 1
#define hainan__GPU__SQ__NUM_PERF_CNTRS__7_PRESENT 1
#define hainan__GPU__SQ__NUM_SGPR_PER_SIMD 512
#define hainan__GPU__SQ__NUM_SGPR_PER_SIMD__512 1
#define hainan__GPU__SQ__P2_IS_P1 1
#define hainan__GPU__SQ__P2_IS_P1__1 1
#define hainan__GPU__SQ__USE_SV_PACKAGES 0
#define hainan__GPU__SQ__USE_SV_PACKAGES__0 1
#define hainan__GPU__SQ__BUG_307568_FIXED 1
#define hainan__GPU__SQ__BUG_307568_FIXED__1 1
#define hainan__GPU__SQC__NUM_SQC 2
#define hainan__GPU__SQC__NUM_SQC__2 1
#define hainan__GPU__SQC__NUM_SQC__0_PRESENT 1
#define hainan__GPU__SQC__NUM_SQC__1_PRESENT 1
#define hainan__GPU__SQC__NUM_SQC_PER_SH 2
#define hainan__GPU__SQC__NUM_SQC_PER_SH__2 1
#define hainan__GPU__SQC__NUM_SQC_PER_SH__0_PRESENT 1
#define hainan__GPU__SQC__NUM_SQC_PER_SH__1_PRESENT 1
#define hainan__GPU__SQC__IDENTICAL_NAMES 0
#define hainan__GPU__SQC__IDENTICAL_NAMES__0 1
#define hainan__GPU__SQC__SH_SQC0_POSN_AFTER_SQ 0
#define hainan__GPU__SQC__SH_SQC0_POSN_AFTER_SQ__0 1
#define hainan__GPU__SQC__SH_SQC0_FIRST_CONNECTED_SQ 0
#define hainan__GPU__SQC__SH_SQC0_FIRST_CONNECTED_SQ__0 1
#define hainan__GPU__SQC__SH_SQC0_NUM_CU 3
#define hainan__GPU__SQC__SH_SQC0_NUM_CU__3 1
#define hainan__GPU__SQC__SH_SQC0_NUM_CU__0_PRESENT 1
#define hainan__GPU__SQC__SH_SQC0_NUM_CU__1_PRESENT 1
#define hainan__GPU__SQC__SH_SQC0_NUM_CU__2_PRESENT 1
#define hainan__GPU__SQC__SH_SQC0_NUM_BANK 4
#define hainan__GPU__SQC__SH_SQC0_NUM_BANK__4 1
#define hainan__GPU__SQC__SH_SQC0_NUM_BANK__0_PRESENT 1
#define hainan__GPU__SQC__SH_SQC0_NUM_BANK__1_PRESENT 1
#define hainan__GPU__SQC__SH_SQC0_NUM_BANK__2_PRESENT 1
#define hainan__GPU__SQC__SH_SQC0_NUM_BANK__3_PRESENT 1
#define hainan__GPU__SQC__SH_SQC0_BANK_INST_CACHE_SIZE_KBYTES 8
#define hainan__GPU__SQC__SH_SQC0_BANK_INST_CACHE_SIZE_KBYTES__8 1
#define hainan__GPU__SQC__SH_SQC0_BANK_DATA_CACHE_SIZE_KBYTES 4
#define hainan__GPU__SQC__SH_SQC0_BANK_DATA_CACHE_SIZE_KBYTES__4 1
#define hainan__GPU__SQC__SH_SQC1_POSN_AFTER_SQ 3
#define hainan__GPU__SQC__SH_SQC1_POSN_AFTER_SQ__3 1
#define hainan__GPU__SQC__SH_SQC1_FIRST_CONNECTED_SQ 3
#define hainan__GPU__SQC__SH_SQC1_FIRST_CONNECTED_SQ__3 1
#define hainan__GPU__SQC__SH_SQC1_NUM_CU 2
#define hainan__GPU__SQC__SH_SQC1_NUM_CU__2 1
#define hainan__GPU__SQC__SH_SQC1_NUM_CU__0_PRESENT 1
#define hainan__GPU__SQC__SH_SQC1_NUM_CU__1_PRESENT 1
#define hainan__GPU__SQC__SH_SQC1_NUM_BANK 2
#define hainan__GPU__SQC__SH_SQC1_NUM_BANK__2 1
#define hainan__GPU__SQC__SH_SQC1_NUM_BANK__0_PRESENT 1
#define hainan__GPU__SQC__SH_SQC1_NUM_BANK__1_PRESENT 1
#define hainan__GPU__SQC__SH_SQC1_BANK_INST_CACHE_SIZE_KBYTES 16
#define hainan__GPU__SQC__SH_SQC1_BANK_INST_CACHE_SIZE_KBYTES__16 1
#define hainan__GPU__SQC__SH_SQC1_BANK_DATA_CACHE_SIZE_KBYTES 8
#define hainan__GPU__SQC__SH_SQC1_BANK_DATA_CACHE_SIZE_KBYTES__8 1
#define hainan__GPU__SQC__SH_SQC2_POSN_AFTER_SQ 0
#define hainan__GPU__SQC__SH_SQC2_POSN_AFTER_SQ__0 1
#define hainan__GPU__SQC__SH_SQC2_FIRST_CONNECTED_SQ 0
#define hainan__GPU__SQC__SH_SQC2_FIRST_CONNECTED_SQ__0 1
#define hainan__GPU__SQC__SH_SQC2_NUM_CU 0
#define hainan__GPU__SQC__SH_SQC2_NUM_CU__0 1
#define hainan__GPU__SQC__SH_SQC2_NUM_BANK 0
#define hainan__GPU__SQC__SH_SQC2_NUM_BANK__0 1
#define hainan__GPU__SQC__SH_SQC2_BANK_INST_CACHE_SIZE_KBYTES 0
#define hainan__GPU__SQC__SH_SQC2_BANK_INST_CACHE_SIZE_KBYTES__0 1
#define hainan__GPU__SQC__SH_SQC2_BANK_DATA_CACHE_SIZE_KBYTES 0
#define hainan__GPU__SQC__SH_SQC2_BANK_DATA_CACHE_SIZE_KBYTES__0 1
#define hainan__GPU__SQC__P2_IS_P1 1
#define hainan__GPU__SQC__P2_IS_P1__1 1
#define hainan__GPU__SQC__BUG_303685_EXISTS 1
#define hainan__GPU__SQC__BUG_303685_EXISTS__1 1
#define hainan__GPU__GC__GDS_EXISTS 1
#define hainan__GPU__GC__GDS_EXISTS__1 1
#define hainan__GPU__GC__RB_REDUNDANCY 0
#define hainan__GPU__GC__RB_REDUNDANCY__0 1
#define hainan__GPU__GC__SC_DOES_RB_REDUNDANCY 0
#define hainan__GPU__GC__SC_DOES_RB_REDUNDANCY__0 1
#define hainan__GPU__GC__MEM_ADDR_BITS 40
#define hainan__GPU__GC__MEM_ADDR_BITS__40 1
#define hainan__GPU__GC__NEW_VERTEX_VECTOR_ORDER 0
#define hainan__GPU__GC__NEW_VERTEX_VECTOR_ORDER__0 1
#define hainan__GPU__GC__NUM_INTERPS 1
#define hainan__GPU__GC__NUM_INTERPS__1 1
#define hainan__GPU__GC__HZ_PRESENT 1
#define hainan__GPU__GC__HZ_PRESENT__1 1
#define hainan__GPU__GC__NUM_CLKS_PER_PRIM 1
#define hainan__GPU__GC__NUM_CLKS_PER_PRIM__1 1
#define hainan__GPU__GC__NUM_INTERP_PRIM_PER_CLK 2
#define hainan__GPU__GC__NUM_INTERP_PRIM_PER_CLK__2 1
#define hainan__GPU__GC__ATTR_BUS_PRIM_PER_CLK 2
#define hainan__GPU__GC__ATTR_BUS_PRIM_PER_CLK__2 1
#define hainan__GPU__GC__NUM_MAX_GS_THDS 16
#define hainan__GPU__GC__NUM_MAX_GS_THDS__16 1
#define hainan__GPU__GC__NUM_MIN_GS_THDS 4
#define hainan__GPU__GC__NUM_MIN_GS_THDS__4 1
#define hainan__GPU__GC__NUM_STATES 8
#define hainan__GPU__GC__NUM_STATES__8 1
#define hainan__GPU__GC__NUM_STATES__0_PRESENT 1
#define hainan__GPU__GC__NUM_STATES__1_PRESENT 1
#define hainan__GPU__GC__NUM_STATES__2_PRESENT 1
#define hainan__GPU__GC__NUM_STATES__3_PRESENT 1
#define hainan__GPU__GC__NUM_STATES__4_PRESENT 1
#define hainan__GPU__GC__NUM_STATES__5_PRESENT 1
#define hainan__GPU__GC__NUM_STATES__6_PRESENT 1
#define hainan__GPU__GC__NUM_STATES__7_PRESENT 1
#define hainan__GPU__GC__STWTPTR_WIDTH 3
#define hainan__GPU__GC__STWTPTR_WIDTH__3 1
#define hainan__GPU__SH__DOUBLE_FLOAT_PRESENT 1
#define hainan__GPU__SH__DOUBLE_FLOAT_PRESENT__1 1
#define hainan__GPU__SH__NUM_DOUBLE_VSPS_PER_SIMD 1
#define hainan__GPU__SH__NUM_DOUBLE_VSPS_PER_SIMD__1 1
#define hainan__GPU__SH__NUM_DOUBLE_VSPS_PER_SIMD__0_PRESENT 1
#define hainan__GPU__SH__NORM_SIN_COS 1
#define hainan__GPU__SH__NORM_SIN_COS__1 1
#define hainan__GPU__SH__MICROCODE_LEVEL 10
#define hainan__GPU__SH__MICROCODE_LEVEL__10 1
#define hainan__GPU__SH__NUM_EXPREQ_PER_CU 12
#define hainan__GPU__SH__NUM_EXPREQ_PER_CU__12 1
#define hainan__GPU__GC__GLOBAL_VGT_PA 0
#define hainan__GPU__GC__GLOBAL_VGT_PA__0 1
#define hainan__GPU__GC__NUM_FRONTEND 1
#define hainan__GPU__GC__NUM_FRONTEND__1 1
#define hainan__GPU__GC__NUM_FRONTEND__0_PRESENT 1
#define hainan__GPU__GC__COALESCED_READ_PRESENT 1
#define hainan__GPU__GC__COALESCED_READ_PRESENT__1 1
#define hainan__GPU__GC__NUM_CLKS_PER_TILE 1
#define hainan__GPU__GC__NUM_CLKS_PER_TILE__1 1
#define hainan__GPU__GC__DBSC_TRUE_QUAD_INTF 1
#define hainan__GPU__GC__DBSC_TRUE_QUAD_INTF__1 1
#define hainan__GPU__GC__ASYNC_DISPATCH 1
#define hainan__GPU__GC__ASYNC_DISPATCH__1 1
#define hainan__GPU__GC__VMID_PORTS_EXISTS 1
#define hainan__GPU__GC__VMID_PORTS_EXISTS__1 1
#define hainan__GPU__GC__NUM_EXPORT_BUS 2
#define hainan__GPU__GC__NUM_EXPORT_BUS__2 1
#define hainan__GPU__GC__TILING_CONFIG_TABLE 1
#define hainan__GPU__GC__TILING_CONFIG_TABLE__1 1
#define hainan__GPU__GC__FMASK_TILING_CONFIG_TABLE 1
#define hainan__GPU__GC__FMASK_TILING_CONFIG_TABLE__1 1
#define hainan__GPU__GC__NEW_SRC_COLOR_FORMAT 1
#define hainan__GPU__GC__NEW_SRC_COLOR_FORMAT__1 1
#define hainan__GPU__SP__NUM_GPRS 256
#define hainan__GPU__SP__NUM_GPRS__256 1
#define hainan__GPU__SP__GPR_ADDR_WIDTH 8
#define hainan__GPU__SP__GPR_ADDR_WIDTH__8 1
#define hainan__GPU__SP__WIDTH_GPRS 128
#define hainan__GPU__SP__WIDTH_GPRS__128 1
#define hainan__GPU__SPI__TMP_SCBD_SLOTS_PER_CU 32
#define hainan__GPU__SPI__TMP_SCBD_SLOTS_PER_CU__32 1
#define hainan__GPU__VGT__GSPRIM_BUFF_DEPTH 768
#define hainan__GPU__VGT__GSPRIM_BUFF_DEPTH__768 1
#define hainan__GPU__VGT__GS_TABLE_DEPTH 16
#define hainan__GPU__VGT__GS_TABLE_DEPTH__16 1
#define hainan__GPU__SX__PARAMETER_CACHE_DEPTH 512
#define hainan__GPU__SX__PARAMETER_CACHE_DEPTH__512 1
#define hainan__GPU__SX__PARAMETER_CACHE_WIDTH 16
#define hainan__GPU__SX__PARAMETER_CACHE_WIDTH__16 1
#define hainan__GPU__SX__PARAMETER_CACHE_WIDTH__0_PRESENT 1
#define hainan__GPU__SX__PARAMETER_CACHE_WIDTH__1_PRESENT 1
#define hainan__GPU__SX__PARAMETER_CACHE_WIDTH__2_PRESENT 1
#define hainan__GPU__SX__PARAMETER_CACHE_WIDTH__3_PRESENT 1
#define hainan__GPU__SX__PARAMETER_CACHE_WIDTH__4_PRESENT 1
#define hainan__GPU__SX__PARAMETER_CACHE_WIDTH__5_PRESENT 1
#define hainan__GPU__SX__PARAMETER_CACHE_WIDTH__6_PRESENT 1
#define hainan__GPU__SX__PARAMETER_CACHE_WIDTH__7_PRESENT 1
#define hainan__GPU__SX__PARAMETER_CACHE_WIDTH__8_PRESENT 1
#define hainan__GPU__SX__PARAMETER_CACHE_WIDTH__9_PRESENT 1
#define hainan__GPU__SX__PARAMETER_CACHE_WIDTH__10_PRESENT 1
#define hainan__GPU__SX__PARAMETER_CACHE_WIDTH__11_PRESENT 1
#define hainan__GPU__SX__PARAMETER_CACHE_WIDTH__12_PRESENT 1
#define hainan__GPU__SX__PARAMETER_CACHE_WIDTH__13_PRESENT 1
#define hainan__GPU__SX__PARAMETER_CACHE_WIDTH__14_PRESENT 1
#define hainan__GPU__SX__PARAMETER_CACHE_WIDTH__15_PRESENT 1
#define hainan__GPU__SX__COLOR_SCOREBOARD_SLOTS 64
#define hainan__GPU__SX__COLOR_SCOREBOARD_SLOTS__64 1
#define hainan__GPU__SX__POS_SCOREBOARD_SLOTS 16
#define hainan__GPU__SX__POS_SCOREBOARD_SLOTS__16 1
#define hainan__GPU__SX__COLOR_EXPORT_BUFFER_SIZE 256
#define hainan__GPU__SX__COLOR_EXPORT_BUFFER_SIZE__256 1
#define hainan__GPU__SX__POS_EXPORT_BUFFER_SIZE 256
#define hainan__GPU__SX__POS_EXPORT_BUFFER_SIZE__256 1
#define hainan__GPU__SX__COLOR_EXPORT_REG_BUFFER_SIZE 1024
#define hainan__GPU__SX__COLOR_EXPORT_REG_BUFFER_SIZE__1024 1
#define hainan__GPU__SX__POS_EXPORT_REG_BUFFER_SIZE 1024
#define hainan__GPU__SX__POS_EXPORT_REG_BUFFER_SIZE__1024 1
#define hainan__GPU__SX__PIXEL_FIFO_DEPTH 32
#define hainan__GPU__SX__PIXEL_FIFO_DEPTH__32 1
#define hainan__GPU__PA__PRIM_BUFF_DEPTH 1536
#define hainan__GPU__PA__PRIM_BUFF_DEPTH__1536 1
#define hainan__GPU__PA__NUM_CLIPPERS 4
#define hainan__GPU__PA__NUM_CLIPPERS__4 1
#define hainan__GPU__PA__LOG2_MAX_SAMPLES 3
#define hainan__GPU__PA__LOG2_MAX_SAMPLES__3 1
#define hainan__GPU__TA__GRBM_INTF_RESET_FIX 1
#define hainan__GPU__TA__GRBM_INTF_RESET_FIX__1 1
#define hainan__GPU__TC__TCC_PRESENT 1
#define hainan__GPU__TC__TCC_PRESENT__1 1
#define hainan__GPU__TC__TCR_TCA_REQ_CREDITS 32
#define hainan__GPU__TC__TCR_TCA_REQ_CREDITS__32 1
#define hainan__GPU__TC__TA_HANDLE_BASEADDR 1
#define hainan__GPU__TC__TA_HANDLE_BASEADDR__1 1
#define hainan__GPU__TC__TCP_L1_SIZE 16
#define hainan__GPU__TC__TCP_L1_SIZE__16 1
#define hainan__GPU__TC__NUM_TCPS 5
#define hainan__GPU__TC__NUM_TCPS__5 1
#define hainan__GPU__TC__NUM_TCPS__0_PRESENT 1
#define hainan__GPU__TC__NUM_TCPS__1_PRESENT 1
#define hainan__GPU__TC__NUM_TCPS__2_PRESENT 1
#define hainan__GPU__TC__NUM_TCPS__3_PRESENT 1
#define hainan__GPU__TC__NUM_TCPS__4_PRESENT 1
#define hainan__GPU__TC__NUM_TCCS 2
#define hainan__GPU__TC__NUM_TCCS__2 1
#define hainan__GPU__TC__NUM_TCCS__0_PRESENT 1
#define hainan__GPU__TC__NUM_TCCS__1_PRESENT 1
#define hainan__GPU__TC__NUM_TCAS 2
#define hainan__GPU__TC__NUM_TCAS__2 1
#define hainan__GPU__TC__NUM_TCAS__0_PRESENT 1
#define hainan__GPU__TC__NUM_TCAS__1_PRESENT 1
#define hainan__GPU__TC__NUM_TCIRS 3
#define hainan__GPU__TC__NUM_TCIRS__3 1
#define hainan__GPU__TC__NUM_TCIRS__0_PRESENT 1
#define hainan__GPU__TC__NUM_TCIRS__1_PRESENT 1
#define hainan__GPU__TC__NUM_TCIRS__2_PRESENT 1
#define hainan__GPU__TC__NUM_TCIWS 1
#define hainan__GPU__TC__NUM_TCIWS__1 1
#define hainan__GPU__TC__NUM_TCIWS__0_PRESENT 1
#define hainan__GPU__TC__CLIENT_TCI_REQ_CREDITS 8
#define hainan__GPU__TC__CLIENT_TCI_REQ_CREDITS__8 1
#define hainan__GPU__TC__VGT_TCI_REQ_CREDITS 8
#define hainan__GPU__TC__VGT_TCI_REQ_CREDITS__8 1
#define hainan__GPU__TC__SQC_TCI_REQ_CREDITS 8
#define hainan__GPU__TC__SQC_TCI_REQ_CREDITS__8 1
#define hainan__GPU__TC__CP_TCI_REQ_CREDITS 8
#define hainan__GPU__TC__CP_TCI_REQ_CREDITS__8 1
#define hainan__GPU__TC__NUM_TCIS 4
#define hainan__GPU__TC__NUM_TCIS__4 1
#define hainan__GPU__TC__NUM_TCIS__0_PRESENT 1
#define hainan__GPU__TC__NUM_TCIS__1_PRESENT 1
#define hainan__GPU__TC__NUM_TCIS__2_PRESENT 1
#define hainan__GPU__TC__NUM_TCIS__3_PRESENT 1
#define hainan__GPU__TC__TCC_NUM_LINES 2048
#define hainan__GPU__TC__TCC_NUM_LINES__2048 1
#define hainan__GPU__TC__TCA_PHASE 1
#define hainan__GPU__TC__TCA_PHASE__1 1
#define hainan__GPU__TC__TCA_RTN_ARB_IO_PIPELINING 0
#define hainan__GPU__TC__TCA_RTN_ARB_IO_PIPELINING__0 1
#define hainan__GPU__TC__CP_VGT_TCI_ABOVE_SH0 0
#define hainan__GPU__TC__CP_VGT_TCI_ABOVE_SH0__0 1
#define hainan__GPU__DB__TB_USES_EMULATOR_MODE 0
#define hainan__GPU__DB__TB_USES_EMULATOR_MODE__0 1
#define hainan__GPU__DB__USE_ADDRRAXX_LIB 1
#define hainan__GPU__DB__USE_ADDRRAXX_LIB__1 1
#define hainan__GPU__DB__LEGACY_TILE_MODE_ASSERTS 1
#define hainan__GPU__DB__LEGACY_TILE_MODE_ASSERTS__1 1
#define hainan__GPU__DB__SUBBLOCK_GATES_PRESENT 1
#define hainan__GPU__DB__SUBBLOCK_GATES_PRESENT__1 1
#define hainan__GPU__CB__BLENDER_NUM_PIXELS 4
#define hainan__GPU__CB__BLENDER_NUM_PIXELS__4 1
#define hainan__GPU__CB__BLENDER_NUM_FP32_COMPS 4
#define hainan__GPU__CB__BLENDER_NUM_FP32_COMPS__4 1
#define hainan__GPU__CB__COMPRESSION 1
#define hainan__GPU__CB__COMPRESSION__1 1
#define hainan__GPU__LDS__SIZE 64
#define hainan__GPU__LDS__SIZE__64 1
#define hainan__GPU__LDS__NUM_PIXELS 32
#define hainan__GPU__LDS__NUM_PIXELS__32 1
#define hainan__GPU__LDS__NUM_BANKS 32
#define hainan__GPU__LDS__NUM_BANKS__32 1
#define hainan__GPU__GDS__SIZE 64
#define hainan__GPU__GDS__SIZE__64 1
#define hainan__GPU__GDS__NUM_PIXELS 16
#define hainan__GPU__GDS__NUM_PIXELS__16 1
#define hainan__GPU__GDS__NUM_PIXELS__0_PRESENT 1
#define hainan__GPU__GDS__NUM_PIXELS__1_PRESENT 1
#define hainan__GPU__GDS__NUM_PIXELS__2_PRESENT 1
#define hainan__GPU__GDS__NUM_PIXELS__3_PRESENT 1
#define hainan__GPU__GDS__NUM_PIXELS__4_PRESENT 1
#define hainan__GPU__GDS__NUM_PIXELS__5_PRESENT 1
#define hainan__GPU__GDS__NUM_PIXELS__6_PRESENT 1
#define hainan__GPU__GDS__NUM_PIXELS__7_PRESENT 1
#define hainan__GPU__GDS__NUM_PIXELS__8_PRESENT 1
#define hainan__GPU__GDS__NUM_PIXELS__9_PRESENT 1
#define hainan__GPU__GDS__NUM_PIXELS__10_PRESENT 1
#define hainan__GPU__GDS__NUM_PIXELS__11_PRESENT 1
#define hainan__GPU__GDS__NUM_PIXELS__12_PRESENT 1
#define hainan__GPU__GDS__NUM_PIXELS__13_PRESENT 1
#define hainan__GPU__GDS__NUM_PIXELS__14_PRESENT 1
#define hainan__GPU__GDS__NUM_PIXELS__15_PRESENT 1
#define hainan__GPU__GDS__NUM_BANKS 16
#define hainan__GPU__GDS__NUM_BANKS__16 1
#define hainan__GPU__GDS__NUM_BANKS__0_PRESENT 1
#define hainan__GPU__GDS__NUM_BANKS__1_PRESENT 1
#define hainan__GPU__GDS__NUM_BANKS__2_PRESENT 1
#define hainan__GPU__GDS__NUM_BANKS__3_PRESENT 1
#define hainan__GPU__GDS__NUM_BANKS__4_PRESENT 1
#define hainan__GPU__GDS__NUM_BANKS__5_PRESENT 1
#define hainan__GPU__GDS__NUM_BANKS__6_PRESENT 1
#define hainan__GPU__GDS__NUM_BANKS__7_PRESENT 1
#define hainan__GPU__GDS__NUM_BANKS__8_PRESENT 1
#define hainan__GPU__GDS__NUM_BANKS__9_PRESENT 1
#define hainan__GPU__GDS__NUM_BANKS__10_PRESENT 1
#define hainan__GPU__GDS__NUM_BANKS__11_PRESENT 1
#define hainan__GPU__GDS__NUM_BANKS__12_PRESENT 1
#define hainan__GPU__GDS__NUM_BANKS__13_PRESENT 1
#define hainan__GPU__GDS__NUM_BANKS__14_PRESENT 1
#define hainan__GPU__GDS__NUM_BANKS__15_PRESENT 1
#define hainan__GPU__GDS__NUM_OA_COUNTERS 4
#define hainan__GPU__GDS__NUM_OA_COUNTERS__4 1
#define hainan__GPU__RLC__LARGE_UCODE_RAM 1
#define hainan__GPU__RLC__LARGE_UCODE_RAM__1 1
#define hainan__GPU__RLC__LARGE_SCRATCH_RAM 1
#define hainan__GPU__RLC__LARGE_SCRATCH_RAM__1 1
#define hainan__GPU__RLC__GFX_POWER_GATING 0
#define hainan__GPU__RLC__GFX_POWER_GATING__0 1
#define hainan__GPU__GC__SC_BCI_16_SAMPLE_PER_PIXEL 1
#define hainan__GPU__GC__SC_BCI_16_SAMPLE_PER_PIXEL__1 1
#define hainan__GPU__GC__TMP_USE_RASTER_CONFIG 1
#define hainan__GPU__GC__TMP_USE_RASTER_CONFIG__1 1
#define hainan__GPU__GC__FLT_NORM_0_6 0
#define hainan__GPU__GC__FLT_NORM_0_6__0 1
#define hainan__GPU__IO__PCIE_PHY falcon65g16x
#define hainan__GPU__IO__PCIE_PHY__FALCON65G16X 1
#define hainan__GPU__IO__DVP_SUBMOD io_r
#define hainan__GPU__IO__DVP_SUBMOD__IO_R 1
#define hainan__GPU__IO__SYNC_SUBMOD io_b
#define hainan__GPU__IO__SYNC_SUBMOD__IO_B 1
#define hainan__GPU__IO__GENERICA_SUBMOD io_b
#define hainan__GPU__IO__GENERICA_SUBMOD__IO_B 1
#define hainan__GPU__IO__GENERICB_SUBMOD io_b
#define hainan__GPU__IO__GENERICB_SUBMOD__IO_B 1
#define hainan__GPU__IO__GENERICC_SUBMOD io_b
#define hainan__GPU__IO__GENERICC_SUBMOD__IO_B 1
#define hainan__GPU__IO__GENERICD_SUBMOD io_b
#define hainan__GPU__IO__GENERICD_SUBMOD__IO_B 1
#define hainan__GPU__IO__GENERICE_SUBMOD io_b
#define hainan__GPU__IO__GENERICE_SUBMOD__IO_B 1
#define hainan__GPU__IO__GENERICF_SUBMOD io_b
#define hainan__GPU__IO__GENERICF_SUBMOD__IO_B 1
#define hainan__GPU__IO__GENERICG_SUBMOD io_b
#define hainan__GPU__IO__GENERICG_SUBMOD__IO_B 1
#define hainan__GPU__IO__VID_SUBMOD io_r
#define hainan__GPU__IO__VID_SUBMOD__IO_R 1
#define hainan__GPU__IO__GPIO_SUBMOD io_b
#define hainan__GPU__IO__GPIO_SUBMOD__IO_B 1
#define hainan__GPU__IO__PLL_SUBMOD io_b
#define hainan__GPU__IO__PLL_SUBMOD__IO_B 1
#define hainan__GPU__IO__SPLL_SUBMOD io_b
#define hainan__GPU__IO__SPLL_SUBMOD__IO_B 1
#define hainan__GPU__IO__UPLL_SUBMOD io_b
#define hainan__GPU__IO__UPLL_SUBMOD__IO_B 1
#define hainan__GPU__IO__HPD_SUBMOD io_b
#define hainan__GPU__IO__HPD_SUBMOD__IO_B 1
#define hainan__GPU__IO__I2C_SUBMOD io_b
#define hainan__GPU__IO__I2C_SUBMOD__IO_B 1
#define hainan__GPU__IO__ASAT_45_PLL 1
#define hainan__GPU__IO__ASAT_45_PLL__1 1
#define hainan__GPU__IO__PWRGOOD 1
#define hainan__GPU__IO__PWRGOOD__1 1
#define hainan__GPU__IO__NUM_MPLL 2
#define hainan__GPU__IO__NUM_MPLL__2 1
#define hainan__GPU__IO__READY 1
#define hainan__GPU__IO__READY__1 1
#define hainan__GPU__MC__NUM_MCB_BLOCKS 1
#define hainan__GPU__MC__NUM_MCB_BLOCKS__1 1
#define hainan__GPU__MC__NUM_MCB_BLOCKS__0_PRESENT 1
#define hainan__GPU__MC__NUM_MCB_TILES 1
#define hainan__GPU__MC__NUM_MCB_TILES__1 1
#define hainan__GPU__MC__NUM_MCB_TILES__0_PRESENT 1
#define hainan__GPU__MC__NUM_MCD_BLOCKS 1
#define hainan__GPU__MC__NUM_MCD_BLOCKS__1 1
#define hainan__GPU__MC__NUM_MCD_BLOCKS__0_PRESENT 1
#define hainan__GPU__MC__NUM_MCC_BLOCKS 1
#define hainan__GPU__MC__NUM_MCC_BLOCKS__1 1
#define hainan__GPU__MC__NUM_MCC_BLOCKS__0_PRESENT 1
#define hainan__GPU__MC__NUM_MCT_TILES 1
#define hainan__GPU__MC__NUM_MCT_TILES__1 1
#define hainan__GPU__MC__NUM_IO_CHNLS 2
#define hainan__GPU__MC__NUM_IO_CHNLS__2 1
#define hainan__GPU__MC__NUM_IO_CHNLS__0_PRESENT 1
#define hainan__GPU__MC__NUM_IO_CHNLS__1_PRESENT 1
#define hainan__GPU__MC__CDRRDBK 6
#define hainan__GPU__MC__CDRRDBK__6 1
#define hainan__GPU__MC__NUM_RPB_EFF_QUEUES 2
#define hainan__GPU__MC__NUM_RPB_EFF_QUEUES__2 1
#define hainan__GPU__MC__MCD0_BLOCK 1
#define hainan__GPU__MC__MCD0_BLOCK__1 1
#define hainan__GPU__MC__MCC0_BLOCK 1
#define hainan__GPU__MC__MCC0_BLOCK__1 1
#define hainan__GPU__MC__MCB_BLOCK 1
#define hainan__GPU__MC__MCB_BLOCK__1 1
#define hainan__GPU__MC__ALLOW_LARRAY 0
#define hainan__GPU__MC__ALLOW_LARRAY__0 1
#define hainan__GPU__MC__MCD_SRBM_PRESENT 1
#define hainan__GPU__MC__MCD_SRBM_PRESENT__1 1
#define hainan__GPU__MC__HDP_RD_ON_GBL1 1
#define hainan__GPU__MC__HDP_RD_ON_GBL1__1 1
#define hainan__GPU__MC__TWO_GBL0_RDRET 1
#define hainan__GPU__MC__TWO_GBL0_RDRET__1 1
#define hainan__GPU__MC__NUM_OF_RB_PER_MCD 1
#define hainan__GPU__MC__NUM_OF_RB_PER_MCD__1 1
#define hainan__GPU__MC__NUM_TC_PER_MCD 2
#define hainan__GPU__MC__NUM_TC_PER_MCD__2 1
#define hainan__GPU__MC__NUM_TCCS 2
#define hainan__GPU__MC__NUM_TCCS__2 1
#define hainan__GPU__MC__NUM_MCD_POW2 1
#define hainan__GPU__MC__NUM_MCD_POW2__1 1
#define hainan__GPU__MC__MCD0_IO0_REP 1
#define hainan__GPU__MC__MCD0_IO0_REP__1 1
#define hainan__GPU__MC__MCD0_IO1_REP 1
#define hainan__GPU__MC__MCD0_IO1_REP__1 1
#define hainan__GPU__MC__SIMPLIFIED_BLACKOUT 1
#define hainan__GPU__MC__SIMPLIFIED_BLACKOUT__1 1
#define hainan__GPU__MC__DDR5_MCLK_DEFAULT 5
#define hainan__GPU__MC__DDR5_MCLK_DEFAULT__5 1
#define hainan__GPU__MC__XBAR_REMAP 0
#define hainan__GPU__MC__XBAR_REMAP__0 1
#define hainan__GPU__MC__GPU_VIRTUAL_ADDRESS_WIDTH 40
#define hainan__GPU__MC__GPU_VIRTUAL_ADDRESS_WIDTH__40 1
#define hainan__GPU__MC__GPU_PHYSICAL_ADDRESS_WIDTH 40
#define hainan__GPU__MC__GPU_PHYSICAL_ADDRESS_WIDTH__40 1
#define hainan__GPU__MC__PCIE_VIRTUAL_ADDRESS_WIDTH 48
#define hainan__GPU__MC__PCIE_VIRTUAL_ADDRESS_WIDTH__48 1
#define hainan__GPU__MC__PCIE_PHYSICAL_ADDRESS_WIDTH 48
#define hainan__GPU__MC__PCIE_PHYSICAL_ADDRESS_WIDTH__48 1
#define hainan__GPU__MC__SPLIT_TILES 1
#define hainan__GPU__MC__SPLIT_TILES__1 1
#define hainan__GPU__MC__FUSION_FEATURE_ONLY 0
#define hainan__GPU__MC__FUSION_FEATURE_ONLY__0 1
#define hainan__GPU__MC__POWER_GATING 1
#define hainan__GPU__MC__POWER_GATING__1 1
#define hainan__GPU__MC__NUM_PGFSM_BLOCKS 3
#define hainan__GPU__MC__NUM_PGFSM_BLOCKS__3 1
#define hainan__GPU__MC__PHY_POWER_GATING 1
#define hainan__GPU__MC__PHY_POWER_GATING__1 1
#define hainan__GPU__MC__LOWSPEED_MEMPHY 1
#define hainan__GPU__MC__LOWSPEED_MEMPHY__1 1
#define hainan__GPU__MC__PAB_EXISTS 0
#define hainan__GPU__MC__PAB_EXISTS__0 1
#define hainan__GPU__VID__PRESENT 0
#define hainan__GPU__VID__PRESENT__0 1
#define hainan__GPU__DC__PRESENT 0
#define hainan__GPU__DC__PRESENT__0 1
#define hainan__GPU__AVP__PRESENT 0
#define hainan__GPU__AVP__PRESENT__0 1
#define hainan__GPU__UVD__PRESENT 0
#define hainan__GPU__UVD__PRESENT__0 1
#define hainan__ENV__GPU__UVD__HAVE_RTL 0
#define hainan__ENV__GPU__UVD__HAVE_RTL__0 1
#define hainan__ENV__GPU__MC__HAVE_BFM 1
#define hainan__ENV__GPU__MC__HAVE_BFM__1 1
#define hainan__ENV__GPU__MC__HAVE_RTL 0
#define hainan__ENV__GPU__MC__HAVE_RTL__0 1
#define hainan__GPU__UVD__PROJ_LARK 1
#define hainan__GPU__UVD__PROJ_LARK__1 1
#define hainan__GPU__UVD__CTX_ENABLE 1
#define hainan__GPU__UVD__CTX_ENABLE__1 1
#define hainan__GPU__UVD__MC_7XX 1
#define hainan__GPU__UVD__MC_7XX__1 1
#define hainan__GPU__UVD__CGC_CGTT_LOCAL_CLOCK_GATER 1
#define hainan__GPU__UVD__CGC_CGTT_LOCAL_CLOCK_GATER__1 1
#define hainan__GPU__MC__ARB_VM_CREDITS 32
#define hainan__GPU__MC__ARB_VM_CREDITS__32 1
#define hainan__GPU__MC__MCD_TLBS 4
#define hainan__GPU__MC__MCD_TLBS__4 1
#define hainan__GPU__MC__MCB_TLBS 3
#define hainan__GPU__MC__MCB_TLBS__3 1
#define hainan__GPU__MC__NO_STALL_ON_FAULT 1
#define hainan__GPU__MC__NO_STALL_ON_FAULT__1 1
#define hainan__GPU__MC__VMC_CACHES 2
#define hainan__GPU__MC__VMC_CACHES__2 1
#define hainan__GPU__MC__BIGK_CACHE_SIZE 4
#define hainan__GPU__MC__BIGK_CACHE_SIZE__4 1
#define hainan__GPU__MC__MCB_TLB0_CAM 5
#define hainan__GPU__MC__MCB_TLB0_CAM__5 1
#define hainan__GPU__MC__MCB_TLB1_CAM 4
#define hainan__GPU__MC__MCB_TLB1_CAM__4 1
#define hainan__GPU__MC__MCB_TLB2_CAM 4
#define hainan__GPU__MC__MCB_TLB2_CAM__4 1
#define hainan__GPU__MC__MCD_TLB0_CAM 4
#define hainan__GPU__MC__MCD_TLB0_CAM__4 1
#define hainan__GPU__MC__MCD_TLB1_CAM 4
#define hainan__GPU__MC__MCD_TLB1_CAM__4 1
#define hainan__GPU__MC__MCD_TLB2_CAM 4
#define hainan__GPU__MC__MCD_TLB2_CAM__4 1
#define hainan__GPU__MC__MCD_TLB3_CAM 4
#define hainan__GPU__MC__MCD_TLB3_CAM__4 1
#define hainan__GPU__MC__SEND_FREE_AT_RTN 1
#define hainan__GPU__MC__SEND_FREE_AT_RTN__1 1
#define hainan__GPU__MC__CONTEXT_WIDTH 3
#define hainan__GPU__MC__CONTEXT_WIDTH__3 1
#define hainan__GPU__MC__BUG_159204_EXISTS 1
#define hainan__GPU__MC__BUG_159204_EXISTS__1 1
#endif
projects/rocr-runtime/runtime/hsa-ext-aql-profile/gfxip/gfx8/features_oland.h
+979
Просмотреть файл
@@ -0,0 +1,979 @@
#ifndef oland____GPU_FEATURES_H__
#define oland____GPU_FEATURES_H__
#define oland__GPU__BIF__VC_PRESENT 0
#define oland__GPU__BIF__VC_PRESENT__0 1
#define oland__GPU__BIF__PCIEGEN2_MCB_DEPTH 96
#define oland__GPU__BIF__PCIEGEN2_MCB_DEPTH__96 1
#define oland__GPU__BIF__CLKBUF_PRESENT 1
#define oland__GPU__BIF__CLKBUF_PRESENT__1 1
#define oland__GPU__XSP__PRESENT 0
#define oland__GPU__XSP__PRESENT__0 1
#define oland__GPU__CHIP__DFS 1
#define oland__GPU__CHIP__DFS__1 1
#define oland__GPU__CHIP__TECH tsmc28hp
#define oland__GPU__CHIP__TECH__TSMC28HP 1
#define oland__GPU__CHIP__TECHVER B .0.5
#define oland__GPU__CHIP__TECHVER__B_0_5 1
#define oland__TOOLS__GUTS__TECHNM tsmc28hp
#define oland__TOOLS__GUTS__TECHNM__TSMC28HP 1
#define oland__TOOLS__GUTS__MEMTECH 28nm
#define oland__TOOLS__GUTS__MEMTECH__28NM 1
#define oland__TOOLS__GUTS__LARRVENDOR AMD
#define oland__TOOLS__GUTS__LARRVENDOR__AMD 1
#define oland__TOOLS__GUTS__MEMFABTECH TSMC28
#define oland__TOOLS__GUTS__MEMFABTECH__TSMC28 1
#define oland__TOOLS__GUTS__MEMVENDOR Virage
#define oland__TOOLS__GUTS__MEMVENDOR__VIRAGE 1
#define oland__TOOLS__GUTS__MEMTYPE slow
#define oland__TOOLS__GUTS__MEMTYPE__SLOW 1
#define oland__TOOLS__GUTS__MEMVER 1_0
#define oland__TOOLS__GUTS__MEMVER__1_0 1
#define oland__TOOLS__GUTS__LARRTYPE default
#define oland__TOOLS__GUTS__LARRTYPE__DEFAULT 1
#define oland__TOOLS__GUTS__LARRVER 0_6ola
#define oland__TOOLS__GUTS__LARRVER__0_6OLA 1
#define oland__TOOLS__GUTS__TECHVER B .0.5
#define oland__TOOLS__GUTS__TECHVER__B_0_5 1
#define oland__TOOLS__GUTS__MEMVIEWVER 0_2
#define oland__TOOLS__GUTS__MEMVIEWVER__0_2 1
#define oland__GPU__CHIP__MEMTECH 28nm
#define oland__GPU__CHIP__MEMTECH__28NM 1
#define oland__GPU__CHIP__MEMVIEWVER 0_2
#define oland__GPU__CHIP__MEMVIEWVER__0_2 1
#define oland__GPU__CHIP__MEM virage
#define oland__GPU__CHIP__MEM__VIRAGE 1
#define oland__GPU__CHIP__MEMVENDOR Virage
#define oland__GPU__CHIP__MEMVENDOR__VIRAGE 1
#define oland__GPU__CHIP__SRAM_MEMFABTECH TSMC28
#define oland__GPU__CHIP__SRAM_MEMFABTECH__TSMC28 1
#define oland__GPU__CHIP__LARR_MEMWRAPPERVER 0_1
#define oland__GPU__CHIP__LARR_MEMWRAPPERVER__0_1 1
#define oland__GPU__CHIP__SRAM_MEMWRAPPERVER 0_1
#define oland__GPU__CHIP__SRAM_MEMWRAPPERVER__0_1 1
#define oland__GPU__CHIP__SRAM_TIMING slow
#define oland__GPU__CHIP__SRAM_TIMING__SLOW 1
#define oland__GPU__CHIP__SRAM_MEMVER 1_0_1
#define oland__GPU__CHIP__SRAM_MEMVER__1_0_1 1
#define oland__GPU__CHIP__LARRVENDOR AMD
#define oland__GPU__CHIP__LARRVENDOR__AMD 1
#define oland__GPU__CHIP__LARR_MEMFABTECH TSMC28
#define oland__GPU__CHIP__LARR_MEMFABTECH__TSMC28 1
#define oland__GPU__CHIP__LARR_TIMING default
#define oland__GPU__CHIP__LARR_TIMING__DEFAULT 1
#define oland__GPU__CHIP__LARR_MEMVER 0_6ola
#define oland__GPU__CHIP__LARR_MEMVER__0_6OLA 1
#define oland__GPU__CHIP__MEMFABTECH TSMC28
#define oland__GPU__CHIP__MEMFABTECH__TSMC28 1
#define oland__GPU__CHIP__MEMVER 1_0
#define oland__GPU__CHIP__MEMVER__1_0 1
#define oland__GPU__CHIP__MEMTYPE slow
#define oland__GPU__CHIP__MEMTYPE__SLOW 1
#define oland__GPU__CHIP__LARRVER 0_6ola
#define oland__GPU__CHIP__LARRVER__0_6OLA 1
#define oland__GPU__CHIP__LARRTYPE default
#define oland__GPU__CHIP__LARRTYPE__DEFAULT 1
#define oland__GPU__CHIP__TILES_PRESENT 0
#define oland__GPU__CHIP__TILES_PRESENT__0 1
#define oland__GPU__CHIP__SMSGCOUNT 2
#define oland__GPU__CHIP__SMSGCOUNT__2 1
#define oland__GPU__CHIP__SMSG_0_PRESENT 1
#define oland__GPU__CHIP__SMSG_0_PRESENT__1 1
#define oland__GPU__CHIP__SMSG_1_PRESENT 1
#define oland__GPU__CHIP__SMSG_1_PRESENT__1 1
#define oland__GPU__CHIP__SMSG_2_PRESENT 0
#define oland__GPU__CHIP__SMSG_2_PRESENT__0 1
#define oland__GPU__CHIP__SMSG_3_PRESENT 0
#define oland__GPU__CHIP__SMSG_3_PRESENT__0 1
#define oland__GPU__CHIP__SMSG_FOR_BL 1
#define oland__GPU__CHIP__SMSG_FOR_BL__1 1
#define oland__GPU__CHIP__SMSG_FOR_TR 0
#define oland__GPU__CHIP__SMSG_FOR_TR__0 1
#define oland__GPU__CHIP__TCB_DEPTH 512
#define oland__GPU__CHIP__TCB_DEPTH__512 1
#define oland__GPU__CHIP__XCLK_MHZ 25
#define oland__GPU__CHIP__XCLK_MHZ__25 1
#define oland__GPU__LBIST__PRESENT 0
#define oland__GPU__LBIST__PRESENT__0 1
#define oland__GPU__CHIP__BACO 1
#define oland__GPU__CHIP__BACO__1 1
#define oland__GPU__CEC__PRESENT 1
#define oland__GPU__CEC__PRESENT__1 1
#define oland__GPU__CHIP__REAL_RDL_READY 1
#define oland__GPU__CHIP__REAL_RDL_READY__1 1
#define oland__GPU__CHIP__INFERRED_REPS 1
#define oland__GPU__CHIP__INFERRED_REPS__1 1
#define oland__GPU__CHIP__DRMDMA_POWERGATE 0
#define oland__GPU__CHIP__DRMDMA_POWERGATE__0 1
#define oland__GPU__CHIP__EDCMEM1 0
#define oland__GPU__CHIP__EDCMEM1__0 1
#define oland__GPU__CHIP__POWERGATE 0
#define oland__GPU__CHIP__POWERGATE__0 1
#define oland__GPU__THM__CMON_PRESENT 1
#define oland__GPU__THM__CMON_PRESENT__1 1
#define oland__GPU__TMON0__LEFT_NUM_RDI 6
#define oland__GPU__TMON0__LEFT_NUM_RDI__6 1
#define oland__GPU__TMON0__RIGHT_NUM_RDI 6
#define oland__GPU__TMON0__RIGHT_NUM_RDI__6 1
#define oland__GPU__DFT__IBIZA_TMON 1
#define oland__GPU__DFT__IBIZA_TMON__1 1
#define oland__GPU__CHIP__MEM_POWER_CTRL 17
#define oland__GPU__CHIP__MEM_POWER_CTRL__17 1
#define oland__GPU__CHIP__MEM_POWER_CTRL_LS 0
#define oland__GPU__CHIP__MEM_POWER_CTRL_LS__0 1
#define oland__GPU__CHIP__MEM_POWER_CTRL_DS_D 1
#define oland__GPU__CHIP__MEM_POWER_CTRL_DS_D__1 1
#define oland__GPU__CHIP__MEM_POWER_CTRL_DS_M 2
#define oland__GPU__CHIP__MEM_POWER_CTRL_DS_M__2 1
#define oland__GPU__CHIP__MEM_POWER_CTRL_SD_D 3
#define oland__GPU__CHIP__MEM_POWER_CTRL_SD_D__3 1
#define oland__GPU__CHIP__MEM_POWER_CTRL_SD_M 4
#define oland__GPU__CHIP__MEM_POWER_CTRL_SD_M__4 1
#define oland__GPU__CHIP__MEM_POWER_CTRL_DS 5
#define oland__GPU__CHIP__MEM_POWER_CTRL_DS__5 1
#define oland__GPU__CHIP__MEM_POWER_CTRL_SD 6
#define oland__GPU__CHIP__MEM_POWER_CTRL_SD__6 1
#define oland__GPU__CHIP__MEM_POWER_CTRL_FISO 7
#define oland__GPU__CHIP__MEM_POWER_CTRL_FISO__7 1
#define oland__GPU__CHIP__MEM_POWER_CTRL_V_RM_START 8
#define oland__GPU__CHIP__MEM_POWER_CTRL_V_RM_START__8 1
#define oland__GPU__CHIP__MEM_POWER_CTRL_V_RM_END 16
#define oland__GPU__CHIP__MEM_POWER_CTRL_V_RM_END__16 1
#define oland__GPU__CHIP__MEM_POWER_CTRL_A_RM_START 8
#define oland__GPU__CHIP__MEM_POWER_CTRL_A_RM_START__8 1
#define oland__GPU__CHIP__MEM_POWER_CTRL_A_RM_END 30
#define oland__GPU__CHIP__MEM_POWER_CTRL_A_RM_END__30 1
#define oland__GPU__CHIP__MEM_POWER_CTRL_V_RM_RF_RME 8
#define oland__GPU__CHIP__MEM_POWER_CTRL_V_RM_RF_RME__8 1
#define oland__GPU__CHIP__MEM_POWER_CTRL_V_RM_RF_RM_START 9
#define oland__GPU__CHIP__MEM_POWER_CTRL_V_RM_RF_RM_START__9 1
#define oland__GPU__CHIP__MEM_POWER_CTRL_V_RM_RF_RM_END 10
#define oland__GPU__CHIP__MEM_POWER_CTRL_V_RM_RF_RM_END__10 1
#define oland__GPU__CHIP__MEM_POWER_CTRL_V_RM_PDP_RME 11
#define oland__GPU__CHIP__MEM_POWER_CTRL_V_RM_PDP_RME__11 1
#define oland__GPU__CHIP__MEM_POWER_CTRL_V_RM_PDP_RM_START 12
#define oland__GPU__CHIP__MEM_POWER_CTRL_V_RM_PDP_RM_START__12 1
#define oland__GPU__CHIP__MEM_POWER_CTRL_V_RM_PDP_RM_END 13
#define oland__GPU__CHIP__MEM_POWER_CTRL_V_RM_PDP_RM_END__13 1
#define oland__GPU__CHIP__MEM_POWER_CTRL_V_RM_HD_RME 14
#define oland__GPU__CHIP__MEM_POWER_CTRL_V_RM_HD_RME__14 1
#define oland__GPU__CHIP__MEM_POWER_CTRL_V_RM_HD_RM_START 15
#define oland__GPU__CHIP__MEM_POWER_CTRL_V_RM_HD_RM_START__15 1
#define oland__GPU__CHIP__MEM_POWER_CTRL_V_RM_HD_RM_END 16
#define oland__GPU__CHIP__MEM_POWER_CTRL_V_RM_HD_RM_END__16 1
#define oland__GPU__CHIP__MEM_POWER_CTRL_A_RM_RF_RME 8
#define oland__GPU__CHIP__MEM_POWER_CTRL_A_RM_RF_RME__8 1
#define oland__GPU__CHIP__MEM_POWER_CTRL_A_RM_RF_RM_START 9
#define oland__GPU__CHIP__MEM_POWER_CTRL_A_RM_RF_RM_START__9 1
#define oland__GPU__CHIP__MEM_POWER_CTRL_A_RM_RF_RM_END 17
#define oland__GPU__CHIP__MEM_POWER_CTRL_A_RM_RF_RM_END__17 1
#define oland__GPU__CHIP__MEM_POWER_CTRL_A_RM_PDP_RME 18
#define oland__GPU__CHIP__MEM_POWER_CTRL_A_RM_PDP_RME__18 1
#define oland__GPU__CHIP__MEM_POWER_CTRL_A_RM_PDP_RM_START 19
#define oland__GPU__CHIP__MEM_POWER_CTRL_A_RM_PDP_RM_START__19 1
#define oland__GPU__CHIP__MEM_POWER_CTRL_A_RM_PDP_RM_END 30
#define oland__GPU__CHIP__MEM_POWER_CTRL_A_RM_PDP_RM_END__30 1
#define oland__GPU__TSS__NUM_TILES 5
#define oland__GPU__TSS__NUM_TILES__5 1
#define oland__GPU__TSS__TSS0_TILE 1
#define oland__GPU__TSS__TSS0_TILE__1 1
#define oland__GPU__TSS__TSS1_TILE 1
#define oland__GPU__TSS__TSS1_TILE__1 1
#define oland__GPU__TSS__TSS2_TILE 1
#define oland__GPU__TSS__TSS2_TILE__1 1
#define oland__GPU__TSS__TSS3_TILE 1
#define oland__GPU__TSS__TSS3_TILE__1 1
#define oland__GPU__TSS__TSS4_TILE 1
#define oland__GPU__TSS__TSS4_TILE__1 1
#define oland__GPU__TSS__TSS4_AS_ADC 1
#define oland__GPU__TSS__TSS4_AS_ADC__1 1
#define oland__GPU__RCU__PROGRAMMABLE_RMBITS 1
#define oland__GPU__RCU__PROGRAMMABLE_RMBITS__1 1
#define oland__GPU__CGTT_TILE__PDLY 1
#define oland__GPU__CGTT_TILE__PDLY__1 1
#define oland__GPU__PDLY_TILE__PDLY 1
#define oland__GPU__PDLY_TILE__PDLY__1 1
#define oland__GPU__PDLY_TILE__CLKGATE 0
#define oland__GPU__PDLY_TILE__CLKGATE__0 1
#define oland__GPU__CG__SMC_SCRATCH_REGS 1
#define oland__GPU__CG__SMC_SCRATCH_REGS__1 1
#define oland__GPU__CG__CG_DLL_PDNB 1
#define oland__GPU__CG__CG_DLL_PDNB__1 1
#define oland__GPU__SMU__USE_HW_VBI 1
#define oland__GPU__SMU__USE_HW_VBI__1 1
#define oland__GPU__SMU__NUM_CAC_MGR_4 1
#define oland__GPU__SMU__NUM_CAC_MGR_4__1 1
#define oland__GPU__PDMA__PRESENT 0
#define oland__GPU__PDMA__PRESENT__0 1
#define oland__GPU__DRMDMA__DUAL_DRMDMA_PRESENT 1
#define oland__GPU__DRMDMA__DUAL_DRMDMA_PRESENT__1 1
#define oland__GPU__DRM__BGAES_OFF 1
#define oland__GPU__DRM__BGAES_OFF__1 1
#define oland__GPU__DLB__SLEW 1
#define oland__GPU__DLB__SLEW__1 1
#define oland__GPU__ROM__EXT_CS_EN 1
#define oland__GPU__ROM__EXT_CS_EN__1 1
#define oland__GPU__CPL__GPIO_23_PRESENT 0
#define oland__GPU__CPL__GPIO_23_PRESENT__0 1
#define oland__GPU__CPL__GPIO_24_PRESENT 0
#define oland__GPU__CPL__GPIO_24_PRESENT__0 1
#define oland__GPU__CPL__GPIO_25_PRESENT 0
#define oland__GPU__CPL__GPIO_25_PRESENT__0 1
#define oland__GPU__CPL__GPIO_26_PRESENT 0
#define oland__GPU__CPL__GPIO_26_PRESENT__0 1
#define oland__GPU__CPL__GPIO_27_PRESENT 0
#define oland__GPU__CPL__GPIO_27_PRESENT__0 1
#define oland__GPU__CPL__MLPS_0_PRESENT 1
#define oland__GPU__CPL__MLPS_0_PRESENT__1 1
#define oland__GPU__CPL__MLPS_1_PRESENT 1
#define oland__GPU__CPL__MLPS_1_PRESENT__1 1
#define oland__GPU__CPL__MLPS_2_PRESENT 1
#define oland__GPU__CPL__MLPS_2_PRESENT__1 1
#define oland__GPU__CPL__MLPS_3_PRESENT 1
#define oland__GPU__CPL__MLPS_3_PRESENT__1 1
#define oland__GPU__CPL__SX_0_PRESENT 1
#define oland__GPU__CPL__SX_0_PRESENT__1 1
#define oland__GPU__SMC__TAP_FED_PRESENT 1
#define oland__GPU__SMC__TAP_FED_PRESENT__1 1
#define oland__GPU__CPL__PG_CODE_ENABLE 1
#define oland__GPU__CPL__PG_CODE_ENABLE__1 1
#define oland__GPU__CPL__PG_CODE_GPG 1
#define oland__GPU__CPL__PG_CODE_GPG__1 1
#define oland__GPU__AVP__MC_IF 1
#define oland__GPU__AVP__MC_IF__1 1
#define oland__GPU__AVP__UVD_RLC_CMC_IF 1
#define oland__GPU__AVP__UVD_RLC_CMC_IF__1 1
#define oland__GPU__DC__TMDS_LINK tmds_link_dual
#define oland__GPU__DC__TMDS_LINK__TMDS_LINK_DUAL 1
#define oland__GPU__DC__NUM_DDC_PAIRS 6
#define oland__GPU__DC__NUM_DDC_PAIRS__6 1
#define oland__GPU__DC__NUM_DDC_PAIRS__0_PRESENT 1
#define oland__GPU__DC__NUM_DDC_PAIRS__1_PRESENT 1
#define oland__GPU__DC__NUM_DDC_PAIRS__2_PRESENT 1
#define oland__GPU__DC__NUM_DDC_PAIRS__3_PRESENT 1
#define oland__GPU__DC__NUM_DDC_PAIRS__4_PRESENT 1
#define oland__GPU__DC__NUM_DDC_PAIRS__5_PRESENT 1
#define oland__GPU__DC__NUM_HPD 6
#define oland__GPU__DC__NUM_HPD__6 1
#define oland__GPU__DC__NUM_HPD__0_PRESENT 1
#define oland__GPU__DC__NUM_HPD__1_PRESENT 1
#define oland__GPU__DC__NUM_HPD__2_PRESENT 1
#define oland__GPU__DC__NUM_HPD__3_PRESENT 1
#define oland__GPU__DC__NUM_HPD__4_PRESENT 1
#define oland__GPU__DC__NUM_HPD__5_PRESENT 1
#define oland__GPU__DC__NUM_PIPE_PAIRS 3
#define oland__GPU__DC__NUM_PIPE_PAIRS__3 1
#define oland__GPU__DC__NUM_PIPE_PAIRS__0_PRESENT 1
#define oland__GPU__DC__NUM_PIPE_PAIRS__1_PRESENT 1
#define oland__GPU__DC__NUM_PIPE_PAIRS__2_PRESENT 1
#define oland__GPU__DC__NUM_PIPES 6
#define oland__GPU__DC__NUM_PIPES__6 1
#define oland__GPU__DC__NUM_PIPES__0_PRESENT 1
#define oland__GPU__DC__NUM_PIPES__1_PRESENT 1
#define oland__GPU__DC__NUM_PIPES__2_PRESENT 1
#define oland__GPU__DC__NUM_PIPES__3_PRESENT 1
#define oland__GPU__DC__NUM_PIPES__4_PRESENT 1
#define oland__GPU__DC__NUM_PIPES__5_PRESENT 1
#define oland__GPU__DC__NUM_DIG 6
#define oland__GPU__DC__NUM_DIG__6 1
#define oland__GPU__DC__NUM_DIG__0_PRESENT 1
#define oland__GPU__DC__NUM_DIG__1_PRESENT 1
#define oland__GPU__DC__NUM_DIG__2_PRESENT 1
#define oland__GPU__DC__NUM_DIG__3_PRESENT 1
#define oland__GPU__DC__NUM_DIG__4_PRESENT 1
#define oland__GPU__DC__NUM_DIG__5_PRESENT 1
#define oland__GPU__DC__NUM_AUX 6
#define oland__GPU__DC__NUM_AUX__6 1
#define oland__GPU__DC__NUM_AUX__0_PRESENT 1
#define oland__GPU__DC__NUM_AUX__1_PRESENT 1
#define oland__GPU__DC__NUM_AUX__2_PRESENT 1
#define oland__GPU__DC__NUM_AUX__3_PRESENT 1
#define oland__GPU__DC__NUM_AUX__4_PRESENT 1
#define oland__GPU__DC__NUM_AUX__5_PRESENT 1
#define oland__GPU__DISPPLL__MACRO walden
#define oland__GPU__DISPPLL__MACRO__WALDEN 1
#define oland__GPU__TMDPA__MACRO walden
#define oland__GPU__TMDPA__MACRO__WALDEN 1
#define oland__GPU__TMDPB__MACRO walden
#define oland__GPU__TMDPB__MACRO__WALDEN 1
#define oland__GPU__LVTMDP__MACRO walden
#define oland__GPU__LVTMDP__MACRO__WALDEN 1
#define oland__GPU__DACA__MACRO walden
#define oland__GPU__DACA__MACRO__WALDEN 1
#define oland__GPU__DACB__MACRO walden
#define oland__GPU__DACB__MACRO__WALDEN 1
#define oland__GPU__DC__VIP_PRESENT 1
#define oland__GPU__DC__VIP_PRESENT__1 1
#define oland__GPU__DC__ABM_PRESENT 1
#define oland__GPU__DC__ABM_PRESENT__1 1
#define oland__GPU__DC__DMCU_PRESENT 1
#define oland__GPU__DC__DMCU_PRESENT__1 1
#define oland__GPU__DC__DVO_PRESENT 1
#define oland__GPU__DC__DVO_PRESENT__1 1
#define oland__GPU__DC__SDVO_PRESENT 1
#define oland__GPU__DC__SDVO_PRESENT__1 1
#define oland__GPU__DC__LVDS_PRESENT 1
#define oland__GPU__DC__LVDS_PRESENT__1 1
#define oland__GPU__UNIPHYAB__PRESENT 1
#define oland__GPU__UNIPHYAB__PRESENT__1 1
#define oland__GPU__UNIPHYCD__PRESENT 1
#define oland__GPU__UNIPHYCD__PRESENT__1 1
#define oland__GPU__UNIPHYEF__PRESENT 1
#define oland__GPU__UNIPHYEF__PRESENT__1 1
#define oland__GPU__UNIPHYAB__TYPE lvtmdp
#define oland__GPU__UNIPHYAB__TYPE__LVTMDP 1
#define oland__GPU__UNIPHYCD__TYPE tmdpa
#define oland__GPU__UNIPHYCD__TYPE__TMDPA 1
#define oland__GPU__UNIPHYEF__TYPE tmdpb
#define oland__GPU__UNIPHYEF__TYPE__TMDPB 1
#define oland__GPU__UNIPHYAB__LVTMDP 1
#define oland__GPU__UNIPHYAB__LVTMDP__1 1
#define oland__GPU__DC__DACA_PRESENT 1
#define oland__GPU__DC__DACA_PRESENT__1 1
#define oland__GPU__DC__DACB_PRESENT 1
#define oland__GPU__DC__DACB_PRESENT__1 1
#define oland__GPU__DC__TVOUT_PRESENT 1
#define oland__GPU__DC__TVOUT_PRESENT__1 1
#define oland__GPU__DC__MVP_PRESENT 1
#define oland__GPU__DC__MVP_PRESENT__1 1
#define oland__GPU__DC__DENTIST_INTERFACE_PRESENT 0
#define oland__GPU__DC__DENTIST_INTERFACE_PRESENT__0 1
#define oland__GPU__DC__DDC1AUX1 dual_mode
#define oland__GPU__DC__DDC1AUX1__DUAL_MODE 1
#define oland__GPU__DC__DDC2AUX2 dual_mode
#define oland__GPU__DC__DDC2AUX2__DUAL_MODE 1
#define oland__GPU__DC__DDC3AUX3 dual_mode
#define oland__GPU__DC__DDC3AUX3__DUAL_MODE 1
#define oland__GPU__DC__DDC4AUX4 dual_mode
#define oland__GPU__DC__DDC4AUX4__DUAL_MODE 1
#define oland__GPU__DC__DDC5AUX5 dual_mode
#define oland__GPU__DC__DDC5AUX5__DUAL_MODE 1
#define oland__GPU__DC__DDC6AUX6 dual_mode
#define oland__GPU__DC__DDC6AUX6__DUAL_MODE 1
#define oland__GPU__DC__AUX1_PRESENT 1
#define oland__GPU__DC__AUX1_PRESENT__1 1
#define oland__GPU__DC__AUX2_PRESENT 1
#define oland__GPU__DC__AUX2_PRESENT__1 1
#define oland__GPU__DC__AUX3_PRESENT 1
#define oland__GPU__DC__AUX3_PRESENT__1 1
#define oland__GPU__DC__AUX4_PRESENT 1
#define oland__GPU__DC__AUX4_PRESENT__1 1
#define oland__GPU__DC__AUX5_PRESENT 1
#define oland__GPU__DC__AUX5_PRESENT__1 1
#define oland__GPU__DC__AUX6_PRESENT 1
#define oland__GPU__DC__AUX6_PRESENT__1 1
#define oland__GPU__DC__DENTIST_PRESENT 0
#define oland__GPU__DC__DENTIST_PRESENT__0 1
#define oland__GPU__DC__GENERICA_PRESENT 1
#define oland__GPU__DC__GENERICA_PRESENT__1 1
#define oland__GPU__DC__GENERICB_PRESENT 1
#define oland__GPU__DC__GENERICB_PRESENT__1 1
#define oland__GPU__DC__GENERICC_PRESENT 1
#define oland__GPU__DC__GENERICC_PRESENT__1 1
#define oland__GPU__DC__GENERICD_PRESENT 1
#define oland__GPU__DC__GENERICD_PRESENT__1 1
#define oland__GPU__DC__GENERICE_PRESENT 1
#define oland__GPU__DC__GENERICE_PRESENT__1 1
#define oland__GPU__DC__GENERICF_PRESENT 1
#define oland__GPU__DC__GENERICF_PRESENT__1 1
#define oland__GPU__DC__GENERICG_PRESENT 1
#define oland__GPU__DC__GENERICG_PRESENT__1 1
#define oland__GPU__DC__BLON_TYPE 0
#define oland__GPU__DC__BLON_TYPE__0 1
#define oland__GPU__DC__NB_STUTTER_MODE_PRESENT 0
#define oland__GPU__DC__NB_STUTTER_MODE_PRESENT__0 1
#define oland__GPU__DC__PCIE_REFCLK_TEST_MODE_MUX_PRESENT 0
#define oland__GPU__DC__PCIE_REFCLK_TEST_MODE_MUX_PRESENT__0 1
#define oland__GPU__DC__REFCLK_TEST_MODE_MUX_PRESENT 0
#define oland__GPU__DC__REFCLK_TEST_MODE_MUX_PRESENT__0 1
#define oland__GPU__DC__PIXCLK_TEST_MODE_MUX_PRESENT 0
#define oland__GPU__DC__PIXCLK_TEST_MODE_MUX_PRESENT__0 1
#define oland__GPU__DC__SYMCLK_TEST_MODE_MUX_PRESENT 0
#define oland__GPU__DC__SYMCLK_TEST_MODE_MUX_PRESENT__0 1
#define oland__GPU__GC__NUM_SE 1
#define oland__GPU__GC__NUM_SE__1 1
#define oland__GPU__GC__NUM_SE__0_PRESENT 1
#define oland__GPU__GC__NUM_SH_PER_SE 1
#define oland__GPU__GC__NUM_SH_PER_SE__1 1
#define oland__GPU__GC__NUM_SH_PER_SE__0_PRESENT 1
#define oland__GPU__GC__NUM_RB_PER_SE 2
#define oland__GPU__GC__NUM_RB_PER_SE__2 1
#define oland__GPU__GC__NUM_RB_PER_SE__0_PRESENT 1
#define oland__GPU__GC__NUM_RB_PER_SE__1_PRESENT 1
#define oland__GPU__GC__NUM_CU_PER_SH 6
#define oland__GPU__GC__NUM_CU_PER_SH__6 1
#define oland__GPU__GC__NUM_CU_PER_SH__0_PRESENT 1
#define oland__GPU__GC__NUM_CU_PER_SH__1_PRESENT 1
#define oland__GPU__GC__NUM_CU_PER_SH__2_PRESENT 1
#define oland__GPU__GC__NUM_CU_PER_SH__3_PRESENT 1
#define oland__GPU__GC__NUM_CU_PER_SH__4_PRESENT 1
#define oland__GPU__GC__NUM_CU_PER_SH__5_PRESENT 1
#define oland__GPU__GC__WAVE_SIZE 64
#define oland__GPU__GC__WAVE_SIZE__64 1
#define oland__GPU__GC__NUM_CP_RINGS 3
#define oland__GPU__GC__NUM_CP_RINGS__3 1
#define oland__GPU__GC__NUM_CP_RINGS__0_PRESENT 1
#define oland__GPU__GC__NUM_CP_RINGS__1_PRESENT 1
#define oland__GPU__GC__NUM_CP_RINGS__2_PRESENT 1
#define oland__GPU__GC__NUM_SC_PER_SE 1
#define oland__GPU__GC__NUM_SC_PER_SE__1 1
#define oland__GPU__GC__NUM_SC_PER_SE__0_PRESENT 1
#define oland__GPU__GC__NUM_BCI_PER_SE 1
#define oland__GPU__GC__NUM_BCI_PER_SE__1 1
#define oland__GPU__GC__NUM_BCI_PER_SE__0_PRESENT 1
#define oland__GPU__GC__NUM_RB_PER_SC 2
#define oland__GPU__GC__NUM_RB_PER_SC__2 1
#define oland__GPU__GC__NUM_RB_PER_SC__0_PRESENT 1
#define oland__GPU__GC__NUM_RB_PER_SC__1_PRESENT 1
#define oland__GPU__GC__NUM_RB_PER_PACKER 2
#define oland__GPU__GC__NUM_RB_PER_PACKER__2 1
#define oland__GPU__GC__NUM_RB_PER_PACKER__0_PRESENT 1
#define oland__GPU__GC__NUM_RB_PER_PACKER__1_PRESENT 1
#define oland__GPU__GC__NUM_PACKER_PER_SC 1
#define oland__GPU__GC__NUM_PACKER_PER_SC__1 1
#define oland__GPU__GC__NUM_PACKER_PER_SC__0_PRESENT 1
#define oland__GPU__GC__NUM_DB_PER_PACKER 2
#define oland__GPU__GC__NUM_DB_PER_PACKER__2 1
#define oland__GPU__GC__NUM_DB_PER_PACKER__0_PRESENT 1
#define oland__GPU__GC__NUM_DB_PER_PACKER__1_PRESENT 1
#define oland__GPU__GC__NUM_PACKER_PER_SE 1
#define oland__GPU__GC__NUM_PACKER_PER_SE__1 1
#define oland__GPU__GC__NUM_PACKER_PER_SE__0_PRESENT 1
#define oland__GPU__GC__NUM_RB_PER_SX 2
#define oland__GPU__GC__NUM_RB_PER_SX__2 1
#define oland__GPU__GC__NUM_RB_PER_SX__0_PRESENT 1
#define oland__GPU__GC__NUM_RB_PER_SX__1_PRESENT 1
#define oland__GPU__GC__NUM_CU_PER_SE 6
#define oland__GPU__GC__NUM_CU_PER_SE__6 1
#define oland__GPU__GC__NUM_CU_PER_SE__0_PRESENT 1
#define oland__GPU__GC__NUM_CU_PER_SE__1_PRESENT 1
#define oland__GPU__GC__NUM_CU_PER_SE__2_PRESENT 1
#define oland__GPU__GC__NUM_CU_PER_SE__3_PRESENT 1
#define oland__GPU__GC__NUM_CU_PER_SE__4_PRESENT 1
#define oland__GPU__GC__NUM_CU_PER_SE__5_PRESENT 1
#define oland__GPU__GC__MAX_NUMBER_WAVES 240
#define oland__GPU__GC__MAX_NUMBER_WAVES__240 1
#define oland__GPU__GC__MAX_NUMBER_WAVES_PER_PACKER 240
#define oland__GPU__GC__MAX_NUMBER_WAVES_PER_PACKER__240 1
#define oland__GPU__SQ__NUM_WAVES_PER_SIMD 10
#define oland__GPU__SQ__NUM_WAVES_PER_SIMD__10 1
#define oland__GPU__SQ__THREAD_GROUPS_PER_CU 16
#define oland__GPU__SQ__THREAD_GROUPS_PER_CU__16 1
#define oland__GPU__SQ__NUM_PERF_CNTRS 8
#define oland__GPU__SQ__NUM_PERF_CNTRS__8 1
#define oland__GPU__SQ__NUM_PERF_CNTRS__0_PRESENT 1
#define oland__GPU__SQ__NUM_PERF_CNTRS__1_PRESENT 1
#define oland__GPU__SQ__NUM_PERF_CNTRS__2_PRESENT 1
#define oland__GPU__SQ__NUM_PERF_CNTRS__3_PRESENT 1
#define oland__GPU__SQ__NUM_PERF_CNTRS__4_PRESENT 1
#define oland__GPU__SQ__NUM_PERF_CNTRS__5_PRESENT 1
#define oland__GPU__SQ__NUM_PERF_CNTRS__6_PRESENT 1
#define oland__GPU__SQ__NUM_PERF_CNTRS__7_PRESENT 1
#define oland__GPU__SQ__NUM_SGPR_PER_SIMD 512
#define oland__GPU__SQ__NUM_SGPR_PER_SIMD__512 1
#define oland__GPU__SQ__P2_IS_P1 1
#define oland__GPU__SQ__P2_IS_P1__1 1
#define oland__GPU__SQ__USE_SV_PACKAGES 0
#define oland__GPU__SQ__USE_SV_PACKAGES__0 1
#define oland__GPU__SQ__BUG_307568_FIXED 1
#define oland__GPU__SQ__BUG_307568_FIXED__1 1
#define oland__GPU__SQC__NUM_SQC 2
#define oland__GPU__SQC__NUM_SQC__2 1
#define oland__GPU__SQC__NUM_SQC__0_PRESENT 1
#define oland__GPU__SQC__NUM_SQC__1_PRESENT 1
#define oland__GPU__SQC__NUM_SQC_PER_SH 2
#define oland__GPU__SQC__NUM_SQC_PER_SH__2 1
#define oland__GPU__SQC__NUM_SQC_PER_SH__0_PRESENT 1
#define oland__GPU__SQC__NUM_SQC_PER_SH__1_PRESENT 1
#define oland__GPU__SQC__IDENTICAL_NAMES 1
#define oland__GPU__SQC__IDENTICAL_NAMES__1 1
#define oland__GPU__SQC__SH_SQC0_POSN_AFTER_SQ 0
#define oland__GPU__SQC__SH_SQC0_POSN_AFTER_SQ__0 1
#define oland__GPU__SQC__SH_SQC0_FIRST_CONNECTED_SQ 0
#define oland__GPU__SQC__SH_SQC0_FIRST_CONNECTED_SQ__0 1
#define oland__GPU__SQC__SH_SQC0_NUM_CU 3
#define oland__GPU__SQC__SH_SQC0_NUM_CU__3 1
#define oland__GPU__SQC__SH_SQC0_NUM_CU__0_PRESENT 1
#define oland__GPU__SQC__SH_SQC0_NUM_CU__1_PRESENT 1
#define oland__GPU__SQC__SH_SQC0_NUM_CU__2_PRESENT 1
#define oland__GPU__SQC__SH_SQC0_NUM_BANK 4
#define oland__GPU__SQC__SH_SQC0_NUM_BANK__4 1
#define oland__GPU__SQC__SH_SQC0_NUM_BANK__0_PRESENT 1
#define oland__GPU__SQC__SH_SQC0_NUM_BANK__1_PRESENT 1
#define oland__GPU__SQC__SH_SQC0_NUM_BANK__2_PRESENT 1
#define oland__GPU__SQC__SH_SQC0_NUM_BANK__3_PRESENT 1
#define oland__GPU__SQC__SH_SQC0_BANK_INST_CACHE_SIZE_KBYTES 8
#define oland__GPU__SQC__SH_SQC0_BANK_INST_CACHE_SIZE_KBYTES__8 1
#define oland__GPU__SQC__SH_SQC0_BANK_DATA_CACHE_SIZE_KBYTES 4
#define oland__GPU__SQC__SH_SQC0_BANK_DATA_CACHE_SIZE_KBYTES__4 1
#define oland__GPU__SQC__SH_SQC1_POSN_AFTER_SQ 3
#define oland__GPU__SQC__SH_SQC1_POSN_AFTER_SQ__3 1
#define oland__GPU__SQC__SH_SQC1_FIRST_CONNECTED_SQ 3
#define oland__GPU__SQC__SH_SQC1_FIRST_CONNECTED_SQ__3 1
#define oland__GPU__SQC__SH_SQC1_NUM_CU 3
#define oland__GPU__SQC__SH_SQC1_NUM_CU__3 1
#define oland__GPU__SQC__SH_SQC1_NUM_CU__0_PRESENT 1
#define oland__GPU__SQC__SH_SQC1_NUM_CU__1_PRESENT 1
#define oland__GPU__SQC__SH_SQC1_NUM_CU__2_PRESENT 1
#define oland__GPU__SQC__SH_SQC1_NUM_BANK 4
#define oland__GPU__SQC__SH_SQC1_NUM_BANK__4 1
#define oland__GPU__SQC__SH_SQC1_NUM_BANK__0_PRESENT 1
#define oland__GPU__SQC__SH_SQC1_NUM_BANK__1_PRESENT 1
#define oland__GPU__SQC__SH_SQC1_NUM_BANK__2_PRESENT 1
#define oland__GPU__SQC__SH_SQC1_NUM_BANK__3_PRESENT 1
#define oland__GPU__SQC__SH_SQC1_BANK_INST_CACHE_SIZE_KBYTES 8
#define oland__GPU__SQC__SH_SQC1_BANK_INST_CACHE_SIZE_KBYTES__8 1
#define oland__GPU__SQC__SH_SQC1_BANK_DATA_CACHE_SIZE_KBYTES 4
#define oland__GPU__SQC__SH_SQC1_BANK_DATA_CACHE_SIZE_KBYTES__4 1
#define oland__GPU__SQC__SH_SQC2_POSN_AFTER_SQ 0
#define oland__GPU__SQC__SH_SQC2_POSN_AFTER_SQ__0 1
#define oland__GPU__SQC__SH_SQC2_FIRST_CONNECTED_SQ 0
#define oland__GPU__SQC__SH_SQC2_FIRST_CONNECTED_SQ__0 1
#define oland__GPU__SQC__SH_SQC2_NUM_CU 0
#define oland__GPU__SQC__SH_SQC2_NUM_CU__0 1
#define oland__GPU__SQC__SH_SQC2_NUM_BANK 0
#define oland__GPU__SQC__SH_SQC2_NUM_BANK__0 1
#define oland__GPU__SQC__SH_SQC2_BANK_INST_CACHE_SIZE_KBYTES 0
#define oland__GPU__SQC__SH_SQC2_BANK_INST_CACHE_SIZE_KBYTES__0 1
#define oland__GPU__SQC__SH_SQC2_BANK_DATA_CACHE_SIZE_KBYTES 0
#define oland__GPU__SQC__SH_SQC2_BANK_DATA_CACHE_SIZE_KBYTES__0 1
#define oland__GPU__SQC__P2_IS_P1 1
#define oland__GPU__SQC__P2_IS_P1__1 1
#define oland__GPU__SQC__BUG_303685_EXISTS 1
#define oland__GPU__SQC__BUG_303685_EXISTS__1 1
#define oland__GPU__GC__GDS_EXISTS 1
#define oland__GPU__GC__GDS_EXISTS__1 1
#define oland__GPU__GC__RB_REDUNDANCY 0
#define oland__GPU__GC__RB_REDUNDANCY__0 1
#define oland__GPU__GC__SC_DOES_RB_REDUNDANCY 0
#define oland__GPU__GC__SC_DOES_RB_REDUNDANCY__0 1
#define oland__GPU__GC__MEM_ADDR_BITS 40
#define oland__GPU__GC__MEM_ADDR_BITS__40 1
#define oland__GPU__GC__NEW_VERTEX_VECTOR_ORDER 0
#define oland__GPU__GC__NEW_VERTEX_VECTOR_ORDER__0 1
#define oland__GPU__GC__NUM_INTERPS 1
#define oland__GPU__GC__NUM_INTERPS__1 1
#define oland__GPU__GC__HZ_PRESENT 1
#define oland__GPU__GC__HZ_PRESENT__1 1
#define oland__GPU__GC__NUM_CLKS_PER_PRIM 1
#define oland__GPU__GC__NUM_CLKS_PER_PRIM__1 1
#define oland__GPU__GC__NUM_INTERP_PRIM_PER_CLK 2
#define oland__GPU__GC__NUM_INTERP_PRIM_PER_CLK__2 1
#define oland__GPU__GC__ATTR_BUS_PRIM_PER_CLK 2
#define oland__GPU__GC__ATTR_BUS_PRIM_PER_CLK__2 1
#define oland__GPU__GC__NUM_MAX_GS_THDS 16
#define oland__GPU__GC__NUM_MAX_GS_THDS__16 1
#define oland__GPU__GC__NUM_MIN_GS_THDS 4
#define oland__GPU__GC__NUM_MIN_GS_THDS__4 1
#define oland__GPU__GC__NUM_STATES 8
#define oland__GPU__GC__NUM_STATES__8 1
#define oland__GPU__GC__NUM_STATES__0_PRESENT 1
#define oland__GPU__GC__NUM_STATES__1_PRESENT 1
#define oland__GPU__GC__NUM_STATES__2_PRESENT 1
#define oland__GPU__GC__NUM_STATES__3_PRESENT 1
#define oland__GPU__GC__NUM_STATES__4_PRESENT 1
#define oland__GPU__GC__NUM_STATES__5_PRESENT 1
#define oland__GPU__GC__NUM_STATES__6_PRESENT 1
#define oland__GPU__GC__NUM_STATES__7_PRESENT 1
#define oland__GPU__GC__STWTPTR_WIDTH 3
#define oland__GPU__GC__STWTPTR_WIDTH__3 1
#define oland__GPU__SH__DOUBLE_FLOAT_PRESENT 1
#define oland__GPU__SH__DOUBLE_FLOAT_PRESENT__1 1
#define oland__GPU__SH__NUM_DOUBLE_VSPS_PER_SIMD 1
#define oland__GPU__SH__NUM_DOUBLE_VSPS_PER_SIMD__1 1
#define oland__GPU__SH__NUM_DOUBLE_VSPS_PER_SIMD__0_PRESENT 1
#define oland__GPU__SH__NORM_SIN_COS 1
#define oland__GPU__SH__NORM_SIN_COS__1 1
#define oland__GPU__SH__MICROCODE_LEVEL 10
#define oland__GPU__SH__MICROCODE_LEVEL__10 1
#define oland__GPU__SH__NUM_EXPREQ_PER_CU 12
#define oland__GPU__SH__NUM_EXPREQ_PER_CU__12 1
#define oland__GPU__GC__GLOBAL_VGT_PA 0
#define oland__GPU__GC__GLOBAL_VGT_PA__0 1
#define oland__GPU__GC__NUM_FRONTEND 1
#define oland__GPU__GC__NUM_FRONTEND__1 1
#define oland__GPU__GC__NUM_FRONTEND__0_PRESENT 1
#define oland__GPU__GC__COALESCED_READ_PRESENT 1
#define oland__GPU__GC__COALESCED_READ_PRESENT__1 1
#define oland__GPU__GC__NUM_CLKS_PER_TILE 1
#define oland__GPU__GC__NUM_CLKS_PER_TILE__1 1
#define oland__GPU__GC__DBSC_TRUE_QUAD_INTF 1
#define oland__GPU__GC__DBSC_TRUE_QUAD_INTF__1 1
#define oland__GPU__GC__ASYNC_DISPATCH 1
#define oland__GPU__GC__ASYNC_DISPATCH__1 1
#define oland__GPU__GC__VMID_PORTS_EXISTS 1
#define oland__GPU__GC__VMID_PORTS_EXISTS__1 1
#define oland__GPU__GC__NUM_EXPORT_BUS 2
#define oland__GPU__GC__NUM_EXPORT_BUS__2 1
#define oland__GPU__GC__TILING_CONFIG_TABLE 1
#define oland__GPU__GC__TILING_CONFIG_TABLE__1 1
#define oland__GPU__GC__FMASK_TILING_CONFIG_TABLE 1
#define oland__GPU__GC__FMASK_TILING_CONFIG_TABLE__1 1
#define oland__GPU__GC__NEW_SRC_COLOR_FORMAT 1
#define oland__GPU__GC__NEW_SRC_COLOR_FORMAT__1 1
#define oland__GPU__SP__NUM_GPRS 256
#define oland__GPU__SP__NUM_GPRS__256 1
#define oland__GPU__SP__GPR_ADDR_WIDTH 8
#define oland__GPU__SP__GPR_ADDR_WIDTH__8 1
#define oland__GPU__SP__WIDTH_GPRS 128
#define oland__GPU__SP__WIDTH_GPRS__128 1
#define oland__GPU__SPI__TMP_SCBD_SLOTS_PER_CU 32
#define oland__GPU__SPI__TMP_SCBD_SLOTS_PER_CU__32 1
#define oland__GPU__VGT__GSPRIM_BUFF_DEPTH 768
#define oland__GPU__VGT__GSPRIM_BUFF_DEPTH__768 1
#define oland__GPU__VGT__GS_TABLE_DEPTH 16
#define oland__GPU__VGT__GS_TABLE_DEPTH__16 1
#define oland__GPU__SX__PARAMETER_CACHE_DEPTH 512
#define oland__GPU__SX__PARAMETER_CACHE_DEPTH__512 1
#define oland__GPU__SX__PARAMETER_CACHE_WIDTH 16
#define oland__GPU__SX__PARAMETER_CACHE_WIDTH__16 1
#define oland__GPU__SX__PARAMETER_CACHE_WIDTH__0_PRESENT 1
#define oland__GPU__SX__PARAMETER_CACHE_WIDTH__1_PRESENT 1
#define oland__GPU__SX__PARAMETER_CACHE_WIDTH__2_PRESENT 1
#define oland__GPU__SX__PARAMETER_CACHE_WIDTH__3_PRESENT 1
#define oland__GPU__SX__PARAMETER_CACHE_WIDTH__4_PRESENT 1
#define oland__GPU__SX__PARAMETER_CACHE_WIDTH__5_PRESENT 1
#define oland__GPU__SX__PARAMETER_CACHE_WIDTH__6_PRESENT 1
#define oland__GPU__SX__PARAMETER_CACHE_WIDTH__7_PRESENT 1
#define oland__GPU__SX__PARAMETER_CACHE_WIDTH__8_PRESENT 1
#define oland__GPU__SX__PARAMETER_CACHE_WIDTH__9_PRESENT 1
#define oland__GPU__SX__PARAMETER_CACHE_WIDTH__10_PRESENT 1
#define oland__GPU__SX__PARAMETER_CACHE_WIDTH__11_PRESENT 1
#define oland__GPU__SX__PARAMETER_CACHE_WIDTH__12_PRESENT 1
#define oland__GPU__SX__PARAMETER_CACHE_WIDTH__13_PRESENT 1
#define oland__GPU__SX__PARAMETER_CACHE_WIDTH__14_PRESENT 1
#define oland__GPU__SX__PARAMETER_CACHE_WIDTH__15_PRESENT 1
#define oland__GPU__SX__COLOR_SCOREBOARD_SLOTS 64
#define oland__GPU__SX__COLOR_SCOREBOARD_SLOTS__64 1
#define oland__GPU__SX__POS_SCOREBOARD_SLOTS 16
#define oland__GPU__SX__POS_SCOREBOARD_SLOTS__16 1
#define oland__GPU__SX__COLOR_EXPORT_BUFFER_SIZE 256
#define oland__GPU__SX__COLOR_EXPORT_BUFFER_SIZE__256 1
#define oland__GPU__SX__POS_EXPORT_BUFFER_SIZE 256
#define oland__GPU__SX__POS_EXPORT_BUFFER_SIZE__256 1
#define oland__GPU__SX__COLOR_EXPORT_REG_BUFFER_SIZE 1024
#define oland__GPU__SX__COLOR_EXPORT_REG_BUFFER_SIZE__1024 1
#define oland__GPU__SX__POS_EXPORT_REG_BUFFER_SIZE 1024
#define oland__GPU__SX__POS_EXPORT_REG_BUFFER_SIZE__1024 1
#define oland__GPU__SX__PIXEL_FIFO_DEPTH 32
#define oland__GPU__SX__PIXEL_FIFO_DEPTH__32 1
#define oland__GPU__PA__PRIM_BUFF_DEPTH 1536
#define oland__GPU__PA__PRIM_BUFF_DEPTH__1536 1
#define oland__GPU__PA__NUM_CLIPPERS 4
#define oland__GPU__PA__NUM_CLIPPERS__4 1
#define oland__GPU__PA__LOG2_MAX_SAMPLES 3
#define oland__GPU__PA__LOG2_MAX_SAMPLES__3 1
#define oland__GPU__TA__GRBM_INTF_RESET_FIX 1
#define oland__GPU__TA__GRBM_INTF_RESET_FIX__1 1
#define oland__GPU__TC__TCC_PRESENT 1
#define oland__GPU__TC__TCC_PRESENT__1 1
#define oland__GPU__TC__TCR_TCA_REQ_CREDITS 32
#define oland__GPU__TC__TCR_TCA_REQ_CREDITS__32 1
#define oland__GPU__TC__TA_HANDLE_BASEADDR 1
#define oland__GPU__TC__TA_HANDLE_BASEADDR__1 1
#define oland__GPU__TC__TCP_L1_SIZE 16
#define oland__GPU__TC__TCP_L1_SIZE__16 1
#define oland__GPU__TC__NUM_TCPS 6
#define oland__GPU__TC__NUM_TCPS__6 1
#define oland__GPU__TC__NUM_TCPS__0_PRESENT 1
#define oland__GPU__TC__NUM_TCPS__1_PRESENT 1
#define oland__GPU__TC__NUM_TCPS__2_PRESENT 1
#define oland__GPU__TC__NUM_TCPS__3_PRESENT 1
#define oland__GPU__TC__NUM_TCPS__4_PRESENT 1
#define oland__GPU__TC__NUM_TCPS__5_PRESENT 1
#define oland__GPU__TC__NUM_TCCS 4
#define oland__GPU__TC__NUM_TCCS__4 1
#define oland__GPU__TC__NUM_TCCS__0_PRESENT 1
#define oland__GPU__TC__NUM_TCCS__1_PRESENT 1
#define oland__GPU__TC__NUM_TCCS__2_PRESENT 1
#define oland__GPU__TC__NUM_TCCS__3_PRESENT 1
#define oland__GPU__TC__NUM_TCAS 2
#define oland__GPU__TC__NUM_TCAS__2 1
#define oland__GPU__TC__NUM_TCAS__0_PRESENT 1
#define oland__GPU__TC__NUM_TCAS__1_PRESENT 1
#define oland__GPU__TC__NUM_TCIRS 3
#define oland__GPU__TC__NUM_TCIRS__3 1
#define oland__GPU__TC__NUM_TCIRS__0_PRESENT 1
#define oland__GPU__TC__NUM_TCIRS__1_PRESENT 1
#define oland__GPU__TC__NUM_TCIRS__2_PRESENT 1
#define oland__GPU__TC__NUM_TCIWS 1
#define oland__GPU__TC__NUM_TCIWS__1 1
#define oland__GPU__TC__NUM_TCIWS__0_PRESENT 1
#define oland__GPU__TC__CLIENT_TCI_REQ_CREDITS 8
#define oland__GPU__TC__CLIENT_TCI_REQ_CREDITS__8 1
#define oland__GPU__TC__VGT_TCI_REQ_CREDITS 8
#define oland__GPU__TC__VGT_TCI_REQ_CREDITS__8 1
#define oland__GPU__TC__SQC_TCI_REQ_CREDITS 8
#define oland__GPU__TC__SQC_TCI_REQ_CREDITS__8 1
#define oland__GPU__TC__CP_TCI_REQ_CREDITS 8
#define oland__GPU__TC__CP_TCI_REQ_CREDITS__8 1
#define oland__GPU__TC__NUM_TCIS 4
#define oland__GPU__TC__NUM_TCIS__4 1
#define oland__GPU__TC__NUM_TCIS__0_PRESENT 1
#define oland__GPU__TC__NUM_TCIS__1_PRESENT 1
#define oland__GPU__TC__NUM_TCIS__2_PRESENT 1
#define oland__GPU__TC__NUM_TCIS__3_PRESENT 1
#define oland__GPU__TC__TCC_NUM_LINES 1024
#define oland__GPU__TC__TCC_NUM_LINES__1024 1
#define oland__GPU__TC__TCA_PHASE 0
#define oland__GPU__TC__TCA_PHASE__0 1
#define oland__GPU__TC__TCA_RTN_ARB_IO_PIPELINING 0
#define oland__GPU__TC__TCA_RTN_ARB_IO_PIPELINING__0 1
#define oland__GPU__TC__CP_VGT_TCI_ABOVE_SH0 0
#define oland__GPU__TC__CP_VGT_TCI_ABOVE_SH0__0 1
#define oland__GPU__DB__TB_USES_EMULATOR_MODE 0
#define oland__GPU__DB__TB_USES_EMULATOR_MODE__0 1
#define oland__GPU__DB__USE_ADDRRAXX_LIB 1
#define oland__GPU__DB__USE_ADDRRAXX_LIB__1 1
#define oland__GPU__DB__LEGACY_TILE_MODE_ASSERTS 1
#define oland__GPU__DB__LEGACY_TILE_MODE_ASSERTS__1 1
#define oland__GPU__DB__SUBBLOCK_GATES_PRESENT 0
#define oland__GPU__DB__SUBBLOCK_GATES_PRESENT__0 1
#define oland__GPU__CB__BLENDER_NUM_PIXELS 4
#define oland__GPU__CB__BLENDER_NUM_PIXELS__4 1
#define oland__GPU__CB__BLENDER_NUM_FP32_COMPS 4
#define oland__GPU__CB__BLENDER_NUM_FP32_COMPS__4 1
#define oland__GPU__CB__COMPRESSION 1
#define oland__GPU__CB__COMPRESSION__1 1
#define oland__GPU__LDS__SIZE 64
#define oland__GPU__LDS__SIZE__64 1
#define oland__GPU__LDS__NUM_PIXELS 32
#define oland__GPU__LDS__NUM_PIXELS__32 1
#define oland__GPU__LDS__NUM_BANKS 32
#define oland__GPU__LDS__NUM_BANKS__32 1
#define oland__GPU__GDS__SIZE 64
#define oland__GPU__GDS__SIZE__64 1
#define oland__GPU__GDS__NUM_PIXELS 16
#define oland__GPU__GDS__NUM_PIXELS__16 1
#define oland__GPU__GDS__NUM_PIXELS__0_PRESENT 1
#define oland__GPU__GDS__NUM_PIXELS__1_PRESENT 1
#define oland__GPU__GDS__NUM_PIXELS__2_PRESENT 1
#define oland__GPU__GDS__NUM_PIXELS__3_PRESENT 1
#define oland__GPU__GDS__NUM_PIXELS__4_PRESENT 1
#define oland__GPU__GDS__NUM_PIXELS__5_PRESENT 1
#define oland__GPU__GDS__NUM_PIXELS__6_PRESENT 1
#define oland__GPU__GDS__NUM_PIXELS__7_PRESENT 1
#define oland__GPU__GDS__NUM_PIXELS__8_PRESENT 1
#define oland__GPU__GDS__NUM_PIXELS__9_PRESENT 1
#define oland__GPU__GDS__NUM_PIXELS__10_PRESENT 1
#define oland__GPU__GDS__NUM_PIXELS__11_PRESENT 1
#define oland__GPU__GDS__NUM_PIXELS__12_PRESENT 1
#define oland__GPU__GDS__NUM_PIXELS__13_PRESENT 1
#define oland__GPU__GDS__NUM_PIXELS__14_PRESENT 1
#define oland__GPU__GDS__NUM_PIXELS__15_PRESENT 1
#define oland__GPU__GDS__NUM_BANKS 16
#define oland__GPU__GDS__NUM_BANKS__16 1
#define oland__GPU__GDS__NUM_BANKS__0_PRESENT 1
#define oland__GPU__GDS__NUM_BANKS__1_PRESENT 1
#define oland__GPU__GDS__NUM_BANKS__2_PRESENT 1
#define oland__GPU__GDS__NUM_BANKS__3_PRESENT 1
#define oland__GPU__GDS__NUM_BANKS__4_PRESENT 1
#define oland__GPU__GDS__NUM_BANKS__5_PRESENT 1
#define oland__GPU__GDS__NUM_BANKS__6_PRESENT 1
#define oland__GPU__GDS__NUM_BANKS__7_PRESENT 1
#define oland__GPU__GDS__NUM_BANKS__8_PRESENT 1
#define oland__GPU__GDS__NUM_BANKS__9_PRESENT 1
#define oland__GPU__GDS__NUM_BANKS__10_PRESENT 1
#define oland__GPU__GDS__NUM_BANKS__11_PRESENT 1
#define oland__GPU__GDS__NUM_BANKS__12_PRESENT 1
#define oland__GPU__GDS__NUM_BANKS__13_PRESENT 1
#define oland__GPU__GDS__NUM_BANKS__14_PRESENT 1
#define oland__GPU__GDS__NUM_BANKS__15_PRESENT 1
#define oland__GPU__GDS__NUM_OA_COUNTERS 4
#define oland__GPU__GDS__NUM_OA_COUNTERS__4 1
#define oland__GPU__RLC__LARGE_UCODE_RAM 1
#define oland__GPU__RLC__LARGE_UCODE_RAM__1 1
#define oland__GPU__RLC__LARGE_SCRATCH_RAM 1
#define oland__GPU__RLC__LARGE_SCRATCH_RAM__1 1
#define oland__GPU__RLC__GFX_POWER_GATING 0
#define oland__GPU__RLC__GFX_POWER_GATING__0 1
#define oland__GPU__GC__SC_BCI_16_SAMPLE_PER_PIXEL 1
#define oland__GPU__GC__SC_BCI_16_SAMPLE_PER_PIXEL__1 1
#define oland__GPU__GC__TMP_USE_RASTER_CONFIG 1
#define oland__GPU__GC__TMP_USE_RASTER_CONFIG__1 1
#define oland__GPU__GC__FLT_NORM_0_6 0
#define oland__GPU__GC__FLT_NORM_0_6__0 1
#define oland__GPU__IO__PCIE_PHY falcon65g16x
#define oland__GPU__IO__PCIE_PHY__FALCON65G16X 1
#define oland__GPU__IO__DVP_SUBMOD io_r
#define oland__GPU__IO__DVP_SUBMOD__IO_R 1
#define oland__GPU__IO__SYNC_SUBMOD io_b
#define oland__GPU__IO__SYNC_SUBMOD__IO_B 1
#define oland__GPU__IO__GENERICA_SUBMOD io_b
#define oland__GPU__IO__GENERICA_SUBMOD__IO_B 1
#define oland__GPU__IO__GENERICB_SUBMOD io_b
#define oland__GPU__IO__GENERICB_SUBMOD__IO_B 1
#define oland__GPU__IO__GENERICC_SUBMOD io_b
#define oland__GPU__IO__GENERICC_SUBMOD__IO_B 1
#define oland__GPU__IO__GENERICD_SUBMOD io_b
#define oland__GPU__IO__GENERICD_SUBMOD__IO_B 1
#define oland__GPU__IO__GENERICE_SUBMOD io_b
#define oland__GPU__IO__GENERICE_SUBMOD__IO_B 1
#define oland__GPU__IO__GENERICF_SUBMOD io_b
#define oland__GPU__IO__GENERICF_SUBMOD__IO_B 1
#define oland__GPU__IO__GENERICG_SUBMOD io_b
#define oland__GPU__IO__GENERICG_SUBMOD__IO_B 1
#define oland__GPU__IO__VID_SUBMOD io_r
#define oland__GPU__IO__VID_SUBMOD__IO_R 1
#define oland__GPU__IO__GPIO_SUBMOD io_b
#define oland__GPU__IO__GPIO_SUBMOD__IO_B 1
#define oland__GPU__IO__PLL_SUBMOD io_b
#define oland__GPU__IO__PLL_SUBMOD__IO_B 1
#define oland__GPU__IO__SPLL_SUBMOD io_b
#define oland__GPU__IO__SPLL_SUBMOD__IO_B 1
#define oland__GPU__IO__UPLL_SUBMOD io_b
#define oland__GPU__IO__UPLL_SUBMOD__IO_B 1
#define oland__GPU__IO__HPD_SUBMOD io_b
#define oland__GPU__IO__HPD_SUBMOD__IO_B 1
#define oland__GPU__IO__I2C_SUBMOD io_b
#define oland__GPU__IO__I2C_SUBMOD__IO_B 1
#define oland__GPU__IO__ASAT_45_PLL 1
#define oland__GPU__IO__ASAT_45_PLL__1 1
#define oland__GPU__IO__PWRGOOD 1
#define oland__GPU__IO__PWRGOOD__1 1
#define oland__GPU__IO__NUM_MPLL 2
#define oland__GPU__IO__NUM_MPLL__2 1
#define oland__GPU__IO__READY 1
#define oland__GPU__IO__READY__1 1
#define oland__GPU__MC__NUM_MCB_BLOCKS 1
#define oland__GPU__MC__NUM_MCB_BLOCKS__1 1
#define oland__GPU__MC__NUM_MCB_BLOCKS__0_PRESENT 1
#define oland__GPU__MC__NUM_MCB_TILES 1
#define oland__GPU__MC__NUM_MCB_TILES__1 1
#define oland__GPU__MC__NUM_MCB_TILES__0_PRESENT 1
#define oland__GPU__MC__NUM_MCD_BLOCKS 2
#define oland__GPU__MC__NUM_MCD_BLOCKS__2 1
#define oland__GPU__MC__NUM_MCD_BLOCKS__0_PRESENT 1
#define oland__GPU__MC__NUM_MCD_BLOCKS__1_PRESENT 1
#define oland__GPU__MC__NUM_MCC_BLOCKS 2
#define oland__GPU__MC__NUM_MCC_BLOCKS__2 1
#define oland__GPU__MC__NUM_MCC_BLOCKS__0_PRESENT 1
#define oland__GPU__MC__NUM_MCC_BLOCKS__1_PRESENT 1
#define oland__GPU__MC__NUM_MCT_TILES 2
#define oland__GPU__MC__NUM_MCT_TILES__2 1
#define oland__GPU__MC__NUM_IO_CHNLS 4
#define oland__GPU__MC__NUM_IO_CHNLS__4 1
#define oland__GPU__MC__NUM_IO_CHNLS__0_PRESENT 1
#define oland__GPU__MC__NUM_IO_CHNLS__1_PRESENT 1
#define oland__GPU__MC__NUM_IO_CHNLS__2_PRESENT 1
#define oland__GPU__MC__NUM_IO_CHNLS__3_PRESENT 1
#define oland__GPU__MC__CDRRDBK 6
#define oland__GPU__MC__CDRRDBK__6 1
#define oland__GPU__MC__NUM_RPB_EFF_QUEUES 2
#define oland__GPU__MC__NUM_RPB_EFF_QUEUES__2 1
#define oland__GPU__MC__MCD0_BLOCK 1
#define oland__GPU__MC__MCD0_BLOCK__1 1
#define oland__GPU__MC__MCD1_BLOCK 1
#define oland__GPU__MC__MCD1_BLOCK__1 1
#define oland__GPU__MC__MCC0_BLOCK 1
#define oland__GPU__MC__MCC0_BLOCK__1 1
#define oland__GPU__MC__MCC1_BLOCK 1
#define oland__GPU__MC__MCC1_BLOCK__1 1
#define oland__GPU__MC__MCB_BLOCK 1
#define oland__GPU__MC__MCB_BLOCK__1 1
#define oland__GPU__MC__ALLOW_LARRAY 0
#define oland__GPU__MC__ALLOW_LARRAY__0 1
#define oland__GPU__MC__MCD_SRBM_PRESENT 1
#define oland__GPU__MC__MCD_SRBM_PRESENT__1 1
#define oland__GPU__MC__HDP_RD_ON_GBL1 1
#define oland__GPU__MC__HDP_RD_ON_GBL1__1 1
#define oland__GPU__MC__TWO_GBL0_RDRET 1
#define oland__GPU__MC__TWO_GBL0_RDRET__1 1
#define oland__GPU__MC__NUM_OF_RB_PER_MCD 1
#define oland__GPU__MC__NUM_OF_RB_PER_MCD__1 1
#define oland__GPU__MC__NUM_TC_PER_MCD 2
#define oland__GPU__MC__NUM_TC_PER_MCD__2 1
#define oland__GPU__MC__NUM_TCCS 4
#define oland__GPU__MC__NUM_TCCS__4 1
#define oland__GPU__MC__NUM_MCD_POW2 1
#define oland__GPU__MC__NUM_MCD_POW2__1 1
#define oland__GPU__MC__MCD0_IO0_REP 6
#define oland__GPU__MC__MCD0_IO0_REP__6 1
#define oland__GPU__MC__MCD0_IO1_REP 3
#define oland__GPU__MC__MCD0_IO1_REP__3 1
#define oland__GPU__MC__MCD1_IO0_REP 5
#define oland__GPU__MC__MCD1_IO0_REP__5 1
#define oland__GPU__MC__MCD1_IO1_REP 3
#define oland__GPU__MC__MCD1_IO1_REP__3 1
#define oland__GPU__MC__SIMPLIFIED_BLACKOUT 1
#define oland__GPU__MC__SIMPLIFIED_BLACKOUT__1 1
#define oland__GPU__MC__DDR5_MCLK_DEFAULT 5
#define oland__GPU__MC__DDR5_MCLK_DEFAULT__5 1
#define oland__GPU__MC__XBAR_REMAP 0
#define oland__GPU__MC__XBAR_REMAP__0 1
#define oland__GPU__MC__GPU_VIRTUAL_ADDRESS_WIDTH 40
#define oland__GPU__MC__GPU_VIRTUAL_ADDRESS_WIDTH__40 1
#define oland__GPU__MC__GPU_PHYSICAL_ADDRESS_WIDTH 40
#define oland__GPU__MC__GPU_PHYSICAL_ADDRESS_WIDTH__40 1
#define oland__GPU__MC__PCIE_VIRTUAL_ADDRESS_WIDTH 48
#define oland__GPU__MC__PCIE_VIRTUAL_ADDRESS_WIDTH__48 1
#define oland__GPU__MC__PCIE_PHYSICAL_ADDRESS_WIDTH 48
#define oland__GPU__MC__PCIE_PHYSICAL_ADDRESS_WIDTH__48 1
#define oland__GPU__MC__SPLIT_TILES 1
#define oland__GPU__MC__SPLIT_TILES__1 1
#define oland__GPU__MC__PAB_EXISTS 0
#define oland__GPU__MC__PAB_EXISTS__0 1
#define oland__GPU__MC__FUSION_FEATURE_ONLY 0
#define oland__GPU__MC__FUSION_FEATURE_ONLY__0 1
#define oland__GPU__MC__POWER_GATING 1
#define oland__GPU__MC__POWER_GATING__1 1
#define oland__GPU__MC__NUM_PGFSM_BLOCKS 3
#define oland__GPU__MC__NUM_PGFSM_BLOCKS__3 1
#define oland__GPU__MC__PHY_POWER_GATING 1
#define oland__GPU__MC__PHY_POWER_GATING__1 1
#define oland__GPU__MC__LOWSPEED_MEMPHY 1
#define oland__GPU__MC__LOWSPEED_MEMPHY__1 1
#define oland__GPU__VID__PRESENT 0
#define oland__GPU__VID__PRESENT__0 1
#define oland__GPU__DC__PRESENT 0
#define oland__GPU__DC__PRESENT__0 1
#define oland__GPU__AVP__PRESENT 0
#define oland__GPU__AVP__PRESENT__0 1
#define oland__GPU__UVD__PRESENT 0
#define oland__GPU__UVD__PRESENT__0 1
#define oland__ENV__GPU__UVD__HAVE_RTL 0
#define oland__ENV__GPU__UVD__HAVE_RTL__0 1
#define oland__ENV__GPU__MC__HAVE_BFM 1
#define oland__ENV__GPU__MC__HAVE_BFM__1 1
#define oland__ENV__GPU__MC__HAVE_RTL 0
#define oland__ENV__GPU__MC__HAVE_RTL__0 1
#define oland__GPU__UVD__PROJ_LARK 1
#define oland__GPU__UVD__PROJ_LARK__1 1
#define oland__GPU__UVD__CTX_ENABLE 1
#define oland__GPU__UVD__CTX_ENABLE__1 1
#define oland__GPU__UVD__MC_7XX 1
#define oland__GPU__UVD__MC_7XX__1 1
#define oland__GPU__UVD__CGC_CGTT_LOCAL_CLOCK_GATER 1
#define oland__GPU__UVD__CGC_CGTT_LOCAL_CLOCK_GATER__1 1
#define oland__GPU__MC__ARB_VM_CREDITS 32
#define oland__GPU__MC__ARB_VM_CREDITS__32 1
#define oland__GPU__MC__MCD_TLBS 4
#define oland__GPU__MC__MCD_TLBS__4 1
#define oland__GPU__MC__MCB_TLBS 3
#define oland__GPU__MC__MCB_TLBS__3 1
#define oland__GPU__MC__NO_STALL_ON_FAULT 1
#define oland__GPU__MC__NO_STALL_ON_FAULT__1 1
#define oland__GPU__MC__VMC_CACHES 2
#define oland__GPU__MC__VMC_CACHES__2 1
#define oland__GPU__MC__BIGK_CACHE_SIZE 4
#define oland__GPU__MC__BIGK_CACHE_SIZE__4 1
#define oland__GPU__MC__MCB_TLB0_CAM 5
#define oland__GPU__MC__MCB_TLB0_CAM__5 1
#define oland__GPU__MC__MCB_TLB1_CAM 4
#define oland__GPU__MC__MCB_TLB1_CAM__4 1
#define oland__GPU__MC__MCB_TLB2_CAM 4
#define oland__GPU__MC__MCB_TLB2_CAM__4 1
#define oland__GPU__MC__MCD_TLB0_CAM 4
#define oland__GPU__MC__MCD_TLB0_CAM__4 1
#define oland__GPU__MC__MCD_TLB1_CAM 4
#define oland__GPU__MC__MCD_TLB1_CAM__4 1
#define oland__GPU__MC__MCD_TLB2_CAM 4
#define oland__GPU__MC__MCD_TLB2_CAM__4 1
#define oland__GPU__MC__MCD_TLB3_CAM 4
#define oland__GPU__MC__MCD_TLB3_CAM__4 1
#define oland__GPU__MC__SEND_FREE_AT_RTN 1
#define oland__GPU__MC__SEND_FREE_AT_RTN__1 1
#define oland__GPU__MC__CONTEXT_WIDTH 3
#define oland__GPU__MC__CONTEXT_WIDTH__3 1
#define oland__GPU__MC__BUG_159204_EXISTS 1
#define oland__GPU__MC__BUG_159204_EXISTS__1 1
#endif
projects/rocr-runtime/runtime/hsa-ext-aql-profile/gfxip/gfx8/features_pitcairn.h
+1359
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projects/rocr-runtime/runtime/hsa-ext-aql-profile/gfxip/gfx8/features_tahiti.h
+1261
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projects/rocr-runtime/runtime/hsa-ext-aql-profile/gfxip/gfx8/features_tiran.h
+1640
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projects/rocr-runtime/runtime/hsa-ext-aql-profile/gfxip/gfx8/features_verde.h
+962
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@@ -0,0 +1,962 @@
#ifndef verde____GPU_FEATURES_H__
#define verde____GPU_FEATURES_H__
#define verde__GPU__BIF__VC_PRESENT 0
#define verde__GPU__BIF__VC_PRESENT__0 1
#define verde__GPU__BIF__PCIEGEN2_MCB_DEPTH 96
#define verde__GPU__BIF__PCIEGEN2_MCB_DEPTH__96 1
#define verde__GPU__BIF__CLKBUF_PRESENT 1
#define verde__GPU__BIF__CLKBUF_PRESENT__1 1
#define verde__GPU__XSP__PRESENT 0
#define verde__GPU__XSP__PRESENT__0 1
#define verde__GPU__CHIP__DFS 1
#define verde__GPU__CHIP__DFS__1 1
#define verde__GPU__CHIP__TECH tsmc28hp
#define verde__GPU__CHIP__TECH__TSMC28HP 1
#define verde__GPU__CHIP__TECHVER 0.0.1e
#define verde__GPU__CHIP__TECHVER__0_0_1E 1
#define verde__TOOLS__GUTS__TECHNM tsmc28hp
#define verde__TOOLS__GUTS__TECHNM__TSMC28HP 1
#define verde__TOOLS__GUTS__MEMVENDOR Virage
#define verde__TOOLS__GUTS__MEMVENDOR__VIRAGE 1
#define verde__TOOLS__GUTS__MEMTECH 28nm
#define verde__TOOLS__GUTS__MEMTECH__28NM 1
#define verde__TOOLS__GUTS__LARRVENDOR AMD
#define verde__TOOLS__GUTS__LARRVENDOR__AMD 1
#define verde__TOOLS__GUTS__LARRTYPE default
#define verde__TOOLS__GUTS__LARRTYPE__DEFAULT 1
#define verde__TOOLS__GUTS__LARRVER 0_1
#define verde__TOOLS__GUTS__LARRVER__0_1 1
#define verde__TOOLS__GUTS__MEMFABTECH TSMC28
#define verde__TOOLS__GUTS__MEMFABTECH__TSMC28 1
#define verde__TOOLS__GUTS__MEMVER 0_1
#define verde__TOOLS__GUTS__MEMVER__0_1 1
#define verde__TOOLS__GUTS__MEMTYPE slow
#define verde__TOOLS__GUTS__MEMTYPE__SLOW 1
#define verde__GPU__CHIP__MEMTECH 28nm
#define verde__GPU__CHIP__MEMTECH__28NM 1
#define verde__GPU__CHIP__MEMVIEWVER 0_5
#define verde__GPU__CHIP__MEMVIEWVER__0_5 1
#define verde__GPU__CHIP__MEM virage
#define verde__GPU__CHIP__MEM__VIRAGE 1
#define verde__GPU__CHIP__MEMVENDOR Virage
#define verde__GPU__CHIP__MEMVENDOR__VIRAGE 1
#define verde__GPU__CHIP__SRAM_MEMFABTECH TSMC28
#define verde__GPU__CHIP__SRAM_MEMFABTECH__TSMC28 1
#define verde__GPU__CHIP__SRAM_TIMING slow
#define verde__GPU__CHIP__SRAM_TIMING__SLOW 1
#define verde__GPU__CHIP__SRAM_MEMVER 0_5_1
#define verde__GPU__CHIP__SRAM_MEMVER__0_5_1 1
#define verde__GPU__CHIP__LARRVENDOR AMD
#define verde__GPU__CHIP__LARRVENDOR__AMD 1
#define verde__GPU__CHIP__LARR_MEMFABTECH TSMC28
#define verde__GPU__CHIP__LARR_MEMFABTECH__TSMC28 1
#define verde__GPU__CHIP__LARR_TIMING default
#define verde__GPU__CHIP__LARR_TIMING__DEFAULT 1
#define verde__GPU__CHIP__LARR_MEMVER 0_3
#define verde__GPU__CHIP__LARR_MEMVER__0_3 1
#define verde__GPU__CHIP__TILES_PRESENT 0
#define verde__GPU__CHIP__TILES_PRESENT__0 1
#define verde__GPU__CHIP__SMSGCOUNT 4
#define verde__GPU__CHIP__SMSGCOUNT__4 1
#define verde__GPU__CHIP__SMSG_0_PRESENT 1
#define verde__GPU__CHIP__SMSG_0_PRESENT__1 1
#define verde__GPU__CHIP__SMSG_1_PRESENT 1
#define verde__GPU__CHIP__SMSG_1_PRESENT__1 1
#define verde__GPU__CHIP__SMSG_2_PRESENT 1
#define verde__GPU__CHIP__SMSG_2_PRESENT__1 1
#define verde__GPU__CHIP__SMSG_3_PRESENT 1
#define verde__GPU__CHIP__SMSG_3_PRESENT__1 1
#define verde__GPU__CHIP__XCLK_MHZ 25
#define verde__GPU__CHIP__XCLK_MHZ__25 1
#define verde__GPU__CHIP__POWERGATE 0
#define verde__GPU__CHIP__POWERGATE__0 1
#define verde__GPU__LBIST__PRESENT 0
#define verde__GPU__LBIST__PRESENT__0 1
#define verde__GPU__THM__TMON1_PRESENT 1
#define verde__GPU__THM__TMON1_PRESENT__1 1
#define verde__GPU__THM__TMON2_PRESENT 1
#define verde__GPU__THM__TMON2_PRESENT__1 1
#define verde__GPU__THM__TMON3_PRESENT 1
#define verde__GPU__THM__TMON3_PRESENT__1 1
#define verde__GPU__TMON0__LEFT_NUM_RDI 4
#define verde__GPU__TMON0__LEFT_NUM_RDI__4 1
#define verde__GPU__TMON0__RIGHT_NUM_RDI 4
#define verde__GPU__TMON0__RIGHT_NUM_RDI__4 1
#define verde__GPU__TMON1__LEFT_NUM_RDI 4
#define verde__GPU__TMON1__LEFT_NUM_RDI__4 1
#define verde__GPU__TMON1__RIGHT_NUM_RDI 4
#define verde__GPU__TMON1__RIGHT_NUM_RDI__4 1
#define verde__GPU__TMON2__LEFT_NUM_RDI 4
#define verde__GPU__TMON2__LEFT_NUM_RDI__4 1
#define verde__GPU__TMON2__RIGHT_NUM_RDI 4
#define verde__GPU__TMON2__RIGHT_NUM_RDI__4 1
#define verde__GPU__TMON3__LEFT_NUM_RDI 4
#define verde__GPU__TMON3__LEFT_NUM_RDI__4 1
#define verde__GPU__TMON3__RIGHT_NUM_RDI 4
#define verde__GPU__TMON3__RIGHT_NUM_RDI__4 1
#define verde__GPU__CHIP__MEM_POWER_CTRL 17
#define verde__GPU__CHIP__MEM_POWER_CTRL__17 1
#define verde__GPU__CHIP__MEM_POWER_CTRL_LS 0
#define verde__GPU__CHIP__MEM_POWER_CTRL_LS__0 1
#define verde__GPU__CHIP__MEM_POWER_CTRL_DS_D 1
#define verde__GPU__CHIP__MEM_POWER_CTRL_DS_D__1 1
#define verde__GPU__CHIP__MEM_POWER_CTRL_DS_M 2
#define verde__GPU__CHIP__MEM_POWER_CTRL_DS_M__2 1
#define verde__GPU__CHIP__MEM_POWER_CTRL_SD_D 3
#define verde__GPU__CHIP__MEM_POWER_CTRL_SD_D__3 1
#define verde__GPU__CHIP__MEM_POWER_CTRL_SD_M 4
#define verde__GPU__CHIP__MEM_POWER_CTRL_SD_M__4 1
#define verde__GPU__CHIP__MEM_POWER_CTRL_DS 5
#define verde__GPU__CHIP__MEM_POWER_CTRL_DS__5 1
#define verde__GPU__CHIP__MEM_POWER_CTRL_SD 6
#define verde__GPU__CHIP__MEM_POWER_CTRL_SD__6 1
#define verde__GPU__CHIP__MEM_POWER_CTRL_FISO 7
#define verde__GPU__CHIP__MEM_POWER_CTRL_FISO__7 1
#define verde__GPU__CHIP__MEM_POWER_CTRL_V_RM_START 8
#define verde__GPU__CHIP__MEM_POWER_CTRL_V_RM_START__8 1
#define verde__GPU__CHIP__MEM_POWER_CTRL_V_RM_END 16
#define verde__GPU__CHIP__MEM_POWER_CTRL_V_RM_END__16 1
#define verde__GPU__CHIP__MEM_POWER_CTRL_A_RM_START 8
#define verde__GPU__CHIP__MEM_POWER_CTRL_A_RM_START__8 1
#define verde__GPU__CHIP__MEM_POWER_CTRL_A_RM_END 30
#define verde__GPU__CHIP__MEM_POWER_CTRL_A_RM_END__30 1
#define verde__GPU__CHIP__MEM_POWER_CTRL_V_RM_RF_RME 8
#define verde__GPU__CHIP__MEM_POWER_CTRL_V_RM_RF_RME__8 1
#define verde__GPU__CHIP__MEM_POWER_CTRL_V_RM_RF_RM_START 9
#define verde__GPU__CHIP__MEM_POWER_CTRL_V_RM_RF_RM_START__9 1
#define verde__GPU__CHIP__MEM_POWER_CTRL_V_RM_RF_RM_END 10
#define verde__GPU__CHIP__MEM_POWER_CTRL_V_RM_RF_RM_END__10 1
#define verde__GPU__CHIP__MEM_POWER_CTRL_V_RM_PDP_RME 11
#define verde__GPU__CHIP__MEM_POWER_CTRL_V_RM_PDP_RME__11 1
#define verde__GPU__CHIP__MEM_POWER_CTRL_V_RM_PDP_RM_START 12
#define verde__GPU__CHIP__MEM_POWER_CTRL_V_RM_PDP_RM_START__12 1
#define verde__GPU__CHIP__MEM_POWER_CTRL_V_RM_PDP_RM_END 13
#define verde__GPU__CHIP__MEM_POWER_CTRL_V_RM_PDP_RM_END__13 1
#define verde__GPU__CHIP__MEM_POWER_CTRL_V_RM_HD_RME 14
#define verde__GPU__CHIP__MEM_POWER_CTRL_V_RM_HD_RME__14 1
#define verde__GPU__CHIP__MEM_POWER_CTRL_V_RM_HD_RM_START 15
#define verde__GPU__CHIP__MEM_POWER_CTRL_V_RM_HD_RM_START__15 1
#define verde__GPU__CHIP__MEM_POWER_CTRL_V_RM_HD_RM_END 16
#define verde__GPU__CHIP__MEM_POWER_CTRL_V_RM_HD_RM_END__16 1
#define verde__GPU__CHIP__MEM_POWER_CTRL_A_RM_RF_RME 8
#define verde__GPU__CHIP__MEM_POWER_CTRL_A_RM_RF_RME__8 1
#define verde__GPU__CHIP__MEM_POWER_CTRL_A_RM_RF_RM_START 9
#define verde__GPU__CHIP__MEM_POWER_CTRL_A_RM_RF_RM_START__9 1
#define verde__GPU__CHIP__MEM_POWER_CTRL_A_RM_RF_RM_END 17
#define verde__GPU__CHIP__MEM_POWER_CTRL_A_RM_RF_RM_END__17 1
#define verde__GPU__CHIP__MEM_POWER_CTRL_A_RM_PDP_RME 18
#define verde__GPU__CHIP__MEM_POWER_CTRL_A_RM_PDP_RME__18 1
#define verde__GPU__CHIP__MEM_POWER_CTRL_A_RM_PDP_RM_START 19
#define verde__GPU__CHIP__MEM_POWER_CTRL_A_RM_PDP_RM_START__19 1
#define verde__GPU__CHIP__MEM_POWER_CTRL_A_RM_PDP_RM_END 30
#define verde__GPU__CHIP__MEM_POWER_CTRL_A_RM_PDP_RM_END__30 1
#define verde__GPU__TSS__NUM_TILES 5
#define verde__GPU__TSS__NUM_TILES__5 1
#define verde__GPU__TSS__TSS0_TILE 1
#define verde__GPU__TSS__TSS0_TILE__1 1
#define verde__GPU__TSS__TSS1_TILE 1
#define verde__GPU__TSS__TSS1_TILE__1 1
#define verde__GPU__TSS__TSS2_TILE 1
#define verde__GPU__TSS__TSS2_TILE__1 1
#define verde__GPU__TSS__TSS3_TILE 1
#define verde__GPU__TSS__TSS3_TILE__1 1
#define verde__GPU__TSS__TSS4_TILE 1
#define verde__GPU__TSS__TSS4_TILE__1 1
#define verde__GPU__TSS__TSS4_AS_ADC 1
#define verde__GPU__TSS__TSS4_AS_ADC__1 1
#define verde__GPU__RCU__PROGRAMMABLE_RMBITS 1
#define verde__GPU__RCU__PROGRAMMABLE_RMBITS__1 1
#define verde__GPU__CGTT_TILE__PDLY 1
#define verde__GPU__CGTT_TILE__PDLY__1 1
#define verde__GPU__PDLY_TILE__PDLY 1
#define verde__GPU__PDLY_TILE__PDLY__1 1
#define verde__GPU__PDLY_TILE__CLKGATE 0
#define verde__GPU__PDLY_TILE__CLKGATE__0 1
#define verde__GPU__CG__SMC_SCRATCH_REGS 1
#define verde__GPU__CG__SMC_SCRATCH_REGS__1 1
#define verde__GPU__CG__CG_DLL_PDNB 1
#define verde__GPU__CG__CG_DLL_PDNB__1 1
#define verde__GPU__SMU__USE_HW_VBI 1
#define verde__GPU__SMU__USE_HW_VBI__1 1
#define verde__GPU__SMU__NUM_CAC_MGR_4 1
#define verde__GPU__SMU__NUM_CAC_MGR_4__1 1
#define verde__GPU__PDMA__PRESENT 0
#define verde__GPU__PDMA__PRESENT__0 1
#define verde__GPU__DRMDMA__DUAL_DRMDMA_PRESENT 1
#define verde__GPU__DRMDMA__DUAL_DRMDMA_PRESENT__1 1
#define verde__GPU__DRM__BGAES_OFF 1
#define verde__GPU__DRM__BGAES_OFF__1 1
#define verde__GPU__DLB__SLEW 1
#define verde__GPU__DLB__SLEW__1 1
#define verde__GPU__ROM__EXT_CS_EN 1
#define verde__GPU__ROM__EXT_CS_EN__1 1
#define verde__GPU__CPL__GPIO_23_PRESENT 0
#define verde__GPU__CPL__GPIO_23_PRESENT__0 1
#define verde__GPU__CPL__GPIO_24_PRESENT 0
#define verde__GPU__CPL__GPIO_24_PRESENT__0 1
#define verde__GPU__CPL__GPIO_25_PRESENT 0
#define verde__GPU__CPL__GPIO_25_PRESENT__0 1
#define verde__GPU__CPL__GPIO_26_PRESENT 0
#define verde__GPU__CPL__GPIO_26_PRESENT__0 1
#define verde__GPU__CPL__GPIO_27_PRESENT 0
#define verde__GPU__CPL__GPIO_27_PRESENT__0 1
#define verde__GPU__CPL__MLPS_0_PRESENT 1
#define verde__GPU__CPL__MLPS_0_PRESENT__1 1
#define verde__GPU__CPL__MLPS_1_PRESENT 1
#define verde__GPU__CPL__MLPS_1_PRESENT__1 1
#define verde__GPU__CPL__MLPS_2_PRESENT 1
#define verde__GPU__CPL__MLPS_2_PRESENT__1 1
#define verde__GPU__CPL__MLPS_3_PRESENT 1
#define verde__GPU__CPL__MLPS_3_PRESENT__1 1
#define verde__GPU__CPL__SX_0_PRESENT 1
#define verde__GPU__CPL__SX_0_PRESENT__1 1
#define verde__GPU__SMC__TAP_FED_PRESENT 1
#define verde__GPU__SMC__TAP_FED_PRESENT__1 1
#define verde__GPU__CPL__PG_CODE_ENABLE 1
#define verde__GPU__CPL__PG_CODE_ENABLE__1 1
#define verde__GPU__CPL__PG_CODE_GPG 1
#define verde__GPU__CPL__PG_CODE_GPG__1 1
#define verde__GPU__AVP__MC_IF 1
#define verde__GPU__AVP__MC_IF__1 1
#define verde__GPU__AVP__UVD_RLC_CMC_IF 1
#define verde__GPU__AVP__UVD_RLC_CMC_IF__1 1
#define verde__GPU__DC__TMDS_LINK tmds_link_dual
#define verde__GPU__DC__TMDS_LINK__TMDS_LINK_DUAL 1
#define verde__GPU__DC__NUM_DDC_PAIRS 6
#define verde__GPU__DC__NUM_DDC_PAIRS__6 1
#define verde__GPU__DC__NUM_DDC_PAIRS__0_PRESENT 1
#define verde__GPU__DC__NUM_DDC_PAIRS__1_PRESENT 1
#define verde__GPU__DC__NUM_DDC_PAIRS__2_PRESENT 1
#define verde__GPU__DC__NUM_DDC_PAIRS__3_PRESENT 1
#define verde__GPU__DC__NUM_DDC_PAIRS__4_PRESENT 1
#define verde__GPU__DC__NUM_DDC_PAIRS__5_PRESENT 1
#define verde__GPU__DC__NUM_HPD 6
#define verde__GPU__DC__NUM_HPD__6 1
#define verde__GPU__DC__NUM_HPD__0_PRESENT 1
#define verde__GPU__DC__NUM_HPD__1_PRESENT 1
#define verde__GPU__DC__NUM_HPD__2_PRESENT 1
#define verde__GPU__DC__NUM_HPD__3_PRESENT 1
#define verde__GPU__DC__NUM_HPD__4_PRESENT 1
#define verde__GPU__DC__NUM_HPD__5_PRESENT 1
#define verde__GPU__DC__NUM_PIPE_PAIRS 3
#define verde__GPU__DC__NUM_PIPE_PAIRS__3 1
#define verde__GPU__DC__NUM_PIPE_PAIRS__0_PRESENT 1
#define verde__GPU__DC__NUM_PIPE_PAIRS__1_PRESENT 1
#define verde__GPU__DC__NUM_PIPE_PAIRS__2_PRESENT 1
#define verde__GPU__DC__NUM_PIPES 6
#define verde__GPU__DC__NUM_PIPES__6 1
#define verde__GPU__DC__NUM_PIPES__0_PRESENT 1
#define verde__GPU__DC__NUM_PIPES__1_PRESENT 1
#define verde__GPU__DC__NUM_PIPES__2_PRESENT 1
#define verde__GPU__DC__NUM_PIPES__3_PRESENT 1
#define verde__GPU__DC__NUM_PIPES__4_PRESENT 1
#define verde__GPU__DC__NUM_PIPES__5_PRESENT 1
#define verde__GPU__DC__NUM_DIG 6
#define verde__GPU__DC__NUM_DIG__6 1
#define verde__GPU__DC__NUM_DIG__0_PRESENT 1
#define verde__GPU__DC__NUM_DIG__1_PRESENT 1
#define verde__GPU__DC__NUM_DIG__2_PRESENT 1
#define verde__GPU__DC__NUM_DIG__3_PRESENT 1
#define verde__GPU__DC__NUM_DIG__4_PRESENT 1
#define verde__GPU__DC__NUM_DIG__5_PRESENT 1
#define verde__GPU__DC__NUM_AUX 6
#define verde__GPU__DC__NUM_AUX__6 1
#define verde__GPU__DC__NUM_AUX__0_PRESENT 1
#define verde__GPU__DC__NUM_AUX__1_PRESENT 1
#define verde__GPU__DC__NUM_AUX__2_PRESENT 1
#define verde__GPU__DC__NUM_AUX__3_PRESENT 1
#define verde__GPU__DC__NUM_AUX__4_PRESENT 1
#define verde__GPU__DC__NUM_AUX__5_PRESENT 1
#define verde__GPU__DISPPLL__MACRO walden
#define verde__GPU__DISPPLL__MACRO__WALDEN 1
#define verde__GPU__TMDPA__MACRO walden
#define verde__GPU__TMDPA__MACRO__WALDEN 1
#define verde__GPU__TMDPB__MACRO walden
#define verde__GPU__TMDPB__MACRO__WALDEN 1
#define verde__GPU__LVTMDP__MACRO walden
#define verde__GPU__LVTMDP__MACRO__WALDEN 1
#define verde__GPU__DACA__MACRO walden
#define verde__GPU__DACA__MACRO__WALDEN 1
#define verde__GPU__DACB__MACRO walden
#define verde__GPU__DACB__MACRO__WALDEN 1
#define verde__GPU__DC__VIP_PRESENT 1
#define verde__GPU__DC__VIP_PRESENT__1 1
#define verde__GPU__DC__ABM_PRESENT 1
#define verde__GPU__DC__ABM_PRESENT__1 1
#define verde__GPU__DC__DMCU_PRESENT 1
#define verde__GPU__DC__DMCU_PRESENT__1 1
#define verde__GPU__DC__DVO_PRESENT 1
#define verde__GPU__DC__DVO_PRESENT__1 1
#define verde__GPU__DC__SDVO_PRESENT 1
#define verde__GPU__DC__SDVO_PRESENT__1 1
#define verde__GPU__DC__LVDS_PRESENT 1
#define verde__GPU__DC__LVDS_PRESENT__1 1
#define verde__GPU__UNIPHYAB__PRESENT 1
#define verde__GPU__UNIPHYAB__PRESENT__1 1
#define verde__GPU__UNIPHYCD__PRESENT 1
#define verde__GPU__UNIPHYCD__PRESENT__1 1
#define verde__GPU__UNIPHYEF__PRESENT 1
#define verde__GPU__UNIPHYEF__PRESENT__1 1
#define verde__GPU__UNIPHYAB__TYPE lvtmdp
#define verde__GPU__UNIPHYAB__TYPE__LVTMDP 1
#define verde__GPU__UNIPHYCD__TYPE tmdpa
#define verde__GPU__UNIPHYCD__TYPE__TMDPA 1
#define verde__GPU__UNIPHYEF__TYPE tmdpb
#define verde__GPU__UNIPHYEF__TYPE__TMDPB 1
#define verde__GPU__UNIPHYAB__LVTMDP 1
#define verde__GPU__UNIPHYAB__LVTMDP__1 1
#define verde__GPU__DC__DACA_PRESENT 1
#define verde__GPU__DC__DACA_PRESENT__1 1
#define verde__GPU__DC__DACB_PRESENT 1
#define verde__GPU__DC__DACB_PRESENT__1 1
#define verde__GPU__DC__TVOUT_PRESENT 1
#define verde__GPU__DC__TVOUT_PRESENT__1 1
#define verde__GPU__DC__MVP_PRESENT 1
#define verde__GPU__DC__MVP_PRESENT__1 1
#define verde__GPU__DC__DENTIST_INTERFACE_PRESENT 0
#define verde__GPU__DC__DENTIST_INTERFACE_PRESENT__0 1
#define verde__GPU__DC__DDC1AUX1 dual_mode
#define verde__GPU__DC__DDC1AUX1__DUAL_MODE 1
#define verde__GPU__DC__DDC2AUX2 dual_mode
#define verde__GPU__DC__DDC2AUX2__DUAL_MODE 1
#define verde__GPU__DC__DDC3AUX3 dual_mode
#define verde__GPU__DC__DDC3AUX3__DUAL_MODE 1
#define verde__GPU__DC__DDC4AUX4 dual_mode
#define verde__GPU__DC__DDC4AUX4__DUAL_MODE 1
#define verde__GPU__DC__DDC5AUX5 dual_mode
#define verde__GPU__DC__DDC5AUX5__DUAL_MODE 1
#define verde__GPU__DC__DDC6AUX6 dual_mode
#define verde__GPU__DC__DDC6AUX6__DUAL_MODE 1
#define verde__GPU__DC__AUX1_PRESENT 1
#define verde__GPU__DC__AUX1_PRESENT__1 1
#define verde__GPU__DC__AUX2_PRESENT 1
#define verde__GPU__DC__AUX2_PRESENT__1 1
#define verde__GPU__DC__AUX3_PRESENT 1
#define verde__GPU__DC__AUX3_PRESENT__1 1
#define verde__GPU__DC__AUX4_PRESENT 1
#define verde__GPU__DC__AUX4_PRESENT__1 1
#define verde__GPU__DC__AUX5_PRESENT 1
#define verde__GPU__DC__AUX5_PRESENT__1 1
#define verde__GPU__DC__AUX6_PRESENT 1
#define verde__GPU__DC__AUX6_PRESENT__1 1
#define verde__GPU__DC__DENTIST_PRESENT 0
#define verde__GPU__DC__DENTIST_PRESENT__0 1
#define verde__GPU__DC__GENERICA_PRESENT 1
#define verde__GPU__DC__GENERICA_PRESENT__1 1
#define verde__GPU__DC__GENERICB_PRESENT 1
#define verde__GPU__DC__GENERICB_PRESENT__1 1
#define verde__GPU__DC__GENERICC_PRESENT 1
#define verde__GPU__DC__GENERICC_PRESENT__1 1
#define verde__GPU__DC__GENERICD_PRESENT 1
#define verde__GPU__DC__GENERICD_PRESENT__1 1
#define verde__GPU__DC__GENERICE_PRESENT 1
#define verde__GPU__DC__GENERICE_PRESENT__1 1
#define verde__GPU__DC__GENERICF_PRESENT 1
#define verde__GPU__DC__GENERICF_PRESENT__1 1
#define verde__GPU__DC__GENERICG_PRESENT 1
#define verde__GPU__DC__GENERICG_PRESENT__1 1
#define verde__GPU__DC__BLON_TYPE 0
#define verde__GPU__DC__BLON_TYPE__0 1
#define verde__GPU__DC__NB_STUTTER_MODE_PRESENT 0
#define verde__GPU__DC__NB_STUTTER_MODE_PRESENT__0 1
#define verde__GPU__DC__PCIE_REFCLK_TEST_MODE_MUX_PRESENT 0
#define verde__GPU__DC__PCIE_REFCLK_TEST_MODE_MUX_PRESENT__0 1
#define verde__GPU__DC__REFCLK_TEST_MODE_MUX_PRESENT 0
#define verde__GPU__DC__REFCLK_TEST_MODE_MUX_PRESENT__0 1
#define verde__GPU__DC__PIXCLK_TEST_MODE_MUX_PRESENT 0
#define verde__GPU__DC__PIXCLK_TEST_MODE_MUX_PRESENT__0 1
#define verde__GPU__DC__SYMCLK_TEST_MODE_MUX_PRESENT 0
#define verde__GPU__DC__SYMCLK_TEST_MODE_MUX_PRESENT__0 1
#define verde__GPU__GC__NUM_SE 1
#define verde__GPU__GC__NUM_SE__1 1
#define verde__GPU__GC__NUM_SE__0_PRESENT 1
#define verde__GPU__GC__NUM_SH_PER_SE 2
#define verde__GPU__GC__NUM_SH_PER_SE__2 1
#define verde__GPU__GC__NUM_SH_PER_SE__0_PRESENT 1
#define verde__GPU__GC__NUM_SH_PER_SE__1_PRESENT 1
#define verde__GPU__GC__NUM_RB_PER_SE 4
#define verde__GPU__GC__NUM_RB_PER_SE__4 1
#define verde__GPU__GC__NUM_RB_PER_SE__0_PRESENT 1
#define verde__GPU__GC__NUM_RB_PER_SE__1_PRESENT 1
#define verde__GPU__GC__NUM_RB_PER_SE__2_PRESENT 1
#define verde__GPU__GC__NUM_RB_PER_SE__3_PRESENT 1
#define verde__GPU__GC__NUM_CU_PER_SH 5
#define verde__GPU__GC__NUM_CU_PER_SH__5 1
#define verde__GPU__GC__NUM_CU_PER_SH__0_PRESENT 1
#define verde__GPU__GC__NUM_CU_PER_SH__1_PRESENT 1
#define verde__GPU__GC__NUM_CU_PER_SH__2_PRESENT 1
#define verde__GPU__GC__NUM_CU_PER_SH__3_PRESENT 1
#define verde__GPU__GC__NUM_CU_PER_SH__4_PRESENT 1
#define verde__GPU__GC__WAVE_SIZE 64
#define verde__GPU__GC__WAVE_SIZE__64 1
#define verde__GPU__GC__NUM_CP_RINGS 3
#define verde__GPU__GC__NUM_CP_RINGS__3 1
#define verde__GPU__GC__NUM_CP_RINGS__0_PRESENT 1
#define verde__GPU__GC__NUM_CP_RINGS__1_PRESENT 1
#define verde__GPU__GC__NUM_CP_RINGS__2_PRESENT 1
#define verde__GPU__GC__NUM_SC_PER_SE 1
#define verde__GPU__GC__NUM_SC_PER_SE__1 1
#define verde__GPU__GC__NUM_SC_PER_SE__0_PRESENT 1
#define verde__GPU__GC__NUM_BCI_PER_SE 1
#define verde__GPU__GC__NUM_BCI_PER_SE__1 1
#define verde__GPU__GC__NUM_BCI_PER_SE__0_PRESENT 1
#define verde__GPU__GC__NUM_RB_PER_SC 2
#define verde__GPU__GC__NUM_RB_PER_SC__2 1
#define verde__GPU__GC__NUM_RB_PER_SC__0_PRESENT 1
#define verde__GPU__GC__NUM_RB_PER_SC__1_PRESENT 1
#define verde__GPU__GC__NUM_RB_PER_PACKER 2
#define verde__GPU__GC__NUM_RB_PER_PACKER__2 1
#define verde__GPU__GC__NUM_RB_PER_PACKER__0_PRESENT 1
#define verde__GPU__GC__NUM_RB_PER_PACKER__1_PRESENT 1
#define verde__GPU__GC__NUM_PACKER_PER_SC 1
#define verde__GPU__GC__NUM_PACKER_PER_SC__1 1
#define verde__GPU__GC__NUM_PACKER_PER_SC__0_PRESENT 1
#define verde__GPU__GC__NUM_DB_PER_PACKER 2
#define verde__GPU__GC__NUM_DB_PER_PACKER__2 1
#define verde__GPU__GC__NUM_DB_PER_PACKER__0_PRESENT 1
#define verde__GPU__GC__NUM_DB_PER_PACKER__1_PRESENT 1
#define verde__GPU__GC__NUM_PACKER_PER_SE 1
#define verde__GPU__GC__NUM_PACKER_PER_SE__1 1
#define verde__GPU__GC__NUM_PACKER_PER_SE__0_PRESENT 1
#define verde__GPU__GC__NUM_RB_PER_SX 2
#define verde__GPU__GC__NUM_RB_PER_SX__2 1
#define verde__GPU__GC__NUM_RB_PER_SX__0_PRESENT 1
#define verde__GPU__GC__NUM_RB_PER_SX__1_PRESENT 1
#define verde__GPU__GC__NUM_CU_PER_SE 8
#define verde__GPU__GC__NUM_CU_PER_SE__8 1
#define verde__GPU__GC__NUM_CU_PER_SE__0_PRESENT 1
#define verde__GPU__GC__NUM_CU_PER_SE__1_PRESENT 1
#define verde__GPU__GC__NUM_CU_PER_SE__2_PRESENT 1
#define verde__GPU__GC__NUM_CU_PER_SE__3_PRESENT 1
#define verde__GPU__GC__NUM_CU_PER_SE__4_PRESENT 1
#define verde__GPU__GC__NUM_CU_PER_SE__5_PRESENT 1
#define verde__GPU__GC__NUM_CU_PER_SE__6_PRESENT 1
#define verde__GPU__GC__NUM_CU_PER_SE__7_PRESENT 1
#define verde__GPU__GC__MAX_NUMBER_WAVES 320
#define verde__GPU__GC__MAX_NUMBER_WAVES__320 1
#define verde__GPU__GC__MAX_NUMBER_WAVES_PER_PACKER 320
#define verde__GPU__GC__MAX_NUMBER_WAVES_PER_PACKER__320 1
#define verde__GPU__SQ__NEW_MTBUF_DSTSEL 1
#define verde__GPU__SQ__NEW_MTBUF_DSTSEL__1 1
#define verde__GPU__SQ__NUM_WAVES_PER_SIMD 10
#define verde__GPU__SQ__NUM_WAVES_PER_SIMD__10 1
#define verde__GPU__SQ__THREAD_GROUPS_PER_CU 16
#define verde__GPU__SQ__THREAD_GROUPS_PER_CU__16 1
#define verde__GPU__SQ__NUM_PERF_CNTRS 8
#define verde__GPU__SQ__NUM_PERF_CNTRS__8 1
#define verde__GPU__SQ__NUM_PERF_CNTRS__0_PRESENT 1
#define verde__GPU__SQ__NUM_PERF_CNTRS__1_PRESENT 1
#define verde__GPU__SQ__NUM_PERF_CNTRS__2_PRESENT 1
#define verde__GPU__SQ__NUM_PERF_CNTRS__3_PRESENT 1
#define verde__GPU__SQ__NUM_PERF_CNTRS__4_PRESENT 1
#define verde__GPU__SQ__NUM_PERF_CNTRS__5_PRESENT 1
#define verde__GPU__SQ__NUM_PERF_CNTRS__6_PRESENT 1
#define verde__GPU__SQ__NUM_PERF_CNTRS__7_PRESENT 1
#define verde__GPU__SQ__NUM_SGPR_PER_SIMD 512
#define verde__GPU__SQ__NUM_SGPR_PER_SIMD__512 1
#define verde__GPU__SQ__P2_IS_P1 1
#define verde__GPU__SQ__P2_IS_P1__1 1
#define verde__GPU__SQ__USE_SV_PACKAGES 0
#define verde__GPU__SQ__USE_SV_PACKAGES__0 1
#define verde__GPU__SQC__NUM_SQC 2
#define verde__GPU__SQC__NUM_SQC__2 1
#define verde__GPU__SQC__NUM_SQC__0_PRESENT 1
#define verde__GPU__SQC__NUM_SQC__1_PRESENT 1
#define verde__GPU__SQC__NUM_SQC_PER_SH 2
#define verde__GPU__SQC__NUM_SQC_PER_SH__2 1
#define verde__GPU__SQC__NUM_SQC_PER_SH__0_PRESENT 1
#define verde__GPU__SQC__NUM_SQC_PER_SH__1_PRESENT 1
#define verde__GPU__SQC__SH_SQC0_POSN_AFTER_SQ 1
#define verde__GPU__SQC__SH_SQC0_POSN_AFTER_SQ__1 1
#define verde__GPU__SQC__SH_SQC0_NUM_CU 4
#define verde__GPU__SQC__SH_SQC0_NUM_CU__4 1
#define verde__GPU__SQC__SH_SQC0_NUM_CU__0_PRESENT 1
#define verde__GPU__SQC__SH_SQC0_NUM_CU__1_PRESENT 1
#define verde__GPU__SQC__SH_SQC0_NUM_CU__2_PRESENT 1
#define verde__GPU__SQC__SH_SQC0_NUM_CU__3_PRESENT 1
#define verde__GPU__SQC__SH_SQC0_NUM_BANK 4
#define verde__GPU__SQC__SH_SQC0_NUM_BANK__4 1
#define verde__GPU__SQC__SH_SQC0_NUM_BANK__0_PRESENT 1
#define verde__GPU__SQC__SH_SQC0_NUM_BANK__1_PRESENT 1
#define verde__GPU__SQC__SH_SQC0_NUM_BANK__2_PRESENT 1
#define verde__GPU__SQC__SH_SQC0_NUM_BANK__3_PRESENT 1
#define verde__GPU__SQC__SH_SQC0_BANK_INST_CACHE_SIZE_KBYTES 8
#define verde__GPU__SQC__SH_SQC0_BANK_INST_CACHE_SIZE_KBYTES__8 1
#define verde__GPU__SQC__SH_SQC0_BANK_DATA_CACHE_SIZE_KBYTES 4
#define verde__GPU__SQC__SH_SQC0_BANK_DATA_CACHE_SIZE_KBYTES__4 1
#define verde__GPU__SQC__SH_SQC1_POSN_AFTER_SQ 5
#define verde__GPU__SQC__SH_SQC1_POSN_AFTER_SQ__5 1
#define verde__GPU__SQC__SH_SQC1_NUM_CU 4
#define verde__GPU__SQC__SH_SQC1_NUM_CU__4 1
#define verde__GPU__SQC__SH_SQC1_NUM_CU__0_PRESENT 1
#define verde__GPU__SQC__SH_SQC1_NUM_CU__1_PRESENT 1
#define verde__GPU__SQC__SH_SQC1_NUM_CU__2_PRESENT 1
#define verde__GPU__SQC__SH_SQC1_NUM_CU__3_PRESENT 1
#define verde__GPU__SQC__SH_SQC1_NUM_BANK 4
#define verde__GPU__SQC__SH_SQC1_NUM_BANK__4 1
#define verde__GPU__SQC__SH_SQC1_NUM_BANK__0_PRESENT 1
#define verde__GPU__SQC__SH_SQC1_NUM_BANK__1_PRESENT 1
#define verde__GPU__SQC__SH_SQC1_NUM_BANK__2_PRESENT 1
#define verde__GPU__SQC__SH_SQC1_NUM_BANK__3_PRESENT 1
#define verde__GPU__SQC__SH_SQC1_BANK_INST_CACHE_SIZE_KBYTES 8
#define verde__GPU__SQC__SH_SQC1_BANK_INST_CACHE_SIZE_KBYTES__8 1
#define verde__GPU__SQC__SH_SQC1_BANK_DATA_CACHE_SIZE_KBYTES 4
#define verde__GPU__SQC__SH_SQC1_BANK_DATA_CACHE_SIZE_KBYTES__4 1
#define verde__GPU__SQC__SH_SQC2_POSN_AFTER_SQ 0
#define verde__GPU__SQC__SH_SQC2_POSN_AFTER_SQ__0 1
#define verde__GPU__SQC__SH_SQC2_NUM_CU 0
#define verde__GPU__SQC__SH_SQC2_NUM_CU__0 1
#define verde__GPU__SQC__SH_SQC2_NUM_BANK 0
#define verde__GPU__SQC__SH_SQC2_NUM_BANK__0 1
#define verde__GPU__SQC__SH_SQC2_BANK_INST_CACHE_SIZE_KBYTES 0
#define verde__GPU__SQC__SH_SQC2_BANK_INST_CACHE_SIZE_KBYTES__0 1
#define verde__GPU__SQC__SH_SQC2_BANK_DATA_CACHE_SIZE_KBYTES 0
#define verde__GPU__SQC__SH_SQC2_BANK_DATA_CACHE_SIZE_KBYTES__0 1
#define verde__GPU__SQC__P2_IS_P1 1
#define verde__GPU__SQC__P2_IS_P1__1 1
#define verde__GPU__GC__GDS_EXISTS 1
#define verde__GPU__GC__GDS_EXISTS__1 1
#define verde__GPU__GC__RB_REDUNDANCY 0
#define verde__GPU__GC__RB_REDUNDANCY__0 1
#define verde__GPU__GC__SC_DOES_RB_REDUNDANCY 0
#define verde__GPU__GC__SC_DOES_RB_REDUNDANCY__0 1
#define verde__GPU__GC__MEM_ADDR_BITS 40
#define verde__GPU__GC__MEM_ADDR_BITS__40 1
#define verde__GPU__GC__NEW_VERTEX_VECTOR_ORDER 0
#define verde__GPU__GC__NEW_VERTEX_VECTOR_ORDER__0 1
#define verde__GPU__GC__NUM_INTERPS 1
#define verde__GPU__GC__NUM_INTERPS__1 1
#define verde__GPU__GC__HZ_PRESENT 1
#define verde__GPU__GC__HZ_PRESENT__1 1
#define verde__GPU__GC__NUM_CLKS_PER_PRIM 1
#define verde__GPU__GC__NUM_CLKS_PER_PRIM__1 1
#define verde__GPU__GC__NUM_INTERP_PRIM_PER_CLK 2
#define verde__GPU__GC__NUM_INTERP_PRIM_PER_CLK__2 1
#define verde__GPU__GC__ATTR_BUS_PRIM_PER_CLK 2
#define verde__GPU__GC__ATTR_BUS_PRIM_PER_CLK__2 1
#define verde__GPU__GC__NUM_MAX_GS_THDS 32
#define verde__GPU__GC__NUM_MAX_GS_THDS__32 1
#define verde__GPU__GC__NUM_MIN_GS_THDS 4
#define verde__GPU__GC__NUM_MIN_GS_THDS__4 1
#define verde__GPU__GC__NUM_STATES 8
#define verde__GPU__GC__NUM_STATES__8 1
#define verde__GPU__GC__NUM_STATES__0_PRESENT 1
#define verde__GPU__GC__NUM_STATES__1_PRESENT 1
#define verde__GPU__GC__NUM_STATES__2_PRESENT 1
#define verde__GPU__GC__NUM_STATES__3_PRESENT 1
#define verde__GPU__GC__NUM_STATES__4_PRESENT 1
#define verde__GPU__GC__NUM_STATES__5_PRESENT 1
#define verde__GPU__GC__NUM_STATES__6_PRESENT 1
#define verde__GPU__GC__NUM_STATES__7_PRESENT 1
#define verde__GPU__GC__STWTPTR_WIDTH 3
#define verde__GPU__GC__STWTPTR_WIDTH__3 1
#define verde__GPU__SH__DOUBLE_FLOAT_PRESENT 1
#define verde__GPU__SH__DOUBLE_FLOAT_PRESENT__1 1
#define verde__GPU__SH__NUM_DOUBLE_VSPS_PER_SIMD 1
#define verde__GPU__SH__NUM_DOUBLE_VSPS_PER_SIMD__1 1
#define verde__GPU__SH__NUM_DOUBLE_VSPS_PER_SIMD__0_PRESENT 1
#define verde__GPU__SH__NORM_SIN_COS 1
#define verde__GPU__SH__NORM_SIN_COS__1 1
#define verde__GPU__SH__MICROCODE_LEVEL 10
#define verde__GPU__SH__MICROCODE_LEVEL__10 1
#define verde__GPU__SH__NUM_EXPREQ_PER_CU 12
#define verde__GPU__SH__NUM_EXPREQ_PER_CU__12 1
#define verde__GPU__GC__GLOBAL_VGT_PA 0
#define verde__GPU__GC__GLOBAL_VGT_PA__0 1
#define verde__GPU__GC__NUM_FRONTEND 1
#define verde__GPU__GC__NUM_FRONTEND__1 1
#define verde__GPU__GC__NUM_FRONTEND__0_PRESENT 1
#define verde__GPU__GC__COALESCED_READ_PRESENT 1
#define verde__GPU__GC__COALESCED_READ_PRESENT__1 1
#define verde__GPU__GC__NUM_CLKS_PER_TILE 1
#define verde__GPU__GC__NUM_CLKS_PER_TILE__1 1
#define verde__GPU__GC__DBSC_TRUE_QUAD_INTF 1
#define verde__GPU__GC__DBSC_TRUE_QUAD_INTF__1 1
#define verde__GPU__GC__ASYNC_DISPATCH 1
#define verde__GPU__GC__ASYNC_DISPATCH__1 1
#define verde__GPU__GC__VMID_PORTS_EXISTS 1
#define verde__GPU__GC__VMID_PORTS_EXISTS__1 1
#define verde__GPU__GC__NUM_EXPORT_BUS 2
#define verde__GPU__GC__NUM_EXPORT_BUS__2 1
#define verde__GPU__GC__TILING_CONFIG_TABLE 1
#define verde__GPU__GC__TILING_CONFIG_TABLE__1 1
#define verde__GPU__GC__FMASK_TILING_CONFIG_TABLE 1
#define verde__GPU__GC__FMASK_TILING_CONFIG_TABLE__1 1
#define verde__GPU__GC__NEW_SRC_COLOR_FORMAT 1
#define verde__GPU__GC__NEW_SRC_COLOR_FORMAT__1 1
#define verde__GPU__SP__NUM_GPRS 256
#define verde__GPU__SP__NUM_GPRS__256 1
#define verde__GPU__SP__GPR_ADDR_WIDTH 8
#define verde__GPU__SP__GPR_ADDR_WIDTH__8 1
#define verde__GPU__SP__WIDTH_GPRS 128
#define verde__GPU__SP__WIDTH_GPRS__128 1
#define verde__GPU__SPI__TMP_SCBD_SLOTS_PER_CU 32
#define verde__GPU__SPI__TMP_SCBD_SLOTS_PER_CU__32 1
#define verde__GPU__VGT__GSPRIM_BUFF_DEPTH 768
#define verde__GPU__VGT__GSPRIM_BUFF_DEPTH__768 1
#define verde__GPU__VGT__GS_TABLE_DEPTH 16
#define verde__GPU__VGT__GS_TABLE_DEPTH__16 1
#define verde__GPU__SX__PARAMETER_CACHE_DEPTH 512
#define verde__GPU__SX__PARAMETER_CACHE_DEPTH__512 1
#define verde__GPU__SX__PARAMETER_CACHE_WIDTH 16
#define verde__GPU__SX__PARAMETER_CACHE_WIDTH__16 1
#define verde__GPU__SX__PARAMETER_CACHE_WIDTH__0_PRESENT 1
#define verde__GPU__SX__PARAMETER_CACHE_WIDTH__1_PRESENT 1
#define verde__GPU__SX__PARAMETER_CACHE_WIDTH__2_PRESENT 1
#define verde__GPU__SX__PARAMETER_CACHE_WIDTH__3_PRESENT 1
#define verde__GPU__SX__PARAMETER_CACHE_WIDTH__4_PRESENT 1
#define verde__GPU__SX__PARAMETER_CACHE_WIDTH__5_PRESENT 1
#define verde__GPU__SX__PARAMETER_CACHE_WIDTH__6_PRESENT 1
#define verde__GPU__SX__PARAMETER_CACHE_WIDTH__7_PRESENT 1
#define verde__GPU__SX__PARAMETER_CACHE_WIDTH__8_PRESENT 1
#define verde__GPU__SX__PARAMETER_CACHE_WIDTH__9_PRESENT 1
#define verde__GPU__SX__PARAMETER_CACHE_WIDTH__10_PRESENT 1
#define verde__GPU__SX__PARAMETER_CACHE_WIDTH__11_PRESENT 1
#define verde__GPU__SX__PARAMETER_CACHE_WIDTH__12_PRESENT 1
#define verde__GPU__SX__PARAMETER_CACHE_WIDTH__13_PRESENT 1
#define verde__GPU__SX__PARAMETER_CACHE_WIDTH__14_PRESENT 1
#define verde__GPU__SX__PARAMETER_CACHE_WIDTH__15_PRESENT 1
#define verde__GPU__SX__COLOR_SCOREBOARD_SLOTS 64
#define verde__GPU__SX__COLOR_SCOREBOARD_SLOTS__64 1
#define verde__GPU__SX__POS_SCOREBOARD_SLOTS 16
#define verde__GPU__SX__POS_SCOREBOARD_SLOTS__16 1
#define verde__GPU__SX__COLOR_EXPORT_BUFFER_SIZE 256
#define verde__GPU__SX__COLOR_EXPORT_BUFFER_SIZE__256 1
#define verde__GPU__SX__POS_EXPORT_BUFFER_SIZE 256
#define verde__GPU__SX__POS_EXPORT_BUFFER_SIZE__256 1
#define verde__GPU__SX__COLOR_EXPORT_REG_BUFFER_SIZE 1024
#define verde__GPU__SX__COLOR_EXPORT_REG_BUFFER_SIZE__1024 1
#define verde__GPU__SX__POS_EXPORT_REG_BUFFER_SIZE 1024
#define verde__GPU__SX__POS_EXPORT_REG_BUFFER_SIZE__1024 1
#define verde__GPU__SX__PIXEL_FIFO_DEPTH 32
#define verde__GPU__SX__PIXEL_FIFO_DEPTH__32 1
#define verde__GPU__PA__PRIM_BUFF_DEPTH 1536
#define verde__GPU__PA__PRIM_BUFF_DEPTH__1536 1
#define verde__GPU__PA__NUM_CLIPPERS 4
#define verde__GPU__PA__NUM_CLIPPERS__4 1
#define verde__GPU__PA__LOG2_MAX_SAMPLES 3
#define verde__GPU__PA__LOG2_MAX_SAMPLES__3 1
#define verde__GPU__TC__TCC_PRESENT 1
#define verde__GPU__TC__TCC_PRESENT__1 1
#define verde__GPU__TC__TCR_TCA_REQ_CREDITS 16
#define verde__GPU__TC__TCR_TCA_REQ_CREDITS__16 1
#define verde__GPU__TC__TA_HANDLE_BASEADDR 1
#define verde__GPU__TC__TA_HANDLE_BASEADDR__1 1
#define verde__GPU__TC__TCP_L1_SIZE 16
#define verde__GPU__TC__TCP_L1_SIZE__16 1
#define verde__GPU__TC__NUM_TCPS 8
#define verde__GPU__TC__NUM_TCPS__8 1
#define verde__GPU__TC__NUM_TCPS__0_PRESENT 1
#define verde__GPU__TC__NUM_TCPS__1_PRESENT 1
#define verde__GPU__TC__NUM_TCPS__2_PRESENT 1
#define verde__GPU__TC__NUM_TCPS__3_PRESENT 1
#define verde__GPU__TC__NUM_TCPS__4_PRESENT 1
#define verde__GPU__TC__NUM_TCPS__5_PRESENT 1
#define verde__GPU__TC__NUM_TCPS__6_PRESENT 1
#define verde__GPU__TC__NUM_TCPS__7_PRESENT 1
#define verde__GPU__TC__NUM_TCCS 4
#define verde__GPU__TC__NUM_TCCS__4 1
#define verde__GPU__TC__NUM_TCCS__0_PRESENT 1
#define verde__GPU__TC__NUM_TCCS__1_PRESENT 1
#define verde__GPU__TC__NUM_TCCS__2_PRESENT 1
#define verde__GPU__TC__NUM_TCCS__3_PRESENT 1
#define verde__GPU__TC__NUM_TCAS 2
#define verde__GPU__TC__NUM_TCAS__2 1
#define verde__GPU__TC__NUM_TCAS__0_PRESENT 1
#define verde__GPU__TC__NUM_TCAS__1_PRESENT 1
#define verde__GPU__TC__NUM_TCIRS 3
#define verde__GPU__TC__NUM_TCIRS__3 1
#define verde__GPU__TC__NUM_TCIRS__0_PRESENT 1
#define verde__GPU__TC__NUM_TCIRS__1_PRESENT 1
#define verde__GPU__TC__NUM_TCIRS__2_PRESENT 1
#define verde__GPU__TC__NUM_TCIWS 1
#define verde__GPU__TC__NUM_TCIWS__1 1
#define verde__GPU__TC__NUM_TCIWS__0_PRESENT 1
#define verde__GPU__TC__CLIENT_TCI_REQ_CREDITS 8
#define verde__GPU__TC__CLIENT_TCI_REQ_CREDITS__8 1
#define verde__GPU__TC__VGT_TCI_REQ_CREDITS 8
#define verde__GPU__TC__VGT_TCI_REQ_CREDITS__8 1
#define verde__GPU__TC__SQC_TCI_REQ_CREDITS 8
#define verde__GPU__TC__SQC_TCI_REQ_CREDITS__8 1
#define verde__GPU__TC__CP_TCI_REQ_CREDITS 8
#define verde__GPU__TC__CP_TCI_REQ_CREDITS__8 1
#define verde__GPU__TC__NUM_TCIS 4
#define verde__GPU__TC__NUM_TCIS__4 1
#define verde__GPU__TC__NUM_TCIS__0_PRESENT 1
#define verde__GPU__TC__NUM_TCIS__1_PRESENT 1
#define verde__GPU__TC__NUM_TCIS__2_PRESENT 1
#define verde__GPU__TC__NUM_TCIS__3_PRESENT 1
#define verde__GPU__TC__TCC_NUM_LINES 2048
#define verde__GPU__TC__TCC_NUM_LINES__2048 1
#define verde__GPU__TC__TCA_PHASE 1
#define verde__GPU__TC__TCA_PHASE__1 1
#define verde__GPU__TC__TCA_RTN_ARB_IO_PIPELINING 0
#define verde__GPU__TC__TCA_RTN_ARB_IO_PIPELINING__0 1
#define verde__GPU__TC__CP_VGT_TCI_ABOVE_SH0 0
#define verde__GPU__TC__CP_VGT_TCI_ABOVE_SH0__0 1
#define verde__GPU__DB__TB_USES_EMULATOR_MODE 0
#define verde__GPU__DB__TB_USES_EMULATOR_MODE__0 1
#define verde__GPU__DB__USE_ADDRRAXX_LIB 1
#define verde__GPU__DB__USE_ADDRRAXX_LIB__1 1
#define verde__GPU__DB__LEGACY_TILE_MODE_ASSERTS 1
#define verde__GPU__DB__LEGACY_TILE_MODE_ASSERTS__1 1
#define verde__GPU__DB__SUBBLOCK_GATES_PRESENT 0
#define verde__GPU__DB__SUBBLOCK_GATES_PRESENT__0 1
#define verde__GPU__CB__BLENDER_NUM_PIXELS 4
#define verde__GPU__CB__BLENDER_NUM_PIXELS__4 1
#define verde__GPU__CB__BLENDER_NUM_FP32_COMPS 4
#define verde__GPU__CB__BLENDER_NUM_FP32_COMPS__4 1
#define verde__GPU__CB__COMPRESSION 1
#define verde__GPU__CB__COMPRESSION__1 1
#define verde__GPU__LDS__SIZE 64
#define verde__GPU__LDS__SIZE__64 1
#define verde__GPU__LDS__NUM_PIXELS 32
#define verde__GPU__LDS__NUM_PIXELS__32 1
#define verde__GPU__LDS__NUM_BANKS 32
#define verde__GPU__LDS__NUM_BANKS__32 1
#define verde__GPU__GDS__SIZE 64
#define verde__GPU__GDS__SIZE__64 1
#define verde__GPU__GDS__NUM_PIXELS 16
#define verde__GPU__GDS__NUM_PIXELS__16 1
#define verde__GPU__GDS__NUM_PIXELS__0_PRESENT 1
#define verde__GPU__GDS__NUM_PIXELS__1_PRESENT 1
#define verde__GPU__GDS__NUM_PIXELS__2_PRESENT 1
#define verde__GPU__GDS__NUM_PIXELS__3_PRESENT 1
#define verde__GPU__GDS__NUM_PIXELS__4_PRESENT 1
#define verde__GPU__GDS__NUM_PIXELS__5_PRESENT 1
#define verde__GPU__GDS__NUM_PIXELS__6_PRESENT 1
#define verde__GPU__GDS__NUM_PIXELS__7_PRESENT 1
#define verde__GPU__GDS__NUM_PIXELS__8_PRESENT 1
#define verde__GPU__GDS__NUM_PIXELS__9_PRESENT 1
#define verde__GPU__GDS__NUM_PIXELS__10_PRESENT 1
#define verde__GPU__GDS__NUM_PIXELS__11_PRESENT 1
#define verde__GPU__GDS__NUM_PIXELS__12_PRESENT 1
#define verde__GPU__GDS__NUM_PIXELS__13_PRESENT 1
#define verde__GPU__GDS__NUM_PIXELS__14_PRESENT 1
#define verde__GPU__GDS__NUM_PIXELS__15_PRESENT 1
#define verde__GPU__GDS__NUM_BANKS 16
#define verde__GPU__GDS__NUM_BANKS__16 1
#define verde__GPU__GDS__NUM_BANKS__0_PRESENT 1
#define verde__GPU__GDS__NUM_BANKS__1_PRESENT 1
#define verde__GPU__GDS__NUM_BANKS__2_PRESENT 1
#define verde__GPU__GDS__NUM_BANKS__3_PRESENT 1
#define verde__GPU__GDS__NUM_BANKS__4_PRESENT 1
#define verde__GPU__GDS__NUM_BANKS__5_PRESENT 1
#define verde__GPU__GDS__NUM_BANKS__6_PRESENT 1
#define verde__GPU__GDS__NUM_BANKS__7_PRESENT 1
#define verde__GPU__GDS__NUM_BANKS__8_PRESENT 1
#define verde__GPU__GDS__NUM_BANKS__9_PRESENT 1
#define verde__GPU__GDS__NUM_BANKS__10_PRESENT 1
#define verde__GPU__GDS__NUM_BANKS__11_PRESENT 1
#define verde__GPU__GDS__NUM_BANKS__12_PRESENT 1
#define verde__GPU__GDS__NUM_BANKS__13_PRESENT 1
#define verde__GPU__GDS__NUM_BANKS__14_PRESENT 1
#define verde__GPU__GDS__NUM_BANKS__15_PRESENT 1
#define verde__GPU__GDS__NUM_OA_COUNTERS 4
#define verde__GPU__GDS__NUM_OA_COUNTERS__4 1
#define verde__GPU__RLC__LARGE_UCODE_RAM 1
#define verde__GPU__RLC__LARGE_UCODE_RAM__1 1
#define verde__GPU__RLC__LARGE_SCRATCH_RAM 1
#define verde__GPU__RLC__LARGE_SCRATCH_RAM__1 1
#define verde__GPU__RLC__GFX_POWER_GATING 1
#define verde__GPU__RLC__GFX_POWER_GATING__1 1
#define verde__GPU__GC__SC_BCI_16_SAMPLE_PER_PIXEL 1
#define verde__GPU__GC__SC_BCI_16_SAMPLE_PER_PIXEL__1 1
#define verde__GPU__GC__TMP_USE_RASTER_CONFIG 1
#define verde__GPU__GC__TMP_USE_RASTER_CONFIG__1 1
#define verde__GPU__GC__FLT_NORM_0_6 0
#define verde__GPU__GC__FLT_NORM_0_6__0 1
#define verde__GPU__IO__PCIE_PHY falcon65g16x
#define verde__GPU__IO__PCIE_PHY__FALCON65G16X 1
#define verde__GPU__IO__DVP_SUBMOD io_r
#define verde__GPU__IO__DVP_SUBMOD__IO_R 1
#define verde__GPU__IO__SYNC_SUBMOD io_b
#define verde__GPU__IO__SYNC_SUBMOD__IO_B 1
#define verde__GPU__IO__GENERICA_SUBMOD io_b
#define verde__GPU__IO__GENERICA_SUBMOD__IO_B 1
#define verde__GPU__IO__GENERICB_SUBMOD io_b
#define verde__GPU__IO__GENERICB_SUBMOD__IO_B 1
#define verde__GPU__IO__GENERICC_SUBMOD io_b
#define verde__GPU__IO__GENERICC_SUBMOD__IO_B 1
#define verde__GPU__IO__GENERICD_SUBMOD io_b
#define verde__GPU__IO__GENERICD_SUBMOD__IO_B 1
#define verde__GPU__IO__GENERICE_SUBMOD io_b
#define verde__GPU__IO__GENERICE_SUBMOD__IO_B 1
#define verde__GPU__IO__GENERICF_SUBMOD io_b
#define verde__GPU__IO__GENERICF_SUBMOD__IO_B 1
#define verde__GPU__IO__GENERICG_SUBMOD io_b
#define verde__GPU__IO__GENERICG_SUBMOD__IO_B 1
#define verde__GPU__IO__VID_SUBMOD io_r
#define verde__GPU__IO__VID_SUBMOD__IO_R 1
#define verde__GPU__IO__GPIO_SUBMOD io_b
#define verde__GPU__IO__GPIO_SUBMOD__IO_B 1
#define verde__GPU__IO__PLL_SUBMOD io_b
#define verde__GPU__IO__PLL_SUBMOD__IO_B 1
#define verde__GPU__IO__SPLL_SUBMOD io_b
#define verde__GPU__IO__SPLL_SUBMOD__IO_B 1
#define verde__GPU__IO__UPLL_SUBMOD io_b
#define verde__GPU__IO__UPLL_SUBMOD__IO_B 1
#define verde__GPU__IO__HPD_SUBMOD io_b
#define verde__GPU__IO__HPD_SUBMOD__IO_B 1
#define verde__GPU__IO__I2C_SUBMOD io_b
#define verde__GPU__IO__I2C_SUBMOD__IO_B 1
#define verde__GPU__IO__ASAT_45_PLL 1
#define verde__GPU__IO__ASAT_45_PLL__1 1
#define verde__GPU__IO__PWRGOOD 1
#define verde__GPU__IO__PWRGOOD__1 1
#define verde__GPU__IO__NUM_MPLL 2
#define verde__GPU__IO__NUM_MPLL__2 1
#define verde__GPU__IO__READY 1
#define verde__GPU__IO__READY__1 1
#define verde__GPU__MC__NUM_MCB_BLOCKS 1
#define verde__GPU__MC__NUM_MCB_BLOCKS__1 1
#define verde__GPU__MC__NUM_MCB_BLOCKS__0_PRESENT 1
#define verde__GPU__MC__NUM_MCB_TILES 1
#define verde__GPU__MC__NUM_MCB_TILES__1 1
#define verde__GPU__MC__NUM_MCB_TILES__0_PRESENT 1
#define verde__GPU__MC__NUM_MCD_BLOCKS 3
#define verde__GPU__MC__NUM_MCD_BLOCKS__3 1
#define verde__GPU__MC__NUM_MCD_BLOCKS__0_PRESENT 1
#define verde__GPU__MC__NUM_MCD_BLOCKS__1_PRESENT 1
#define verde__GPU__MC__NUM_MCD_BLOCKS__2_PRESENT 1
#define verde__GPU__MC__NUM_MCC_BLOCKS 2
#define verde__GPU__MC__NUM_MCC_BLOCKS__2 1
#define verde__GPU__MC__NUM_MCC_BLOCKS__0_PRESENT 1
#define verde__GPU__MC__NUM_MCC_BLOCKS__1_PRESENT 1
#define verde__GPU__MC__NUM_MCT_TILES 3
#define verde__GPU__MC__NUM_MCT_TILES__3 1
#define verde__GPU__MC__NUM_IO_CHNLS 6
#define verde__GPU__MC__NUM_IO_CHNLS__6 1
#define verde__GPU__MC__NUM_IO_CHNLS__0_PRESENT 1
#define verde__GPU__MC__NUM_IO_CHNLS__1_PRESENT 1
#define verde__GPU__MC__NUM_IO_CHNLS__2_PRESENT 1
#define verde__GPU__MC__NUM_IO_CHNLS__3_PRESENT 1
#define verde__GPU__MC__NUM_IO_CHNLS__4_PRESENT 1
#define verde__GPU__MC__NUM_IO_CHNLS__5_PRESENT 1
#define verde__GPU__MC__CDRRDBK 6
#define verde__GPU__MC__CDRRDBK__6 1
#define verde__GPU__MC__RPB_NEW_STREAM 1
#define verde__GPU__MC__RPB_NEW_STREAM__1 1
#define verde__GPU__MC__MCD0_BLOCK 1
#define verde__GPU__MC__MCD0_BLOCK__1 1
#define verde__GPU__MC__MCD1_BLOCK 1
#define verde__GPU__MC__MCD1_BLOCK__1 1
#define verde__GPU__MC__MCD2_BLOCK 1
#define verde__GPU__MC__MCD2_BLOCK__1 1
#define verde__GPU__MC__MCC0_BLOCK 1
#define verde__GPU__MC__MCC0_BLOCK__1 1
#define verde__GPU__MC__MCC1_BLOCK 1
#define verde__GPU__MC__MCC1_BLOCK__1 1
#define verde__GPU__MC__MCB_BLOCK 1
#define verde__GPU__MC__MCB_BLOCK__1 1
#define verde__GPU__MC__RB_REDUNDANCY 0
#define verde__GPU__MC__RB_REDUNDANCY__0 1
#define verde__GPU__MC__ALLOW_LARRAY 0
#define verde__GPU__MC__ALLOW_LARRAY__0 1
#define verde__GPU__MC__MCD_SRBM_PRESENT 1
#define verde__GPU__MC__MCD_SRBM_PRESENT__1 1
#define verde__GPU__MC__HDP_RD_ON_GBL1 1
#define verde__GPU__MC__HDP_RD_ON_GBL1__1 1
#define verde__GPU__MC__TWO_GBL0_RDRET 1
#define verde__GPU__MC__TWO_GBL0_RDRET__1 1
#define verde__GPU__MC__TWO_RB_PER_MCD 1
#define verde__GPU__MC__TWO_RB_PER_MCD__1 1
#define verde__GPU__MC__NUM_OF_RB_PER_MCD 2
#define verde__GPU__MC__NUM_OF_RB_PER_MCD__2 1
#define verde__GPU__MC__NUM_TC_PER_MCD 3
#define verde__GPU__MC__NUM_TC_PER_MCD__3 1
#define verde__GPU__MC__NUM_TCCS 6
#define verde__GPU__MC__NUM_TCCS__6 1
#define verde__GPU__MC__MCD0_IO0_REP 1
#define verde__GPU__MC__MCD0_IO0_REP__1 1
#define verde__GPU__MC__MCD0_IO1_REP 1
#define verde__GPU__MC__MCD0_IO1_REP__1 1
#define verde__GPU__MC__MCD1_IO0_REP 1
#define verde__GPU__MC__MCD1_IO0_REP__1 1
#define verde__GPU__MC__MCD1_IO1_REP 1
#define verde__GPU__MC__MCD1_IO1_REP__1 1
#define verde__GPU__MC__MCD2_IO0_REP 1
#define verde__GPU__MC__MCD2_IO0_REP__1 1
#define verde__GPU__MC__MCD2_IO1_REP 1
#define verde__GPU__MC__MCD2_IO1_REP__1 1
#define verde__GPU__MC__SIMPLIFIED_BLACKOUT 1
#define verde__GPU__MC__SIMPLIFIED_BLACKOUT__1 1
#define verde__GPU__MC__DDR5_MCLK_DEFAULT 5
#define verde__GPU__MC__DDR5_MCLK_DEFAULT__5 1
#define verde__GPU__MC__XBAR_REMAP 1
#define verde__GPU__MC__XBAR_REMAP__1 1
#define verde__GPU__MC__PAB_EXISTS 0
#define verde__GPU__MC__PAB_EXISTS__0 1
#define verde__GPU__MC__GPU_VIRTUAL_ADDRESS_WIDTH 40
#define verde__GPU__MC__GPU_VIRTUAL_ADDRESS_WIDTH__40 1
#define verde__GPU__MC__GPU_PHYSICAL_ADDRESS_WIDTH 40
#define verde__GPU__MC__GPU_PHYSICAL_ADDRESS_WIDTH__40 1
#define verde__GPU__MC__PCIE_VIRTUAL_ADDRESS_WIDTH 48
#define verde__GPU__MC__PCIE_VIRTUAL_ADDRESS_WIDTH__48 1
#define verde__GPU__MC__PCIE_PHYSICAL_ADDRESS_WIDTH 48
#define verde__GPU__MC__PCIE_PHYSICAL_ADDRESS_WIDTH__48 1
#define verde__GPU__MC__SPLIT_TILES 1
#define verde__GPU__MC__SPLIT_TILES__1 1
#define verde__GPU__MC__FUSION_FEATURE_ONLY 0
#define verde__GPU__MC__FUSION_FEATURE_ONLY__0 1
#define verde__GPU__MC__POWER_GATING 1
#define verde__GPU__MC__POWER_GATING__1 1
#define verde__GPU__MC__NUM_PGFSM_BLOCKS 3
#define verde__GPU__MC__NUM_PGFSM_BLOCKS__3 1
#define verde__GPU__MC__PHY_POWER_GATING 1
#define verde__GPU__MC__PHY_POWER_GATING__1 1
#define verde__GPU__VID__PRESENT 0
#define verde__GPU__VID__PRESENT__0 1
#define verde__GPU__DC__PRESENT 0
#define verde__GPU__DC__PRESENT__0 1
#define verde__GPU__AVP__PRESENT 0
#define verde__GPU__AVP__PRESENT__0 1
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#define verde__GPU__UVD__PRESENT__0 1
#define verde__ENV__GPU__UVD__HAVE_RTL 0
#define verde__ENV__GPU__UVD__HAVE_RTL__0 1
#define verde__ENV__GPU__MC__HAVE_BFM 1
#define verde__ENV__GPU__MC__HAVE_BFM__1 1
#define verde__ENV__GPU__MC__HAVE_RTL 0
#define verde__ENV__GPU__MC__HAVE_RTL__0 1
#define verde__GPU__UVD__PROJ_LARK 1
#define verde__GPU__UVD__PROJ_LARK__1 1
#define verde__GPU__UVD__CTX_ENABLE 1
#define verde__GPU__UVD__CTX_ENABLE__1 1
#define verde__GPU__UVD__MC_7XX 1
#define verde__GPU__UVD__MC_7XX__1 1
#define verde__GPU__UVD__CGC_CGTT_LOCAL_CLOCK_GATER 1
#define verde__GPU__UVD__CGC_CGTT_LOCAL_CLOCK_GATER__1 1
#define verde__GPU__MC__ARB_VM_CREDITS 32
#define verde__GPU__MC__ARB_VM_CREDITS__32 1
#define verde__GPU__MC__MCD_TLBS 4
#define verde__GPU__MC__MCD_TLBS__4 1
#define verde__GPU__MC__MCB_TLBS 3
#define verde__GPU__MC__MCB_TLBS__3 1
#define verde__GPU__MC__NO_STALL_ON_FAULT 1
#define verde__GPU__MC__NO_STALL_ON_FAULT__1 1
#define verde__GPU__MC__VMC_CACHES 2
#define verde__GPU__MC__VMC_CACHES__2 1
#define verde__GPU__MC__BIGK_CACHE_SIZE 4
#define verde__GPU__MC__BIGK_CACHE_SIZE__4 1
#define verde__GPU__MC__MCB_TLB0_CAM 5
#define verde__GPU__MC__MCB_TLB0_CAM__5 1
#define verde__GPU__MC__MCB_TLB1_CAM 4
#define verde__GPU__MC__MCB_TLB1_CAM__4 1
#define verde__GPU__MC__MCB_TLB2_CAM 4
#define verde__GPU__MC__MCB_TLB2_CAM__4 1
#define verde__GPU__MC__MCD_TLB0_CAM 4
#define verde__GPU__MC__MCD_TLB0_CAM__4 1
#define verde__GPU__MC__MCD_TLB1_CAM 4
#define verde__GPU__MC__MCD_TLB1_CAM__4 1
#define verde__GPU__MC__MCD_TLB2_CAM 4
#define verde__GPU__MC__MCD_TLB2_CAM__4 1
#define verde__GPU__MC__MCD_TLB3_CAM 4
#define verde__GPU__MC__MCD_TLB3_CAM__4 1
#define verde__GPU__MC__SEND_FREE_AT_RTN 1
#define verde__GPU__MC__SEND_FREE_AT_RTN__1 1
#define verde__GPU__MC__CONTEXT_WIDTH 3
#define verde__GPU__MC__CONTEXT_WIDTH__3 1
#define verde__GPU__MC__BUG_159204_EXISTS 1
#define verde__GPU__MC__BUG_159204_EXISTS__1 1
#endif
projects/rocr-runtime/runtime/hsa-ext-aql-profile/gfxip/gfx8/gfx8_utils.h
+98
Просмотреть файл
@@ -0,0 +1,98 @@
// Common header file for Si and Ci CommandWriter implementations
#ifndef _GFX8_UTILS_H_
#define _GFX8_UTILS_H_
#include <assert.h>
namespace pm4_profile {
namespace gfx8 {
static const uint8_t EventTypeToIndexTable[] = {
0, // Reserved_0x00 0x00000000
EVENT_WRITE_INDEX_SAMPLE_STREAMOUTSTATS, // SAMPLE_STREAMOUTSTATS1
// 0x00000001
EVENT_WRITE_INDEX_SAMPLE_STREAMOUTSTATS, // SAMPLE_STREAMOUTSTATS2
// 0x00000002
EVENT_WRITE_INDEX_SAMPLE_STREAMOUTSTATS, // SAMPLE_STREAMOUTSTATS3
// 0x00000003
EVENT_WRITE_INDEX_ANY_EOP_TIMESTAMP, // CACHE_FLUSH_TS 0x00000004
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // CONTEXT_DONE 0x00000005
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // CACHE_FLUSH 0x00000006
EVENT_WRITE_INDEX_VS_PS_PARTIAL_FLUSH, // CS_PARTIAL_FLUSH 0x00000007
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // VGT_STREAMOUT_SYNC 0x00000008
0, // Reserved_0x09 0x00000009
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // VGT_STREAMOUT_RESET 0x0000000a
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // END_OF_PIPE_INCR_DE 0x0000000b
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // END_OF_PIPE_IB_END 0x0000000c
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // RST_PIX_CNT 0x0000000d
0, // Reserved_0x0E 0x0000000e
EVENT_WRITE_INDEX_VS_PS_PARTIAL_FLUSH, // VS_PARTIAL_FLUSH 0x0000000f
EVENT_WRITE_INDEX_VS_PS_PARTIAL_FLUSH, // PS_PARTIAL_FLUSH 0x00000010
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // FLUSH_HS_OUTPUT 0x00000011
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // FLUSH_LS_OUTPUT 0x00000012
0, // Reserved_0x13 0x00000013
EVENT_WRITE_INDEX_ANY_EOP_TIMESTAMP, // CACHE_FLUSH_AND_INV_TS_EVENT
// 0x00000014
EVENT_WRITE_INDEX_ZPASS_DONE, // ZPASS_DONE 0x00000015
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // CACHE_FLUSH_AND_INV_EVENT
// 0x00000016
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // PERFCOUNTER_START 0x00000017
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // PERFCOUNTER_STOP 0x00000018
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // PIPELINESTAT_START 0x00000019
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // PIPELINESTAT_STOP 0x0000001a
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // PERFCOUNTER_SAMPLE 0x0000001b
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // FLUSH_ES_OUTPUT 0x0000001c
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // FLUSH_GS_OUTPUT 0x0000001d
EVENT_WRITE_INDEX_SAMPLE_PIPELINESTAT, // SAMPLE_PIPELINESTAT 0x0000001e
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // SO_VGTSTREAMOUT_FLUSH 0x0000001f
EVENT_WRITE_INDEX_SAMPLE_STREAMOUTSTATS, // SAMPLE_STREAMOUTSTATS
// 0x00000020
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // RESET_VTX_CNT 0x00000021
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // BLOCK_CONTEXT_DONE 0x00000022
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // CS_CONTEXT_DONE 0x00000023
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // VGT_FLUSH 0x00000024
0, // Reserved_0x25 0x00000025
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // SQ_NON_EVENT 0x00000026
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // SC_SEND_DB_VPZ 0x00000027
EVENT_WRITE_INDEX_ANY_EOP_TIMESTAMP, // BOTTOM_OF_PIPE_TS 0x00000028
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // FLUSH_SX_TS 0x00000029
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // DB_CACHE_FLUSH_AND_INV 0x0000002a
EVENT_WRITE_INDEX_ANY_EOP_TIMESTAMP, // FLUSH_AND_INV_DB_DATA_TS 0x0000002b
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // FLUSH_AND_INV_DB_META 0x0000002c
EVENT_WRITE_INDEX_ANY_EOP_TIMESTAMP, // FLUSH_AND_INV_CB_DATA_TS 0x0000002d
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // FLUSH_AND_INV_CB_META 0x0000002e
EVENT_WRITE_EOS_INDEX_CSDONE_PSDONE, // CS_DONE 0x0000002f
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // PS_DONE 0x00000030
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // FLUSH_AND_INV_CB_PIXEL_DATA
// 0x00000031
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // SX_CB_RAT_ACK_REQUEST 0x00000032
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // THREAD_TRACE_START 0x00000033
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // THREAD_TRACE_STOP 0x00000034
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // THREAD_TRACE_MARKER 0x00000035
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // THREAD_TRACE_FLUSH 0x00000036
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // THREAD_TRACE_FINISH 0x00000037
};
/// @brief Enum specifying the size of elements of a buffer
enum BufElementSize {
kBufElementSize2 = 0,
kBufElementSize4 = 1,
kBufElementSize8 = 2,
kBufElementSize16 = 3
};
/// @brief Enum specifying the striding of a buffer
enum BufIndexStride {
kBufIndexStride8 = 0,
kBufIndexStride16 = 1,
kBufIndexStride32 = 2,
kBufIndexStride64 = 3
};
} // gfx8
} // pm4_profile
#endif // _GFX8_UTILS_H_
projects/rocr-runtime/runtime/hsa-ext-aql-profile/gfxip/gfx8/si_ci_vi_merged_enum.h
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projects/rocr-runtime/runtime/hsa-ext-aql-profile/gfxip/gfx8/si_ci_vi_merged_mask.h
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projects/rocr-runtime/runtime/hsa-ext-aql-profile/gfxip/gfx8/si_ci_vi_merged_offset.h
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projects/rocr-runtime/runtime/hsa-ext-aql-profile/gfxip/gfx8/si_ci_vi_merged_pm4_it_opcodes.h
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//////////////////////////////////////////////////////////////////////////////////
// THIS FILE IS AUTO-GENERATED BY PITGEN (vA)
// !!!! DO NOT EDIT BY HAND !!!!
//////////////////////////////////////////////////////////////////////////////////
// Project: 10xx or later
// Description:
//
// PM4 PacketType3 IT_OpCode Definitions
// Extracted From ME and PFP F32 Microcode Jump Tables:
//
//////////////////////////////////////////////////////////////////////////////////
//
// Trade secret of ATI Technologies, Inc.
// Copyright 1999, ATI Technologies, Inc., (unpublished)
//
// All rights reserved. This notice is intended as a precaution against
// inadvertent publication and does not imply publication or any waiver
// of confidentiality. The year included in the foregoing notice is the
// year of creation of the work.
//////////////////////////////////////////////////////////////////////////////////
#ifndef PM4_IT_OPCODES_H
#define PM4_IT_OPCODES_H
enum IT_OpCodeType {
IT_NOP = 0x10,
IT_SET_BASE = 0x11,
IT_CLEAR_STATE = 0x12,
IT_INDEX_BUFFER_SIZE = 0x13,
IT_DISPATCH_DIRECT = 0x15,
IT_DISPATCH_INDIRECT = 0x16,
IT_INDIRECT_BUFFER_END = 0x17,
IT_INDIRECT_BUFFER_CNST_END = 0x19,
IT_ALLOC_GDS__SI = 0x1B,
IT_WRITE_GDS_RAM__SI = 0x1C,
IT_ATOMIC_GDS = 0x1D,
IT_ATOMIC__SI__VI = 0x1E,
IT_OCCLUSION_QUERY = 0x1F,
IT_SET_PREDICATION = 0x20,
IT_REG_RMW = 0x21,
IT_COND_EXEC = 0x22,
IT_PRED_EXEC = 0x23,
IT_DRAW_INDIRECT = 0x24,
IT_DRAW_INDEX_INDIRECT = 0x25,
IT_INDEX_BASE = 0x26,
IT_DRAW_INDEX_2 = 0x27,
IT_CONTEXT_CONTROL = 0x28,
IT_INDEX_TYPE = 0x2A,
IT_DRAW_INDIRECT_MULTI = 0x2C,
IT_DRAW_INDEX_AUTO = 0x2D,
IT_DRAW_INDEX_IMMD__SI = 0x2E,
IT_NUM_INSTANCES = 0x2F,
IT_DRAW_INDEX_MULTI_AUTO = 0x30,
IT_INDIRECT_BUFFER_CNST_PRIV__SI = 0x31,
IT_INDIRECT_BUFFER_PRIV = 0x32,
IT_INDIRECT_BUFFER_CNST = 0x33,
IT_STRMOUT_BUFFER_UPDATE = 0x34,
IT_DRAW_INDEX_OFFSET_2 = 0x35,
IT_WRITE_DATA = 0x37,
IT_DRAW_INDEX_INDIRECT_MULTI = 0x38,
IT_MEM_SEMAPHORE = 0x39,
IT_MPEG_INDEX__SI = 0x3A,
IT_COPY_DW__SI__CI = 0x3B,
IT_WAIT_REG_MEM = 0x3C,
IT_MEM_WRITE__SI = 0x3D,
IT_INDIRECT_BUFFER = 0x3F,
IT_COPY_DATA = 0x40,
IT_CP_DMA = 0x41,
IT_PFP_SYNC_ME = 0x42,
IT_SURFACE_SYNC = 0x43,
IT_ME_INITIALIZE = 0x44,
IT_COND_WRITE = 0x45,
IT_EVENT_WRITE = 0x46,
IT_EVENT_WRITE_EOP = 0x47,
IT_EVENT_WRITE_EOS = 0x48,
IT_PREAMBLE_CNTL = 0x4A,
IT_GFX_CNTX_UPDATE = 0x52,
IT_BLK_CNTX_UPDATE = 0x53,
IT_INCR_UPDT_STATE = 0x55,
IT_ONE_REG_WRITE__SI = 0x57,
IT_LOAD_SH_REG = 0x5F,
IT_LOAD_CONFIG_REG = 0x60,
IT_LOAD_CONTEXT_REG = 0x61,
IT_SET_CONFIG_REG = 0x68,
IT_SET_CONTEXT_REG = 0x69,
IT_SET_SH_REG_DI = 0x72,
IT_SET_CONTEXT_REG_INDIRECT = 0x73,
IT_SET_SH_REG = 0x76,
IT_SET_SH_REG_OFFSET = 0x77,
IT_ME_WRITE__SI = 0x7A,
IT_PFP_WRITE__SI = 0x7B,
IT_SCRATCH_RAM_WRITE = 0x7D,
IT_SCRATCH_RAM_READ = 0x7E,
IT_CE_WRITE__SI = 0x7F,
IT_LOAD_CONST_RAM = 0x80,
IT_WRITE_CONST_RAM = 0x81,
IT_WRITE_CONST_RAM_OFFSET__SI = 0x82,
IT_DUMP_CONST_RAM = 0x83,
IT_INCREMENT_CE_COUNTER = 0x84,
IT_INCREMENT_DE_COUNTER = 0x85,
IT_WAIT_ON_CE_COUNTER = 0x86,
IT_WAIT_ON_DE_COUNTER__SI = 0x87,
IT_WAIT_ON_DE_COUNTER_DIFF = 0x88,
IT_SET_CE_DE_COUNTERS__SI = 0x89,
IT_WAIT_ON_AVAIL_BUFFER__SI = 0x8A,
IT_SWITCH_BUFFER = 0x8B,
IT_FORWARD_HEADER = 0x7C,
IT_ATOMIC_MEM__CI = 0x1E,
IT_DRAW_PREAMBLE__CI__VI = 0x36,
IT_RELEASE_MEM__CI__VI = 0x49,
IT_DMA_DATA__CI__VI = 0x50,
IT_ACQUIRE_MEM__CI__VI = 0x58,
IT_REWIND__CI__VI = 0x59,
IT_INTERRUPT__CI__VI = 0x5A,
IT_LOAD_UCONFIG_REG__CI__VI = 0x5E,
IT_SET_QUEUE_REG__CI__VI = 0x78,
IT_SET_UCONFIG_REG__CI__VI = 0x79,
IT_EOP_BUFFER_END__CI__VI = 0x18,
IT_INTR_BUFFER_END__CI__VI = 0x1A,
IT_RUN_LIST__CI = 0x3E,
IT_SET_RESOURCES__CI__VI = 0xA0,
IT_MAP_PROCESS__CI__VI = 0xA1,
IT_MAP_QUEUES__CI__VI = 0xA2,
IT_QUERY_STATUS__CI = 0xA3,
IT_UNMAP_QUEUES__CI = 0xA4,
IT_COND_PREEMPT__VI = 0x8E,
IT_DISPATCH_DRAW_PREAMBLE__VI = 0x8C,
IT_DISPATCH_DRAW__VI = 0x8D,
IT_DISPATCH_DRAW_PREAMBLE_ACE__VI = 0x8C,
IT_DISPATCH_DRAW_ACE__VI = 0x8D,
IT_PRIME_ATCL2__VI = 0x8E,
IT_UNMAP_QUEUES__VI = 0xA3,
IT_QUERY_STATUS__VI = 0xA4,
IT_RUN_LIST__VI = 0xA5,
};
#define PM4_TYPE_0 0
#define PM4_TYPE_2 2
#define PM4_TYPE_3 3
#endif // PM4_IT_OPCODES_H
projects/rocr-runtime/runtime/hsa-ext-aql-profile/gfxip/gfx8/si_ci_vi_merged_pm4cmds.h
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/*
***************************************************************************************************
*
* Trade secret of Advanced Micro Devices, Inc.
* Copyright (c) 2010 Advanced Micro Devices, Inc. (unpublished)
*
* All rights reserved. This notice is intended as a precaution against inadvertent publication and
* does not imply publication or any waiver of confidentiality. The year included in the foregoing
* notice is the year of creation of the work.
*
***************************************************************************************************
*/
#ifndef _SI_CI_VI_PM4CMDS_H_
#define _SI_CI_VI_PM4CMDS_H_
/******************************************************************************
*
* si_ci_vi_merged_pm4cmds.h
*
* SI PM4 definitions, typedefs, and enumerations.
*
******************************************************************************/
#include "si_pm4defs.h"
#include "si_ci_vi_merged_pm4_it_opcodes.h"
// Wrapper on the new header-generation macro
#define PM4_CMD(op, count) PM4_TYPE_3_HDR(op, count, ShaderGraphics, PredDisable)
// IT_DRAW_INDEX is replaced by IT_DRAW_INDEX_2
#define PM4_CMD_DRAW_INDEX_2(count) PM4_CMD(IT_DRAW_INDEX_2, count)
#define PM4_CMD_DRAW_INDEX_AUTO(count) PM4_CMD(IT_DRAW_INDEX_AUTO, count)
#define PM4_CMD_DRAW_INDEX_IMMD_SI(count) PM4_CMD(IT_DRAW_INDEX_IMMD__SI, count)
#define PM4_CMD_DRAW_INDEX_TYPE(count) PM4_CMD(IT_INDEX_TYPE, count)
#define PM4_CMD_DRAW_NUM_INSTANCES(count) PM4_CMD(IT_NUM_INSTANCES, count)
#define PM4_CMD_DRAW_PREAMBLE(count) PM4_CMD(IT_DRAW_PREAMBLE__CI__VI, count)
#define PM4_CMD_WAIT_REG_MEM(count) PM4_CMD(IT_WAIT_REG_MEM, count)
#define PM4_CMD_MEM_WRITE(count) PM4_CMD(IT_MEM_WRITE, count)
#define PM4_CMD_EVENT_WRITE(count) PM4_CMD(IT_EVENT_WRITE, count)
#define PM4_CMD_EVENT_WRITE_EOP(count) PM4_CMD(IT_EVENT_WRITE_EOP, count)
#define PM4_CMD_STRMOUT_BUFFER_UPDATE(count) PM4_CMD(IT_STRMOUT_BUFFER_UPDATE, count)
#define PM4_CMD_COPY_DATA(count) PM4_CMD(IT_COPY_DATA, count)
#define PM4_CMD_CP_DMA(count) PM4_CMD(IT_CP_DMA, count)
#define PM4_CMD_SET_PREDICATION(count) PM4_CMD(IT_SET_PREDICATION, count)
#define PM4_CMD_SURFACE_BASE_UPDATE(count) PM4_CMD(IT_SURFACE_BASE_UPDATE, count)
#define PM4_CMD_STRMOUT_BASE_UPDATE(count) PM4_CMD(IT_STRMOUT_BASE_UPDATE, count)
#define PM4_CMD_START_3D_CMDBUF(count) PM4_CMD(IT_START_3D_CMDBUF, count)
#define PM4_CMD_ROLL_CONTEXT(count) PM4_CMD(IT_ROLL_CONTEXT, count)
#define PM4_CMD_CONTEXT_CTL(count) PM4_CMD(IT_CONTEXT_CONTROL, count)
#define PM4_CMD_PRED_EXEC PM4_CMD(IT_PRED_EXEC, 2)
#define PM4_CMD_SURFACE_SYNC(count) PM4_CMD(IT_SURFACE_SYNC, count)
#define PM4_CMD_LOAD_CONFIG_REG(count) PM4_CMD(IT_LOAD_CONFIG_REG, count)
#define PM4_CMD_LOAD_CONTEXT_REG(count) PM4_CMD(IT_LOAD_CONTEXT_REG, count)
#define PM4_CMD_LOAD_SH_REG(count) PM4_CMD(IT_LOAD_SH_REG, count)
#define PM4_CMD_SET_CONFIG_REG(count) PM4_CMD(IT_SET_CONFIG_REG, count)
#define PM4_CMD_SET_CONTEXT_REG(count) PM4_CMD(IT_SET_CONTEXT_REG, count)
#define PM4_CMD_SET_SH_REG(count) PM4_CMD(IT_SET_SH_REG, count)
#define PM4_CMD_INDIRECT_BUFFER_CNST_END(count) PM4_CMD(IT_INDIRECT_BUFFER_CNST_END, count)
#define PM4_CMD_INDIRECT_BUFFER_CNST_PRIV(count) PM4_CMD(IT_INDIRECT_BUFFER_CNST_PRIV, count)
#define PM4_CMD_INDIRECT_BUFFER_CNST(count) PM4_CMD(IT_INDIRECT_BUFFER_CNST, count)
#define PM4_CMD_LOAD_CONST_RAM(count) PM4_CMD(IT_LOAD_CONST_RAM, count)
#define PM4_CMD_WRITE_CONST_RAM(count) PM4_CMD(IT_WRITE_CONST_RAM, count)
#define PM4_CMD_DUMP_CONST_RAM(count) PM4_CMD(IT_DUMP_CONST_RAM, count)
#define PM4_CMD_INC_CE_COUNTER(count) PM4_CMD(IT_INCREMENT_CE_COUNTER, count)
#define PM4_CMD_INC_DE_COUNTER(count) PM4_CMD(IT_INCREMENT_DE_COUNTER, count)
#define PM4_CMD_WAIT_ON_CE_COUNTER(count) PM4_CMD(IT_WAIT_ON_CE_COUNTER, count)
#define PM4_CMD_WAIT_ON_DE_COUNTER_DIFF(count) PM4_CMD(IT_WAIT_ON_DE_COUNTER_DIFF, count)
#define PM4_CMD_WRITE_DATA(count) PM4_CMD(IT_WRITE_DATA, count)
#endif // _SI_CI_VI_PM4CMDS_H_
projects/rocr-runtime/runtime/hsa-ext-aql-profile/gfxip/gfx8/si_ci_vi_merged_shift.h
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projects/rocr-runtime/runtime/hsa-ext-aql-profile/gfxip/gfx8/si_ci_vi_merged_sq_reg.h
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projects/rocr-runtime/runtime/hsa-ext-aql-profile/gfxip/gfx8/si_ci_vi_merged_sq_uc_reg.h
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projects/rocr-runtime/runtime/hsa-ext-aql-profile/gfxip/gfx8/si_ci_vi_merged_typedef.h
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projects/rocr-runtime/runtime/hsa-ext-aql-profile/gfxip/gfx8/si_pm4defs.h
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projects/rocr-runtime/runtime/hsa-ext-aql-profile/gfxip/gfx9/f32_ce_pm4_packets_vg10.h
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//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
//
// Trade secret of Advanced Micro Devices, Inc.
// Copyright 2014, Advanced Micro Devices, Inc., (unpublished)
//
// All rights reserved. This notice is intended as a precaution against
// inadvertent publication and does not imply publication or any waiver
// of confidentiality. The year included in the foregoing notice is the
// year of creation of the work.
//
//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
#ifndef F32_CE_PM4_PACKETS_H
#define F32_CE_PM4_PACKETS_H
namespace pm4_profile {
namespace gfx9 {
#ifndef PM4_CE_HEADER_DEFINED
#define PM4_CE_HEADER_DEFINED
typedef union PM4_CE_TYPE_3_HEADER {
struct {
uint32_t reserved1 : 8; ///< reserved
uint32_t opcode : 8; ///< IT opcode
uint32_t count : 14; ///< number of DWORDs - 1 in the information body.
uint32_t type : 2; ///< packet identifier. It should be 3 for type 3 packets
};
uint32_t u32All;
} PM4_CE_TYPE_3_HEADER;
#endif // PM4_CE_HEADER_DEFINED
//--------------------CE_COND_EXEC--------------------
#ifndef PM4_CE_COND_EXEC_DEFINED
#define PM4_CE_COND_EXEC_DEFINED
typedef struct PM4_CE_COND_EXEC {
union {
PM4_CE_TYPE_3_HEADER header; /// header
uint32_t ordinal1;
};
union {
struct {
uint32_t reserved1 : 2;
uint32_t addr_lo : 30;
} bitfields2;
uint32_t ordinal2;
};
uint32_t addr_hi;
uint32_t reserved2;
union {
struct {
uint32_t exec_count : 14;
uint32_t reserved3 : 18;
} bitfields5;
uint32_t ordinal5;
};
} PM4CE_COND_EXEC, *PPM4CE_COND_EXEC;
#endif
//--------------------CE_CONTEXT_CONTROL--------------------
#ifndef PM4_CE_CONTEXT_CONTROL_DEFINED
#define PM4_CE_CONTEXT_CONTROL_DEFINED
typedef struct PM4_CE_CONTEXT_CONTROL {
union {
PM4_CE_TYPE_3_HEADER header; /// header
uint32_t ordinal1;
};
union {
struct {
uint32_t reserved1 : 28;
uint32_t load_ce_ram : 1;
uint32_t reserved2 : 2;
uint32_t load_enable : 1;
} bitfields2;
uint32_t ordinal2;
};
uint32_t reserved3;
} PM4CE_CONTEXT_CONTROL, *PPM4CE_CONTEXT_CONTROL;
#endif
//--------------------CE_COPY_DATA--------------------
#ifndef PM4_CE_COPY_DATA_DEFINED
#define PM4_CE_COPY_DATA_DEFINED
enum CE_COPY_DATA_src_sel_enum {
src_sel__ce_copy_data__mem_mapped_register = 0,
src_sel__ce_copy_data__memory = 1,
src_sel__ce_copy_data__tc_l2 = 2,
src_sel__ce_copy_data__immediate_data = 5
};
enum CE_COPY_DATA_dst_sel_enum {
dst_sel__ce_copy_data__mem_mapped_register = 0,
dst_sel__ce_copy_data__tc_l2 = 2,
dst_sel__ce_copy_data__memory = 5
};
enum CE_COPY_DATA_src_cache_policy_enum {
src_cache_policy__ce_copy_data__lru = 0,
src_cache_policy__ce_copy_data__stream = 1
};
enum CE_COPY_DATA_count_sel_enum {
count_sel__ce_copy_data__32_bits_of_data = 0,
count_sel__ce_copy_data__64_bits_of_data = 1
};
enum CE_COPY_DATA_wr_confirm_enum {
wr_confirm__ce_copy_data__do_not_wait_for_confirmation = 0,
wr_confirm__ce_copy_data__wait_for_confirmation = 1
};
enum CE_COPY_DATA_dst_cache_policy_enum {
dst_cache_policy__ce_copy_data__lru = 0,
dst_cache_policy__ce_copy_data__stream = 1
};
enum CE_COPY_DATA_engine_sel_enum { engine_sel__ce_copy_data__constant_engine = 2 };
typedef struct PM4_CE_COPY_DATA {
union {
PM4_CE_TYPE_3_HEADER header; /// header
uint32_t ordinal1;
};
union {
struct {
CE_COPY_DATA_src_sel_enum src_sel : 4;
uint32_t reserved1 : 4;
CE_COPY_DATA_dst_sel_enum dst_sel : 4;
uint32_t reserved2 : 1;
CE_COPY_DATA_src_cache_policy_enum src_cache_policy : 2;
uint32_t reserved3 : 1;
CE_COPY_DATA_count_sel_enum count_sel : 1;
uint32_t reserved4 : 3;
CE_COPY_DATA_wr_confirm_enum wr_confirm : 1;
uint32_t reserved5 : 4;
CE_COPY_DATA_dst_cache_policy_enum dst_cache_policy : 2;
uint32_t reserved6 : 3;
CE_COPY_DATA_engine_sel_enum engine_sel : 2;
} bitfields2;
uint32_t ordinal2;
};
union {
struct {
uint32_t src_reg_offset : 18;
uint32_t reserved7 : 14;
} bitfields3a;
struct {
uint32_t reserved8 : 2;
uint32_t src_32b_addr_lo : 30;
} bitfields3b;
struct {
uint32_t reserved9 : 3;
uint32_t src_64b_addr_lo : 29;
} bitfields3c;
uint32_t imm_data;
uint32_t ordinal3;
};
union {
uint32_t src_memtc_addr_hi;
uint32_t src_imm_data;
uint32_t ordinal4;
};
union {
struct {
uint32_t dst_reg_offset : 18;
uint32_t reserved10 : 14;
} bitfields5a;
struct {
uint32_t reserved11 : 2;
uint32_t dst_32b_addr_lo : 30;
} bitfields5b;
struct {
uint32_t reserved12 : 3;
uint32_t dst_64b_addr_lo : 29;
} bitfields5c;
uint32_t ordinal5;
};
uint32_t dst_addr_hi;
} PM4CE_COPY_DATA, *PPM4CE_COPY_DATA;
#endif
//--------------------CE_DUMP_CONST_RAM--------------------
#ifndef PM4_CE_DUMP_CONST_RAM_DEFINED
#define PM4_CE_DUMP_CONST_RAM_DEFINED
enum CE_DUMP_CONST_RAM_cache_policy_enum {
cache_policy__ce_dump_const_ram__lru = 0,
cache_policy__ce_dump_const_ram__stream = 1,
cache_policy__ce_dump_const_ram__bypass = 2
};
typedef struct PM4_CE_DUMP_CONST_RAM {
union {
PM4_CE_TYPE_3_HEADER header; /// header
uint32_t ordinal1;
};
union {
struct {
uint32_t offset : 16;
uint32_t reserved1 : 9;
CE_DUMP_CONST_RAM_cache_policy_enum cache_policy : 2;
uint32_t reserved2 : 3;
uint32_t increment_cs : 1;
uint32_t increment_ce : 1;
} bitfields2;
uint32_t ordinal2;
};
union {
struct {
uint32_t num_dw : 15;
uint32_t reserved3 : 17;
} bitfields3;
uint32_t ordinal3;
};
uint32_t addr_lo;
uint32_t addr_hi;
} PM4CE_DUMP_CONST_RAM, *PPM4CE_DUMP_CONST_RAM;
#endif
//--------------------CE_DUMP_CONST_RAM_OFFSET--------------------
#ifndef PM4_CE_DUMP_CONST_RAM_OFFSET_DEFINED
#define PM4_CE_DUMP_CONST_RAM_OFFSET_DEFINED
enum CE_DUMP_CONST_RAM_OFFSET_cache_policy_enum {
cache_policy__ce_dump_const_ram_offset__lru = 0,
cache_policy__ce_dump_const_ram_offset__stream = 1,
cache_policy__ce_dump_const_ram_offset__bypass = 2
};
typedef struct PM4_CE_DUMP_CONST_RAM_OFFSET {
union {
PM4_CE_TYPE_3_HEADER header; /// header
uint32_t ordinal1;
};
union {
struct {
uint32_t offset : 16;
uint32_t reserved1 : 9;
CE_DUMP_CONST_RAM_OFFSET_cache_policy_enum cache_policy : 2;
uint32_t reserved2 : 3;
uint32_t increment_cs : 1;
uint32_t increment_ce : 1;
} bitfields2;
uint32_t ordinal2;
};
union {
struct {
uint32_t num_dw : 15;
uint32_t reserved3 : 17;
} bitfields3;
uint32_t ordinal3;
};
uint32_t addr_offset;
} PM4CE_DUMP_CONST_RAM_OFFSET, *PPM4CE_DUMP_CONST_RAM_OFFSET;
#endif
//--------------------CE_FRAME_CONTROL--------------------
#ifndef PM4_CE_FRAME_CONTROL_DEFINED
#define PM4_CE_FRAME_CONTROL_DEFINED
enum CE_FRAME_CONTROL_command_enum {
command__ce_frame_control__tmz_begin = 0,
command__ce_frame_control__tmz_end = 1
};
typedef struct PM4_CE_FRAME_CONTROL {
union {
PM4_CE_TYPE_3_HEADER header; /// header
uint32_t ordinal1;
};
union {
struct {
uint32_t tmz : 1;
uint32_t reserved1 : 27;
CE_FRAME_CONTROL_command_enum command : 4;
} bitfields2;
uint32_t ordinal2;
};
} PM4CE_FRAME_CONTROL, *PPM4CE_FRAME_CONTROL;
#endif
//--------------------CE_INCREMENT_CE_COUNTER--------------------
#ifndef PM4_CE_INCREMENT_CE_COUNTER_DEFINED
#define PM4_CE_INCREMENT_CE_COUNTER_DEFINED
enum CE_INCREMENT_CE_COUNTER_cntrsel_enum {
cntrsel__ce_increment_ce_counter__invalid = 0,
cntrsel__ce_increment_ce_counter__increment_ce_counter = 1,
cntrsel__ce_increment_ce_counter__increment_cs_counter = 2,
cntrsel__ce_increment_ce_counter__increment_ce_and_cs_counters = 3
};
typedef struct PM4_CE_INCREMENT_CE_COUNTER {
union {
PM4_CE_TYPE_3_HEADER header; /// header
uint32_t ordinal1;
};
union {
struct {
CE_INCREMENT_CE_COUNTER_cntrsel_enum cntrsel : 2;
uint32_t reserved1 : 30;
} bitfields2;
uint32_t ordinal2;
};
} PM4CE_INCREMENT_CE_COUNTER, *PPM4CE_INCREMENT_CE_COUNTER;
#endif
//--------------------CE_INDIRECT_BUFFER_CONST--------------------
#ifndef PM4_CE_INDIRECT_BUFFER_CONST_DEFINED
#define PM4_CE_INDIRECT_BUFFER_CONST_DEFINED
typedef struct PM4_CE_INDIRECT_BUFFER_CONST {
union {
PM4_CE_TYPE_3_HEADER header; /// header
uint32_t ordinal1;
};
union {
struct {
uint32_t reserved1 : 2;
uint32_t ib_base_lo : 30;
} bitfields2;
uint32_t ordinal2;
};
uint32_t ib_base_hi;
union {
struct {
uint32_t ib_size : 20;
uint32_t chain : 1;
uint32_t pre_ena : 1;
uint32_t reserved2 : 2;
uint32_t vmid : 4;
uint32_t cache_policy : 2;
uint32_t pre_resume : 1;
uint32_t priv : 1;
} bitfields4;
uint32_t ordinal4;
};
} PM4CE_INDIRECT_BUFFER_CONST, *PPM4CE_INDIRECT_BUFFER_CONST;
#endif
//--------------------CE_LOAD_CONST_RAM--------------------
#ifndef PM4_CE_LOAD_CONST_RAM_DEFINED
#define PM4_CE_LOAD_CONST_RAM_DEFINED
enum CE_LOAD_CONST_RAM_cache_policy_enum {
cache_policy__ce_load_const_ram__lru = 0,
cache_policy__ce_load_const_ram__stream = 1
};
typedef struct PM4_CE_LOAD_CONST_RAM {
union {
PM4_CE_TYPE_3_HEADER header; /// header
uint32_t ordinal1;
};
uint32_t addr_lo;
uint32_t addr_hi;
union {
struct {
uint32_t num_dw : 15;
uint32_t reserved1 : 17;
} bitfields4;
uint32_t ordinal4;
};
union {
struct {
uint32_t start_addr : 16;
uint32_t reserved2 : 9;
CE_LOAD_CONST_RAM_cache_policy_enum cache_policy : 2;
uint32_t reserved3 : 5;
} bitfields5;
uint32_t ordinal5;
};
} PM4CE_LOAD_CONST_RAM, *PPM4CE_LOAD_CONST_RAM;
#endif
//--------------------CE_NOP--------------------
#ifndef PM4_CE_NOP_DEFINED
#define PM4_CE_NOP_DEFINED
typedef struct PM4_CE_NOP {
union {
PM4_CE_TYPE_3_HEADER header; /// header
uint32_t ordinal1;
};
// uint32_t data_block[]; // N-DWords
} PM4CE_NOP, *PPM4CE_NOP;
#endif
//--------------------CE_PRIME_UTCL2--------------------
#ifndef PM4_CE_PRIME_UTCL2_DEFINED
#define PM4_CE_PRIME_UTCL2_DEFINED
enum CE_PRIME_UTCL2_cache_perm_enum {
cache_perm__ce_prime_utcl2__read = 0,
cache_perm__ce_prime_utcl2__write = 1,
cache_perm__ce_prime_utcl2__execute = 2
};
enum CE_PRIME_UTCL2_prime_mode_enum {
prime_mode__ce_prime_utcl2__dont_wait_for_xack = 0,
prime_mode__ce_prime_utcl2__wait_for_xack = 1
};
enum CE_PRIME_UTCL2_engine_sel_enum { engine_sel__ce_prime_utcl2__constant_engine = 2 };
typedef struct PM4_CE_PRIME_UTCL2 {
union {
PM4_CE_TYPE_3_HEADER header; /// header
uint32_t ordinal1;
};
union {
struct {
CE_PRIME_UTCL2_cache_perm_enum cache_perm : 3;
CE_PRIME_UTCL2_prime_mode_enum prime_mode : 1;
uint32_t reserved1 : 26;
CE_PRIME_UTCL2_engine_sel_enum engine_sel : 2;
} bitfields2;
uint32_t ordinal2;
};
uint32_t addr_lo;
uint32_t addr_hi;
union {
struct {
uint32_t requested_pages : 14;
uint32_t reserved2 : 18;
} bitfields5;
uint32_t ordinal5;
};
} PM4CE_PRIME_UTCL2, *PPM4CE_PRIME_UTCL2;
#endif
//--------------------CE_SET_BASE--------------------
#ifndef PM4_CE_SET_BASE_DEFINED
#define PM4_CE_SET_BASE_DEFINED
enum CE_SET_BASE_base_index_enum {
base_index__ce_set_base__ce_dst_base_addr = 2,
base_index__ce_set_base__ce_partition_bases = 3
};
typedef struct PM4_CE_SET_BASE {
union {
PM4_CE_TYPE_3_HEADER header; /// header
uint32_t ordinal1;
};
union {
struct {
CE_SET_BASE_base_index_enum base_index : 4;
uint32_t reserved1 : 28;
} bitfields2;
uint32_t ordinal2;
};
union {
struct {
uint32_t reserved2 : 3;
uint32_t address_lo : 29;
} bitfields3a;
struct {
uint32_t cs1_index : 16;
uint32_t reserved3 : 16;
} bitfields3b;
uint32_t ordinal3;
};
union {
uint32_t address_hi;
struct {
uint32_t cs2_index : 16;
uint32_t reserved4 : 16;
} bitfields4b;
uint32_t ordinal4;
};
} PM4CE_SET_BASE, *PPM4CE_SET_BASE;
#endif
//--------------------CE_SWITCH_BUFFER--------------------
#ifndef PM4_CE_SWITCH_BUFFER_DEFINED
#define PM4_CE_SWITCH_BUFFER_DEFINED
typedef struct PM4_CE_SWITCH_BUFFER {
union {
PM4_CE_TYPE_3_HEADER header; /// header
uint32_t ordinal1;
};
union {
struct {
uint32_t tmz : 1;
uint32_t reserved1 : 31;
} bitfields2;
uint32_t ordinal2;
};
} PM4CE_SWITCH_BUFFER, *PPM4CE_SWITCH_BUFFER;
#endif
//--------------------CE_WAIT_ON_DE_COUNTER_DIFF--------------------
#ifndef PM4_CE_WAIT_ON_DE_COUNTER_DIFF_DEFINED
#define PM4_CE_WAIT_ON_DE_COUNTER_DIFF_DEFINED
typedef struct PM4_CE_WAIT_ON_DE_COUNTER_DIFF {
union {
PM4_CE_TYPE_3_HEADER header; /// header
uint32_t ordinal1;
};
uint32_t diff;
} PM4CE_WAIT_ON_DE_COUNTER_DIFF, *PPM4CE_WAIT_ON_DE_COUNTER_DIFF;
#endif
//--------------------CE_WRITE_CONST_RAM--------------------
#ifndef PM4_CE_WRITE_CONST_RAM_DEFINED
#define PM4_CE_WRITE_CONST_RAM_DEFINED
typedef struct PM4_CE_WRITE_CONST_RAM {
union {
PM4_CE_TYPE_3_HEADER header; /// header
uint32_t ordinal1;
};
union {
struct {
uint32_t offset : 16;
uint32_t reserved1 : 16;
} bitfields2;
uint32_t ordinal2;
};
// uint32_t data[]; // N-DWords
} PM4CE_WRITE_CONST_RAM, *PPM4CE_WRITE_CONST_RAM;
#endif
//--------------------CE_WRITE_DATA--------------------
#ifndef PM4_CE_WRITE_DATA_DEFINED
#define PM4_CE_WRITE_DATA_DEFINED
enum CE_WRITE_DATA_dst_sel_enum {
dst_sel__ce_write_data__mem_mapped_register = 0,
dst_sel__ce_write_data__memory = 5,
dst_sel__ce_write_data__preemption_meta_memory = 8
};
enum CE_WRITE_DATA_addr_incr_enum {
addr_incr__ce_write_data__increment_address = 0,
addr_incr__ce_write_data__do_not_increment_address = 1
};
enum CE_WRITE_DATA_wr_confirm_enum {
wr_confirm__ce_write_data__do_not_wait_for_write_confirmation = 0,
wr_confirm__ce_write_data__wait_for_write_confirmation = 1
};
enum CE_WRITE_DATA_cache_policy_enum {
cache_policy__ce_write_data__lru = 0,
cache_policy__ce_write_data__stream = 1
};
enum CE_WRITE_DATA_engine_sel_enum { engine_sel__ce_write_data__constant_engine = 2 };
typedef struct PM4_CE_WRITE_DATA {
union {
PM4_CE_TYPE_3_HEADER header; /// header
uint32_t ordinal1;
};
union {
struct {
uint32_t reserved1 : 8;
CE_WRITE_DATA_dst_sel_enum dst_sel : 4;
uint32_t reserved2 : 4;
CE_WRITE_DATA_addr_incr_enum addr_incr : 1;
uint32_t reserved3 : 2;
uint32_t resume_vf : 1;
CE_WRITE_DATA_wr_confirm_enum wr_confirm : 1;
uint32_t reserved4 : 4;
CE_WRITE_DATA_cache_policy_enum cache_policy : 2;
uint32_t reserved5 : 3;
CE_WRITE_DATA_engine_sel_enum engine_sel : 2;
} bitfields2;
uint32_t ordinal2;
};
union {
struct {
uint32_t dst_mmreg_addr : 18;
uint32_t reserved6 : 14;
} bitfields3a;
struct {
uint32_t reserved7 : 2;
uint32_t dst_mem_addr_lo : 30;
} bitfields3b;
uint32_t ordinal3;
};
uint32_t dst_mem_addr_hi;
// uint32_t data[]; // N-DWords
} PM4CE_WRITE_DATA, *PPM4CE_WRITE_DATA;
#endif
} // gfx9
} // pm4_profile
#endif
projects/rocr-runtime/runtime/hsa-ext-aql-profile/gfxip/gfx9/f32_me_pm4_packets_vg10.h
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projects/rocr-runtime/runtime/hsa-ext-aql-profile/gfxip/gfx9/f32_mec_aql_packets_vg10.h
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//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
//
// f32_aql_mec_packets.h
//
// Trade secret of Advanced Micro Devices, Inc.
// Copyright 2010, Advanced Micro Devices, Inc., (unpublished)
//
// All rights reserved. This notice is intended as a precaution against
// inadvertent publication and does not imply publication or any waiver
// of confidentiality. The year included in the foregoing notice is the
// year of creation of the work.
//
//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
#ifndef F32_MEC_AQL_PACKETS_H
#define F32_MEC_AQL_PACKETS_H
namespace pm4_profile {
namespace gfx9 {
//--------------------MEC_AQL_DISPATCH--------------------
#ifndef AQL_MEC_AQL_DISPATCH_DEFINED
#define AQL_MEC_AQL_DISPATCH_DEFINED
typedef struct AQL_MEC_AQL_DISPATCH {
union {
struct {
uint32_t header : 16;
uint32_t dimensions : 2;
uint32_t reserved1 : 14;
} bitfields1;
uint32_t ordinal1;
};
union {
struct {
uint32_t workgroupsizex : 16;
uint32_t workgroupsizey : 16;
} bitfields2;
uint32_t ordinal2;
};
union {
struct {
uint32_t workgroupsizez : 16;
uint32_t reserved2 : 16;
} bitfields3;
uint32_t ordinal3;
};
uint32_t gridsizex;
uint32_t gridsizey;
uint32_t gridsizez;
uint32_t privatesegmentsizebytes;
uint32_t groupsegmentsizebytes;
uint64_t kernelobjectaddress;
uint64_t kernargaddress;
uint64_t reserved3;
uint64_t completionsignal;
} AQLMEC_AQL_DISPATCH, *PAQLMEC_AQL_DISPATCH;
#endif
//--------------------MEC_AQL_BARRIER--------------------
#ifndef AQL_MEC_AQL_BARRIER_DEFINED
#define AQL_MEC_AQL_BARRIER_DEFINED
typedef struct AQL_MEC_AQL_BARRIER {
union {
struct {
uint32_t header : 16;
uint32_t type : 16;
} bitfields1;
uint32_t ordinal1;
};
union {
struct {
uint32_t polltime : 16;
uint32_t reserved1 : 16;
} bitfields2;
uint32_t ordinal2;
};
uint64_t barrierfield0;
uint64_t barrierfield1;
uint64_t barrierfield2;
uint64_t barrierfield3;
uint64_t barrierfield4;
uint64_t reserved2;
uint64_t completionsignal;
} AQLMEC_AQL_BARRIER, *PAQLMEC_AQL_BARRIER;
#endif
//--------------------MEC_AQL_CALL--------------------
#ifndef AQL_MEC_AQL_CALL_DEFINED
#define AQL_MEC_AQL_CALL_DEFINED
typedef struct AQL_MEC_AQL_CALL {
union {
struct {
uint32_t header : 16;
uint32_t type : 16;
} bitfields1;
uint32_t ordinal1;
};
uint32_t reserved1;
uint64_t returnlocation;
uint64_t compareaddress;
uint64_t comparemask;
uint64_t compareref;
uint64_t ibbase;
uint64_t ibsize;
uint64_t reserved2;
uint64_t completionsignal;
} AQLMEC_AQL_CALL, *PAQLMEC_AQL_CALL;
#endif
//--------------------MEC_AQL_DMA--------------------
#ifndef AQL_MEC_AQL_DMA_DEFINED
#define AQL_MEC_AQL_DMA_DEFINED
typedef struct AQL_MEC_AQL_DMA {
union {
struct {
uint32_t header : 16;
uint32_t type : 16;
} bitfields1;
uint32_t ordinal1;
};
uint32_t reserved1;
uint64_t returnlocation;
uint32_t stateobjaddress;
uint64_t sourceaddress;
uint64_t destaddress;
uint64_t size;
uint64_t reserved2;
uint64_t completionsignal;
} AQLMEC_AQL_DMA, *PAQLMEC_AQL_DMA;
#endif
//--------------------MEC_AQL_DRAW--------------------
#ifndef AQL_MEC_AQL_DRAW_DEFINED
#define AQL_MEC_AQL_DRAW_DEFINED
typedef struct AQL_MEC_AQL_DRAW {
union {
struct {
uint32_t header : 16;
uint32_t type : 16;
} bitfields1;
uint32_t ordinal1;
};
uint32_t maxsize;
uint32_t indexbase;
uint32_t indexcount;
union {
struct {
uint32_t indextype : 16;
uint32_t primtype : 16;
} bitfields5;
uint32_t ordinal5;
};
uint32_t numinstances;
uint32_t privatesegmentsizebytes;
uint32_t groupsegmentsizebytes;
uint32_t kernelobjectaddress;
uint32_t kernargaddress;
uint32_t reserved1;
uint32_t reserved2;
uint32_t completionsignal;
} AQLMEC_AQL_DRAW, *PAQLMEC_AQL_DRAW;
#endif
//--------------------MEC_AQL_JUMP--------------------
#ifndef AQL_MEC_AQL_JUMP_DEFINED
#define AQL_MEC_AQL_JUMP_DEFINED
enum MEC_AQL_JUMP_type_enum { type__mec_aql_jump__cond_jump_to_queue_index = 0 };
typedef struct AQL_MEC_AQL_JUMP {
union {
struct {
uint32_t header : 16;
MEC_AQL_JUMP_type_enum type : 16;
} bitfields1;
uint32_t ordinal1;
};
uint32_t reserved1;
uint64_t returnlocation;
uint64_t compareaddress;
uint64_t comparemask;
uint64_t compareref;
uint64_t ibbase;
uint64_t ibsize;
uint64_t reserved2;
uint64_t completionsignal;
} AQLMEC_AQL_JUMP, *PAQLMEC_AQL_JUMP;
#endif
} // gfx9
} // pm4_profile
#endif
projects/rocr-runtime/runtime/hsa-ext-aql-profile/gfxip/gfx9/f32_mec_cmn_structs_vg10.h
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//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
//
// f32_mec_cmn_structs.h
//
// Trade secret of Advanced Micro Devices, Inc.
// Copyright 2010, Advanced Micro Devices, Inc., (unpublished)
//
// All rights reserved. This notice is intended as a precaution against
// inadvertent publication and does not imply publication or any waiver
// of confidentiality. The year included in the foregoing notice is the
// year of creation of the work.
//
//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
#ifndef F32_MEC_CMN_STRUCTS_H
#define F32_MEC_CMN_STRUCTS_H
namespace pm4_profile {
namespace gfx9 {
//--------------------MEC_SDMA_128DW_MQD--------------------
#ifndef STR_MEC_SDMA_128DW_MQD_DEFINED
#define STR_MEC_SDMA_128DW_MQD_DEFINED
typedef struct STR_MEC_SDMA_128DW_MQD {
uint32_t sdmax_rlcx_rb_cntl; // offset: 0 (0x0)
uint32_t sdmax_rlcx_rb_base; // offset: 1 (0x1)
uint32_t sdmax_rlcx_rb_base_hi; // offset: 2 (0x2)
uint32_t sdmax_rlcx_rb_rptr; // offset: 3 (0x3)
uint32_t sdmax_rlcx_rb_wptr; // offset: 4 (0x4)
uint32_t sdmax_rlcx_rb_wptr_poll_cntl; // offset: 5 (0x5)
uint32_t sdmax_rlcx_rb_wptr_poll_addr_hi; // offset: 6 (0x6)
uint32_t sdmax_rlcx_rb_wptr_poll_addr_lo; // offset: 7 (0x7)
uint32_t sdmax_rlcx_rb_rptr_addr_hi; // offset: 8 (0x8)
uint32_t sdmax_rlcx_rb_rptr_addr_lo; // offset: 9 (0x9)
uint32_t sdmax_rlcx_ib_cntl; // offset: 10 (0xa)
uint32_t sdmax_rlcx_ib_rptr; // offset: 11 (0xb)
uint32_t sdmax_rlcx_ib_offset; // offset: 12 (0xc)
uint32_t sdmax_rlcx_ib_base_lo; // offset: 13 (0xd)
uint32_t sdmax_rlcx_ib_base_hi; // offset: 14 (0xe)
uint32_t sdmax_rlcx_ib_size; // offset: 15 (0xf)
uint32_t sdmax_rlcx_skip_cntl; // offset: 16 (0x10)
uint32_t sdmax_rlcx_context_status; // offset: 17 (0x11)
uint32_t sdmax_rlcx_doorbell; // offset: 18 (0x12)
uint32_t sdmax_rlcx_virtual_addr; // offset: 19 (0x13)
uint32_t sdmax_rlcx_ape1_cntl; // offset: 20 (0x14)
uint32_t sdmax_rlcx_doorbell_log; // offset: 21 (0x15)
uint32_t reserved_22; // offset: 22 (0x16)
uint32_t reserved_23; // offset: 23 (0x17)
uint32_t reserved_24; // offset: 24 (0x18)
uint32_t reserved_25; // offset: 25 (0x19)
uint32_t reserved_26; // offset: 26 (0x1A)
uint32_t reserved_27; // offset: 27 (0x1B)
uint32_t reserved_28; // offset: 28 (0x1C)
uint32_t reserved_29; // offset: 29 (0x1D)
uint32_t reserved_30; // offset: 30 (0x1E)
uint32_t reserved_31; // offset: 31 (0x1F)
uint32_t reserved_32; // offset: 32 (0x20)
uint32_t reserved_33; // offset: 33 (0x21)
uint32_t reserved_34; // offset: 34 (0x22)
uint32_t reserved_35; // offset: 35 (0x23)
uint32_t reserved_36; // offset: 36 (0x24)
uint32_t reserved_37; // offset: 37 (0x25)
uint32_t reserved_38; // offset: 38 (0x26)
uint32_t reserved_39; // offset: 39 (0x27)
uint32_t reserved_40; // offset: 40 (0x28)
uint32_t reserved_41; // offset: 41 (0x29)
uint32_t reserved_42; // offset: 42 (0x2A)
uint32_t reserved_43; // offset: 43 (0x2B)
uint32_t reserved_44; // offset: 44 (0x2C)
uint32_t reserved_45; // offset: 45 (0x2D)
uint32_t reserved_46; // offset: 46 (0x2E)
uint32_t reserved_47; // offset: 47 (0x2F)
uint32_t reserved_48; // offset: 48 (0x30)
uint32_t reserved_49; // offset: 49 (0x31)
uint32_t reserved_50; // offset: 50 (0x32)
uint32_t reserved_51; // offset: 51 (0x33)
uint32_t reserved_52; // offset: 52 (0x34)
uint32_t reserved_53; // offset: 53 (0x35)
uint32_t reserved_54; // offset: 54 (0x36)
uint32_t reserved_55; // offset: 55 (0x37)
uint32_t reserved_56; // offset: 56 (0x38)
uint32_t reserved_57; // offset: 57 (0x39)
uint32_t reserved_58; // offset: 58 (0x3A)
uint32_t reserved_59; // offset: 59 (0x3B)
uint32_t reserved_60; // offset: 60 (0x3C)
uint32_t reserved_61; // offset: 61 (0x3D)
uint32_t reserved_62; // offset: 62 (0x3E)
uint32_t reserved_63; // offset: 63 (0x3F)
uint32_t reserved_64; // offset: 64 (0x40)
uint32_t reserved_65; // offset: 65 (0x41)
uint32_t reserved_66; // offset: 66 (0x42)
uint32_t reserved_67; // offset: 67 (0x43)
uint32_t reserved_68; // offset: 68 (0x44)
uint32_t reserved_69; // offset: 69 (0x45)
uint32_t reserved_70; // offset: 70 (0x46)
uint32_t reserved_71; // offset: 0 (0x47)
uint32_t reserved_72; // offset: 1 (0x48)
uint32_t reserved_73; // offset: 2 (0x49)
uint32_t reserved_74; // offset: 3 (0x4A)
uint32_t reserved_75; // offset: 4 (0x4B)
uint32_t reserved_76; // offset: 5 (0x4C)
uint32_t reserved_77; // offset: 6 (0x4D)
uint32_t reserved_78; // offset: 7 (0x4E)
uint32_t reserved_79; // offset: 79 (0x4F)
uint32_t reserved_80; // offset: 80 (0x50)
uint32_t reserved_81; // offset: 81 (0x51)
uint32_t reserved_82; // offset: 82 (0x52)
uint32_t reserved_83; // offset: 83 (0x53)
uint32_t reserved_84; // offset: 84 (0x54)
uint32_t reserved_85; // offset: 85 (0x55)
uint32_t reserved_86; // offset: 86 (0x56)
uint32_t reserved_87; // offset: 87 (0x57)
uint32_t reserved_88; // offset: 88 (0x58)
uint32_t reserved_89; // offset: 89 (0x59)
uint32_t reserved_90; // offset: 90 (0x5A)
uint32_t reserved_91; // offset: 91 (0x5B)
uint32_t reserved_92; // offset: 92 (0x5C)
uint32_t reserved_93; // offset: 93 (0x5D)
uint32_t reserved_94; // offset: 94 (0x5E)
uint32_t reserved_95; // offset: 95 (0x5F)
uint32_t reserved_96; // offset: 96 (0x60)
uint32_t reserved_97; // offset: 97 (0x61)
uint32_t reserved_98; // offset: 98 (0x62)
uint32_t reserved_99; // offset: 99 (0x63)
uint32_t reserved_100; // offset: 100 (0x64)
uint32_t reserved_101; // offset: 101 (0x65)
uint32_t reserved_102; // offset: 102 (0x66)
uint32_t reserved_103; // offset: 103 (0x67)
uint32_t reserved_104; // offset: 104 (0x68)
uint32_t reserved_105; // offset: 105 (0x69)
uint32_t reserved_106; // offset: 106 (0x6A)
uint32_t reserved_107; // offset: 107 (0x6B)
uint32_t reserved_108; // offset: 108 (0x6C)
uint32_t reserved_109; // offset: 109 (0x6D)
uint32_t reserved_110; // offset: 110 (0x6E)
uint32_t reserved_111; // offset: 111 (0x6F)
uint32_t reserved_112; // offset: 112 (0x70)
uint32_t reserved_113; // offset: 113 (0x71)
uint32_t reserved_114; // offset: 114 (0x72)
uint32_t reserved_115; // offset: 115 (0x73)
uint32_t reserved_116; // offset: 116 (0x74)
uint32_t reserved_117; // offset: 117 (0x75)
uint32_t reserved_118; // offset: 118 (0x76)
uint32_t reserved_119; // offset: 119 (0x77)
uint32_t reserved_120; // offset: 120 (0x78)
uint32_t reserved_121; // offset: 121 (0x79)
uint32_t reserved_122; // offset: 122 (0x7A)
uint32_t reserved_123; // offset: 123 (0x7B)
uint32_t reserved_124; // offset: 124 (0x7C)
uint32_t reserved_125; // offset: 125 (0x7D)
uint32_t reserved_126; // offset: 126 (0x7E)
uint32_t reserved_127; // offset: 127 (0x7F)
} STRMEC_SDMA_128DW_MQD, *PSTRMEC_SDMA_128DW_MQD;
#endif
//--------------------MEC_Compute_512DW_MQD--------------------
#ifndef STR_MEC_COMPUTE_512DW_MQD_DEFINED
#define STR_MEC_COMPUTE_512DW_MQD_DEFINED
typedef struct STR_MEC_COMPUTE_512DW_MQD {
uint32_t header; // offset: 0 (0x0)
uint32_t compute_dispatch_initiator; // offset: 1 (0x1)
uint32_t compute_dim_x; // offset: 2 (0x2)
uint32_t compute_dim_y; // offset: 3 (0x3)
uint32_t compute_dim_z; // offset: 4 (0x4)
uint32_t compute_start_x; // offset: 5 (0x5)
uint32_t compute_start_y; // offset: 6 (0x6)
uint32_t compute_start_z; // offset: 7 (0x7)
uint32_t compute_num_thread_x; // offset: 8 (0x8)
uint32_t compute_num_thread_y; // offset: 9 (0x9)
uint32_t compute_num_thread_z; // offset: 10 (0xA)
uint32_t compute_pipelinestat_enable; // offset: 11 (0xB)
uint32_t compute_perfcount_enable; // offset: 12 (0xC)
uint32_t compute_pgm_lo; // offset: 13 (0xD)
uint32_t compute_pgm_hi; // offset: 14 (0xE)
uint32_t compute_tba_lo; // offset: 15 (0xF)
uint32_t compute_tba_hi; // offset: 16 (0x10)
uint32_t compute_tma_lo; // offset: 17 (0x11)
uint32_t compute_tma_hi; // offset: 18 (0x12)
uint32_t compute_pgm_rsrc1; // offset: 19 (0x13)
uint32_t compute_pgm_rsrc2; // offset: 20 (0x14)
uint32_t compute_vmid; // offset: 21 (0x15)
uint32_t compute_resource_limits; // offset: 22 (0x16)
uint32_t compute_static_thread_mgmt_se0; // offset: 23 (0x17)
uint32_t compute_static_thread_mgmt_se1; // offset: 24 (0x18)
uint32_t compute_tmpring_size; // offset: 25 (0x19)
uint32_t compute_static_thread_mgmt_se2; // offset: 26 (0x1A)
uint32_t compute_static_thread_mgmt_se3; // offset: 27 (0x1B)
uint32_t compute_restart_x; // offset: 28 (0x1C)
uint32_t compute_restart_y; // offset: 29 (0x1D)
uint32_t compute_restart_z; // offset: 30 (0x1E)
uint32_t compute_thread_trace_enable; // offset: 31 (0x1F)
uint32_t compute_misc_reserved; // offset: 32 (0x20)
uint32_t compute_dispatch_id; // offset: 33 (0x21)
uint32_t compute_threadgroup_id; // offset: 34 (0x22)
uint32_t compute_relaunch; // offset: 35 (0x23)
uint32_t compute_wave_restore_addr_lo; // offset: 36 (0x24)
uint32_t compute_wave_restore_addr_hi; // offset: 37 (0x25)
uint32_t compute_wave_restore_control; // offset: 38 (0x26)
uint32_t reserved_39; // offset: 39 (0x27)
uint32_t reserved_40; // offset: 40 (0x28)
uint32_t reserved_41; // offset: 41 (0x29)
uint32_t reserved_42; // offset: 42 (0x2A)
uint32_t reserved_43; // offset: 43 (0x2B)
uint32_t reserved_44; // offset: 44 (0x2C)
uint32_t reserved_45; // offset: 45 (0x2D)
uint32_t reserved_46; // offset: 46 (0x2E)
uint32_t reserved_47; // offset: 47 (0x2F)
uint32_t reserved_48; // offset: 48 (0x30)
uint32_t reserved_49; // offset: 49 (0x31)
uint32_t reserved_50; // offset: 50 (0x32)
uint32_t reserved_51; // offset: 51 (0x33)
uint32_t reserved_52; // offset: 52 (0x34)
uint32_t reserved_53; // offset: 53 (0x35)
uint32_t reserved_54; // offset: 54 (0x36)
uint32_t reserved_55; // offset: 55 (0x37)
uint32_t reserved_56; // offset: 56 (0x38)
uint32_t reserved_57; // offset: 57 (0x39)
uint32_t reserved_58; // offset: 58 (0x3A)
uint32_t reserved_59; // offset: 59 (0x3B)
uint32_t reserved_60; // offset: 60 (0x3C)
uint32_t reserved_61; // offset: 61 (0x3D)
uint32_t reserved_62; // offset: 62 (0x3E)
uint32_t reserved_63; // offset: 63 (0x3F)
uint32_t reserved_64; // offset: 64 (0x40)
uint32_t compute_user_data_0; // offset: 65 (0x41)
uint32_t compute_user_data_1; // offset: 66 (0x42)
uint32_t compute_user_data_2; // offset: 67 (0x43)
uint32_t compute_user_data_3; // offset: 68 (0x44)
uint32_t compute_user_data_4; // offset: 69 (0x45)
uint32_t compute_user_data_5; // offset: 70 (0x46)
uint32_t compute_user_data_6; // offset: 71 (0x47)
uint32_t compute_user_data_7; // offset: 72 (0x48)
uint32_t compute_user_data_8; // offset: 73 (0x49)
uint32_t compute_user_data_9; // offset: 74 (0x4A)
uint32_t compute_user_data_10; // offset: 75 (0x4B)
uint32_t compute_user_data_11; // offset: 76 (0x4C)
uint32_t compute_user_data_12; // offset: 77 (0x4D)
uint32_t compute_user_data_13; // offset: 78 (0x4E)
uint32_t compute_user_data_14; // offset: 79 (0x4F)
uint32_t compute_user_data_15; // offset: 80 (0x50)
uint32_t cp_compute_csinvoc_count_lo; // offset: 81 (0x51)
uint32_t cp_compute_csinvoc_count_hi; // offset: 82 (0x52)
uint32_t reserved_83; // offset: 83 (0x53)
uint32_t reserved_84; // offset: 84 (0x54)
uint32_t reserved_85; // offset: 85 (0x55)
uint32_t cp_mqd_query_time_lo; // offset: 86 (0x56)
uint32_t cp_mqd_query_time_hi; // offset: 87 (0x57)
uint32_t cp_mqd_connect_start_time_lo; // offset: 88 (0x58)
uint32_t cp_mqd_connect_start_time_hi; // offset: 89 (0x59)
uint32_t cp_mqd_connect_end_time_lo; // offset: 90 (0x5A)
uint32_t cp_mqd_connect_end_time_hi; // offset: 91 (0x5B)
uint32_t cp_mqd_connect_end_wf_count; // offset: 92 (0x5C)
uint32_t cp_mqd_connect_end_pq_rptr; // offset: 93 (0x5D)
uint32_t cp_mqd_connect_end_pq_wptr; // offset: 94 (0x5E)
uint32_t cp_mqd_connect_end_ib_rptr; // offset: 95 (0x5F)
uint32_t cp_mqd_readindex_lo; // offset: 96 (0x60)
uint32_t cp_mqd_readindex_hi; // offset: 97 (0x61)
uint32_t cp_mqd_save_start_time_lo; // offset: 98 (0x62)
uint32_t cp_mqd_save_start_time_hi; // offset: 99 (0x63)
uint32_t cp_mqd_save_end_time_lo; // offset: 100 (0x64)
uint32_t cp_mqd_save_end_time_hi; // offset: 101 (0x65)
uint32_t cp_mqd_restore_start_time_lo; // offset: 102 (0x66)
uint32_t cp_mqd_restore_start_time_hi; // offset: 103 (0x67)
uint32_t cp_mqd_restore_end_time_lo; // offset: 104 (0x68)
uint32_t cp_mqd_restore_end_time_hi; // offset: 105 (0x69)
uint32_t disable_queue; // offset: 106 (0x6A)
uint32_t reserved_107; // offset: 107 (0x6B)
uint32_t gds_cs_ctxsw_cnt0; // offset: 108 (0x6C)
uint32_t gds_cs_ctxsw_cnt1; // offset: 109 (0x6D)
uint32_t gds_cs_ctxsw_cnt2; // offset: 110 (0x6E)
uint32_t gds_cs_ctxsw_cnt3; // offset: 111 (0x6F)
uint32_t reserved_112; // offset: 112 (0x70)
uint32_t reserved_113; // offset: 113 (0x71)
uint32_t cp_pq_exe_status_lo; // offset: 114 (0x72)
uint32_t cp_pq_exe_status_hi; // offset: 115 (0x73)
uint32_t cp_packet_id_lo; // offset: 116 (0x74)
uint32_t cp_packet_id_hi; // offset: 117 (0x75)
uint32_t cp_packet_exe_status_lo; // offset: 118 (0x76)
uint32_t cp_packet_exe_status_hi; // offset: 119 (0x77)
uint32_t gds_save_base_addr_lo; // offset: 120 (0x78)
uint32_t gds_save_base_addr_hi; // offset: 121 (0x79)
uint32_t gds_save_mask_lo; // offset: 122 (0x7A)
uint32_t gds_save_mask_hi; // offset: 123 (0x7B)
uint32_t ctx_save_base_addr_lo; // offset: 124 (0x7C)
uint32_t ctx_save_base_addr_hi; // offset: 125 (0x7D)
uint32_t reserved_126; // offset: 126 (0x7E)
uint32_t reserved_127; // offset: 127 (0x7F)
uint32_t cp_mqd_base_addr_lo; // offset: 128 (0x80)
uint32_t cp_mqd_base_addr_hi; // offset: 129 (0x81)
uint32_t cp_hqd_active; // offset: 130 (0x82)
uint32_t cp_hqd_vmid; // offset: 131 (0x83)
uint32_t cp_hqd_persistent_state; // offset: 132 (0x84)
uint32_t cp_hqd_pipe_priority; // offset: 133 (0x85)
uint32_t cp_hqd_queue_priority; // offset: 134 (0x86)
uint32_t cp_hqd_quantum; // offset: 135 (0x87)
uint32_t cp_hqd_pq_base_lo; // offset: 136 (0x88)
uint32_t cp_hqd_pq_base_hi; // offset: 137 (0x89)
uint32_t cp_hqd_pq_rptr; // offset: 138 (0x8A)
uint32_t cp_hqd_pq_rptr_report_addr_lo; // offset: 139 (0x8B)
uint32_t cp_hqd_pq_rptr_report_addr_hi; // offset: 140 (0x8C)
uint32_t cp_hqd_pq_wptr_poll_addr_lo; // offset: 141 (0x8D)
uint32_t cp_hqd_pq_wptr_poll_addr_hi; // offset: 142 (0x8E)
uint32_t cp_hqd_pq_doorbell_control; // offset: 143 (0x8F)
uint32_t reserved_144; // offset: 144 (0x90)
uint32_t cp_hqd_pq_control; // offset: 145 (0x91)
uint32_t cp_hqd_ib_base_addr_lo; // offset: 146 (0x92)
uint32_t cp_hqd_ib_base_addr_hi; // offset: 147 (0x93)
uint32_t cp_hqd_ib_rptr; // offset: 148 (0x94)
uint32_t cp_hqd_ib_control; // offset: 149 (0x95)
uint32_t cp_hqd_iq_timer; // offset: 150 (0x96)
uint32_t cp_hqd_iq_rptr; // offset: 151 (0x97)
uint32_t cp_hqd_dequeue_request; // offset: 152 (0x98)
uint32_t cp_hqd_dma_offload; // offset: 153 (0x99)
uint32_t cp_hqd_sema_cmd; // offset: 154 (0x9A)
uint32_t cp_hqd_msg_type; // offset: 155 (0x9B)
uint32_t cp_hqd_atomic0_preop_lo; // offset: 156 (0x9C)
uint32_t cp_hqd_atomic0_preop_hi; // offset: 157 (0x9D)
uint32_t cp_hqd_atomic1_preop_lo; // offset: 158 (0x9E)
uint32_t cp_hqd_atomic1_preop_hi; // offset: 159 (0x9F)
uint32_t cp_hqd_hq_status0; // offset: 160 (0xA0)
uint32_t cp_hqd_hq_control0; // offset: 161 (0xA1)
uint32_t cp_mqd_control; // offset: 162 (0xA2)
uint32_t cp_hqd_hq_status1; // offset: 163 (0xA3)
uint32_t cp_hqd_hq_control1; // offset: 164 (0xA4)
uint32_t cp_hqd_eop_base_addr_lo; // offset: 165 (0xA5)
uint32_t cp_hqd_eop_base_addr_hi; // offset: 166 (0xA6)
uint32_t cp_hqd_eop_control; // offset: 167 (0xA7)
uint32_t cp_hqd_eop_rptr; // offset: 168 (0xA8)
uint32_t cp_hqd_eop_wptr; // offset: 169 (0xA9)
uint32_t cp_hqd_eop_done_events; // offset: 170 (0xAA)
uint32_t cp_hqd_ctx_save_base_addr_lo; // offset: 171 (0xAB)
uint32_t cp_hqd_ctx_save_base_addr_hi; // offset: 172 (0xAC)
uint32_t cp_hqd_ctx_save_control; // offset: 173 (0xAD)
uint32_t cp_hqd_cntl_stack_offset; // offset: 174 (0xAE)
uint32_t cp_hqd_cntl_stack_size; // offset: 175 (0xAF)
uint32_t cp_hqd_wg_state_offset; // offset: 176 (0xB0)
uint32_t cp_hqd_ctx_save_size; // offset: 177 (0xB1)
uint32_t cp_hqd_gds_resource_state; // offset: 178 (0xB2)
uint32_t cp_hqd_error; // offset: 179 (0xB3)
uint32_t cp_hqd_eop_wptr_mem; // offset: 180 (0xB4)
uint32_t cp_hqd_aql_control; // offset: 181 (0xB5)
uint32_t cp_hqd_pq_wptr_lo; // offset: 182 (0xB6)
uint32_t cp_hqd_pq_wptr_hi; // offset: 183 (0xB7)
uint32_t reserved_184; // offset: 184 (0xB8)
uint32_t reserved_185; // offset: 185 (0xB9)
uint32_t reserved_186; // offset: 186 (0xBA)
uint32_t reserved_187; // offset: 187 (0xBB)
uint32_t reserved_188; // offset: 188 (0xBC)
uint32_t reserved_189; // offset: 189 (0xBD)
uint32_t reserved_190; // offset: 190 (0xBE)
uint32_t reserved_191; // offset: 191 (0xBF)
uint32_t iqtimer_pkt_header; // offset: 192 (0xC0)
uint32_t iqtimer_pkt_dw0; // offset: 193 (0xC1)
uint32_t iqtimer_pkt_dw1; // offset: 194 (0xC2)
uint32_t iqtimer_pkt_dw2; // offset: 195 (0xC3)
uint32_t iqtimer_pkt_dw3; // offset: 196 (0xC4)
uint32_t iqtimer_pkt_dw4; // offset: 197 (0xC5)
uint32_t iqtimer_pkt_dw5; // offset: 198 (0xC6)
uint32_t iqtimer_pkt_dw6; // offset: 199 (0xC7)
uint32_t iqtimer_pkt_dw7; // offset: 200 (0xC8)
uint32_t iqtimer_pkt_dw8; // offset: 201 (0xC9)
uint32_t iqtimer_pkt_dw9; // offset: 202 (0xCA)
uint32_t iqtimer_pkt_dw10; // offset: 203 (0xCB)
uint32_t iqtimer_pkt_dw11; // offset: 204 (0xCC)
uint32_t iqtimer_pkt_dw12; // offset: 205 (0xCD)
uint32_t iqtimer_pkt_dw13; // offset: 206 (0xCE)
uint32_t iqtimer_pkt_dw14; // offset: 207 (0xCF)
uint32_t iqtimer_pkt_dw15; // offset: 208 (0xD0)
uint32_t iqtimer_pkt_dw16; // offset: 209 (0xD1)
uint32_t iqtimer_pkt_dw17; // offset: 210 (0xD2)
uint32_t iqtimer_pkt_dw18; // offset: 211 (0xD3)
uint32_t iqtimer_pkt_dw19; // offset: 212 (0xD4)
uint32_t iqtimer_pkt_dw20; // offset: 213 (0xD5)
uint32_t iqtimer_pkt_dw21; // offset: 214 (0xD6)
uint32_t iqtimer_pkt_dw22; // offset: 215 (0xD7)
uint32_t iqtimer_pkt_dw23; // offset: 216 (0xD8)
uint32_t iqtimer_pkt_dw24; // offset: 217 (0xD9)
uint32_t iqtimer_pkt_dw25; // offset: 218 (0xDA)
uint32_t iqtimer_pkt_dw26; // offset: 219 (0xDB)
uint32_t iqtimer_pkt_dw27; // offset: 220 (0xDC)
uint32_t iqtimer_pkt_dw28; // offset: 221 (0xDD)
uint32_t iqtimer_pkt_dw29; // offset: 222 (0xDE)
uint32_t iqtimer_pkt_dw30; // offset: 223 (0xDF)
uint32_t iqtimer_pkt_dw31; // offset: 224 (0xE0)
uint32_t reserved_225; // offset: 225 (0xE1)
uint32_t reserved_226; // offset: 226 (0xE2)
uint32_t reserved_227; // offset: 227 (0xE3)
uint32_t set_resources_header; // offset: 228 (0xE4)
uint32_t set_resources_dw1; // offset: 229 (0xE5)
uint32_t set_resources_dw2; // offset: 230 (0xE6)
uint32_t set_resources_dw3; // offset: 231 (0xE7)
uint32_t set_resources_dw4; // offset: 232 (0xE8)
uint32_t set_resources_dw5; // offset: 233 (0xE9)
uint32_t set_resources_dw6; // offset: 234 (0xEA)
uint32_t set_resources_dw7; // offset: 235 (0xEB)
uint32_t reserved_236; // offset: 236 (0xEC)
uint32_t reserved_237; // offset: 237 (0xED)
uint32_t reserved_238; // offset: 238 (0xEE)
uint32_t reserved_239; // offset: 239 (0xEF)
uint32_t queue_doorbell_id0; // offset: 240 (0xF0)
uint32_t queue_doorbell_id1; // offset: 241 (0xF1)
uint32_t queue_doorbell_id2; // offset: 242 (0xF2)
uint32_t queue_doorbell_id3; // offset: 243 (0xF3)
uint32_t queue_doorbell_id4; // offset: 244 (0xF4)
uint32_t queue_doorbell_id5; // offset: 245 (0xF5)
uint32_t queue_doorbell_id6; // offset: 246 (0xF6)
uint32_t queue_doorbell_id7; // offset: 247 (0xF7)
uint32_t queue_doorbell_id8; // offset: 248 (0xF8)
uint32_t queue_doorbell_id9; // offset: 249 (0xF9)
uint32_t queue_doorbell_id10; // offset: 250 (0xFA)
uint32_t queue_doorbell_id11; // offset: 251 (0xFB)
uint32_t queue_doorbell_id12; // offset: 252 (0xFC)
uint32_t queue_doorbell_id13; // offset: 253 (0xFD)
uint32_t queue_doorbell_id14; // offset: 254 (0xFE)
uint32_t queue_doorbell_id15; // offset: 255 (0xFF)
uint32_t Reserved_256; // offset: 256 (0x100)
uint32_t Reserved_257; // offset: 257 (0x101)
uint32_t Reserved_258; // offset: 258 (0x102)
uint32_t Reserved_259; // offset: 259 (0x103)
uint32_t Reserved_260; // offset: 260 (0x104)
uint32_t Reserved_261; // offset: 261 (0x105)
uint32_t Reserved_262; // offset: 262 (0x106)
uint32_t Reserved_263; // offset: 263 (0x107)
uint32_t Reserved_264; // offset: 264 (0x108)
uint32_t Reserved_265; // offset: 265 (0x109)
uint32_t Reserved_266; // offset: 266 (0x10A)
uint32_t Reserved_267; // offset: 267 (0x10B)
uint32_t Reserved_268; // offset: 268 (0x10C)
uint32_t Reserved_269; // offset: 269 (0x10D)
uint32_t Reserved_270; // offset: 270 (0x10E)
uint32_t Reserved_271; // offset: 271 (0x10F)
uint32_t Reserved_272; // offset: 272 (0x110)
uint32_t Reserved_273; // offset: 273 (0x111)
uint32_t Reserved_274; // offset: 274 (0x112)
uint32_t Reserved_275; // offset: 275 (0x113)
uint32_t Reserved_276; // offset: 276 (0x114)
uint32_t Reserved_277; // offset: 277 (0x115)
uint32_t Reserved_278; // offset: 278 (0x116)
uint32_t Reserved_279; // offset: 279 (0x117)
uint32_t Reserved_280; // offset: 280 (0x118)
uint32_t Reserved_281; // offset: 281 (0x119)
uint32_t Reserved_282; // offset: 282 (0x11A)
uint32_t Reserved_283; // offset: 283 (0x11B)
uint32_t Reserved_284; // offset: 284 (0x11C)
uint32_t Reserved_285; // offset: 285 (0x11D)
uint32_t Reserved_286; // offset: 286 (0x11E)
uint32_t Reserved_287; // offset: 287 (0x11F)
uint32_t Reserved_288; // offset: 288 (0x120)
uint32_t Reserved_289; // offset: 289 (0x121)
uint32_t Reserved_290; // offset: 290 (0x122)
uint32_t Reserved_291; // offset: 291 (0x123)
uint32_t Reserved_292; // offset: 292 (0x124)
uint32_t Reserved_293; // offset: 293 (0x125)
uint32_t Reserved_294; // offset: 294 (0x126)
uint32_t Reserved_295; // offset: 295 (0x127)
uint32_t Reserved_296; // offset: 296 (0x128)
uint32_t Reserved_297; // offset: 297 (0x129)
uint32_t Reserved_298; // offset: 298 (0x12A)
uint32_t Reserved_299; // offset: 299 (0x12B)
uint32_t Reserved_300; // offset: 300 (0x12C)
uint32_t Reserved_301; // offset: 301 (0x12D)
uint32_t Reserved_302; // offset: 302 (0x12E)
uint32_t Reserved_303; // offset: 303 (0x12F)
uint32_t Reserved_304; // offset: 304 (0x130)
uint32_t Reserved_305; // offset: 305 (0x131)
uint32_t Reserved_306; // offset: 306 (0x132)
uint32_t Reserved_307; // offset: 307 (0x133)
uint32_t Reserved_308; // offset: 308 (0x134)
uint32_t Reserved_309; // offset: 309 (0x135)
uint32_t Reserved_310; // offset: 310 (0x136)
uint32_t Reserved_311; // offset: 311 (0x137)
uint32_t Reserved_312; // offset: 312 (0x138)
uint32_t Reserved_313; // offset: 313 (0x139)
uint32_t Reserved_314; // offset: 314 (0x13A)
uint32_t Reserved_315; // offset: 315 (0x13B)
uint32_t Reserved_316; // offset: 316 (0x13C)
uint32_t Reserved_317; // offset: 317 (0x13D)
uint32_t Reserved_318; // offset: 318 (0x13E)
uint32_t Reserved_319; // offset: 319 (0x13F)
uint32_t Reserved_320; // offset: 320 (0x140)
uint32_t Reserved_321; // offset: 321 (0x141)
uint32_t Reserved_322; // offset: 322 (0x142)
uint32_t Reserved_323; // offset: 323 (0x143)
uint32_t Reserved_324; // offset: 324 (0x144)
uint32_t Reserved_325; // offset: 325 (0x145)
uint32_t Reserved_326; // offset: 326 (0x146)
uint32_t Reserved_327; // offset: 327 (0x147)
uint32_t Reserved_328; // offset: 328 (0x148)
uint32_t Reserved_329; // offset: 329 (0x149)
uint32_t Reserved_330; // offset: 330 (0x14A)
uint32_t Reserved_331; // offset: 331 (0x14B)
uint32_t Reserved_332; // offset: 332 (0x14C)
uint32_t Reserved_333; // offset: 333 (0x14D)
uint32_t Reserved_334; // offset: 334 (0x14E)
uint32_t Reserved_335; // offset: 335 (0x14F)
uint32_t Reserved_336; // offset: 336 (0x150)
uint32_t Reserved_337; // offset: 337 (0x151)
uint32_t Reserved_338; // offset: 338 (0x152)
uint32_t Reserved_339; // offset: 339 (0x153)
uint32_t Reserved_340; // offset: 340 (0x154)
uint32_t Reserved_341; // offset: 341 (0x155)
uint32_t Reserved_342; // offset: 342 (0x156)
uint32_t Reserved_343; // offset: 343 (0x157)
uint32_t Reserved_344; // offset: 344 (0x158)
uint32_t Reserved_345; // offset: 345 (0x159)
uint32_t Reserved_346; // offset: 346 (0x15A)
uint32_t Reserved_347; // offset: 347 (0x15B)
uint32_t Reserved_348; // offset: 348 (0x15C)
uint32_t Reserved_349; // offset: 349 (0x15D)
uint32_t Reserved_350; // offset: 350 (0x15E)
uint32_t Reserved_351; // offset: 351 (0x15F)
uint32_t Reserved_352; // offset: 352 (0x160)
uint32_t Reserved_353; // offset: 353 (0x161)
uint32_t Reserved_354; // offset: 354 (0x162)
uint32_t Reserved_355; // offset: 355 (0x163)
uint32_t Reserved_356; // offset: 356 (0x164)
uint32_t Reserved_357; // offset: 357 (0x165)
uint32_t Reserved_358; // offset: 358 (0x166)
uint32_t Reserved_359; // offset: 359 (0x167)
uint32_t Reserved_360; // offset: 360 (0x168)
uint32_t Reserved_361; // offset: 361 (0x169)
uint32_t Reserved_362; // offset: 362 (0x16A)
uint32_t Reserved_363; // offset: 363 (0x16B)
uint32_t Reserved_364; // offset: 364 (0x16C)
uint32_t Reserved_365; // offset: 365 (0x16D)
uint32_t Reserved_366; // offset: 366 (0x16E)
uint32_t Reserved_367; // offset: 367 (0x16F)
uint32_t Reserved_368; // offset: 368 (0x170)
uint32_t Reserved_369; // offset: 369 (0x171)
uint32_t Reserved_370; // offset: 370 (0x172)
uint32_t Reserved_371; // offset: 371 (0x173)
uint32_t Reserved_372; // offset: 372 (0x174)
uint32_t Reserved_373; // offset: 373 (0x175)
uint32_t Reserved_374; // offset: 374 (0x176)
uint32_t Reserved_375; // offset: 375 (0x177)
uint32_t Reserved_376; // offset: 376 (0x178)
uint32_t Reserved_377; // offset: 377 (0x179)
uint32_t Reserved_378; // offset: 378 (0x17A)
uint32_t Reserved_379; // offset: 379 (0x17B)
uint32_t Reserved_380; // offset: 380 (0x17C)
uint32_t Reserved_381; // offset: 381 (0x17D)
uint32_t Reserved_382; // offset: 382 (0x17E)
uint32_t Reserved_383; // offset: 383 (0x17F)
uint32_t Reserved_384; // offset: 384 (0x180)
uint32_t Reserved_385; // offset: 385 (0x181)
uint32_t Reserved_386; // offset: 386 (0x182)
uint32_t Reserved_387; // offset: 387 (0x183)
uint32_t Reserved_388; // offset: 388 (0x184)
uint32_t Reserved_389; // offset: 389 (0x185)
uint32_t Reserved_390; // offset: 390 (0x186)
uint32_t Reserved_391; // offset: 391 (0x187)
uint32_t Reserved_392; // offset: 392 (0x188)
uint32_t Reserved_393; // offset: 393 (0x189)
uint32_t Reserved_394; // offset: 394 (0x18A)
uint32_t Reserved_395; // offset: 395 (0x18B)
uint32_t Reserved_396; // offset: 396 (0x18C)
uint32_t Reserved_397; // offset: 397 (0x18D)
uint32_t Reserved_398; // offset: 398 (0x18E)
uint32_t Reserved_399; // offset: 399 (0x18F)
uint32_t Reserved_400; // offset: 400 (0x190)
uint32_t Reserved_401; // offset: 401 (0x191)
uint32_t Reserved_402; // offset: 402 (0x192)
uint32_t Reserved_403; // offset: 403 (0x193)
uint32_t Reserved_404; // offset: 404 (0x194)
uint32_t Reserved_405; // offset: 405 (0x195)
uint32_t Reserved_406; // offset: 406 (0x196)
uint32_t Reserved_407; // offset: 407 (0x197)
uint32_t Reserved_408; // offset: 408 (0x198)
uint32_t Reserved_409; // offset: 409 (0x199)
uint32_t Reserved_410; // offset: 410 (0x19A)
uint32_t Reserved_411; // offset: 411 (0x19B)
uint32_t Reserved_412; // offset: 412 (0x19C)
uint32_t Reserved_413; // offset: 413 (0x19D)
uint32_t Reserved_414; // offset: 414 (0x19E)
uint32_t Reserved_415; // offset: 415 (0x19F)
uint32_t Reserved_416; // offset: 416 (0x1A0)
uint32_t Reserved_417; // offset: 417 (0x1A1)
uint32_t Reserved_418; // offset: 418 (0x1A2)
uint32_t Reserved_419; // offset: 419 (0x1A3)
uint32_t Reserved_420; // offset: 420 (0x1A4)
uint32_t Reserved_421; // offset: 421 (0x1A5)
uint32_t Reserved_422; // offset: 422 (0x1A6)
uint32_t Reserved_423; // offset: 423 (0x1A7)
uint32_t Reserved_424; // offset: 424 (0x1A8)
uint32_t Reserved_425; // offset: 425 (0x1A9)
uint32_t Reserved_426; // offset: 426 (0x1AA)
uint32_t Reserved_427; // offset: 427 (0x1AB)
uint32_t Reserved_428; // offset: 428 (0x1AC)
uint32_t Reserved_429; // offset: 429 (0x1AD)
uint32_t Reserved_430; // offset: 430 (0x1AE)
uint32_t Reserved_431; // offset: 431 (0x1AF)
uint32_t Reserved_432; // offset: 432 (0x1B0)
uint32_t Reserved_433; // offset: 433 (0x1B1)
uint32_t Reserved_434; // offset: 434 (0x1B2)
uint32_t Reserved_435; // offset: 435 (0x1B3)
uint32_t Reserved_436; // offset: 436 (0x1B4)
uint32_t Reserved_437; // offset: 437 (0x1B5)
uint32_t Reserved_438; // offset: 438 (0x1B6)
uint32_t Reserved_439; // offset: 439 (0x1B7)
uint32_t Reserved_440; // offset: 440 (0x1B8)
uint32_t Reserved_441; // offset: 441 (0x1B9)
uint32_t Reserved_442; // offset: 442 (0x1BA)
uint32_t Reserved_443; // offset: 443 (0x1BB)
uint32_t Reserved_444; // offset: 444 (0x1BC)
uint32_t Reserved_445; // offset: 445 (0x1BD)
uint32_t Reserved_446; // offset: 446 (0x1BE)
uint32_t Reserved_447; // offset: 447 (0x1BF)
uint32_t Reserved_448; // offset: 448 (0x1C0)
uint32_t Reserved_449; // offset: 449 (0x1C1)
uint32_t Reserved_450; // offset: 450 (0x1C2)
uint32_t Reserved_451; // offset: 451 (0x1C3)
uint32_t Reserved_452; // offset: 452 (0x1C4)
uint32_t Reserved_453; // offset: 453 (0x1C5)
uint32_t Reserved_454; // offset: 454 (0x1C6)
uint32_t Reserved_455; // offset: 455 (0x1C7)
uint32_t Reserved_456; // offset: 456 (0x1C8)
uint32_t Reserved_457; // offset: 457 (0x1C9)
uint32_t Reserved_458; // offset: 458 (0x1CA)
uint32_t Reserved_459; // offset: 459 (0x1CB)
uint32_t Reserved_460; // offset: 460 (0x1CC)
uint32_t Reserved_461; // offset: 461 (0x1CD)
uint32_t Reserved_462; // offset: 462 (0x1CE)
uint32_t Reserved_463; // offset: 463 (0x1CF)
uint32_t Reserved_464; // offset: 464 (0x1D0)
uint32_t Reserved_465; // offset: 465 (0x1D1)
uint32_t Reserved_466; // offset: 466 (0x1D2)
uint32_t Reserved_467; // offset: 467 (0x1D3)
uint32_t Reserved_468; // offset: 468 (0x1D4)
uint32_t Reserved_469; // offset: 469 (0x1D5)
uint32_t Reserved_470; // offset: 470 (0x1D6)
uint32_t Reserved_471; // offset: 471 (0x1D7)
uint32_t Reserved_472; // offset: 472 (0x1D8)
uint32_t Reserved_473; // offset: 473 (0x1D9)
uint32_t Reserved_474; // offset: 474 (0x1DA)
uint32_t Reserved_475; // offset: 475 (0x1DB)
uint32_t Reserved_476; // offset: 476 (0x1DC)
uint32_t Reserved_477; // offset: 477 (0x1DD)
uint32_t Reserved_478; // offset: 478 (0x1DE)
uint32_t Reserved_479; // offset: 479 (0x1DF)
uint32_t Reserved_480; // offset: 480 (0x1E0)
uint32_t Reserved_481; // offset: 481 (0x1E1)
uint32_t Reserved_482; // offset: 482 (0x1E2)
uint32_t Reserved_483; // offset: 483 (0x1E3)
uint32_t Reserved_484; // offset: 484 (0x1E4)
uint32_t Reserved_485; // offset: 485 (0x1E5)
uint32_t Reserved_486; // offset: 486 (0x1E6)
uint32_t Reserved_487; // offset: 487 (0x1E7)
uint32_t Reserved_488; // offset: 488 (0x1E8)
uint32_t Reserved_489; // offset: 489 (0x1E9)
uint32_t Reserved_490; // offset: 490 (0x1EA)
uint32_t Reserved_491; // offset: 491 (0x1EB)
uint32_t Reserved_492; // offset: 492 (0x1EC)
uint32_t Reserved_493; // offset: 493 (0x1ED)
uint32_t Reserved_494; // offset: 494 (0x1EE)
uint32_t Reserved_495; // offset: 495 (0x1EF)
uint32_t Reserved_496; // offset: 496 (0x1F0)
uint32_t Reserved_497; // offset: 497 (0x1F1)
uint32_t Reserved_498; // offset: 498 (0x1F2)
uint32_t Reserved_499; // offset: 499 (0x1F3)
uint32_t Reserved_500; // offset: 500 (0x1F4)
uint32_t Reserved_501; // offset: 501 (0x1F5)
uint32_t Reserved_502; // offset: 502 (0x1F6)
uint32_t Reserved_503; // offset: 503 (0x1F7)
uint32_t Reserved_504; // offset: 504 (0x1F8)
uint32_t Reserved_505; // offset: 505 (0x1F9)
uint32_t Reserved_506; // offset: 506 (0x1FA)
uint32_t Reserved_507; // offset: 507 (0x1FB)
uint32_t Reserved_508; // offset: 508 (0x1FC)
uint32_t Reserved_509; // offset: 509 (0x1FD)
uint32_t Reserved_510; // offset: 510 (0x1FE)
uint32_t Reserved_511; // offset: 511 (0x1FF)
} STRMEC_COMPUTE_512DW_MQD, *PSTRMEC_COMPUTE_512DW_MQD;
#endif
} // gfx9
} // pm4_profile
#endif
projects/rocr-runtime/runtime/hsa-ext-aql-profile/gfxip/gfx9/f32_mec_pm4_packets_vg10.h
+1724
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projects/rocr-runtime/runtime/hsa-ext-aql-profile/gfxip/gfx9/f32_mes_pm4_packets_vg10.h
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//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
//
// Trade secret of Advanced Micro Devices, Inc.
// Copyright 2014, Advanced Micro Devices, Inc., (unpublished)
//
// All rights reserved. This notice is intended as a precaution against
// inadvertent publication and does not imply publication or any waiver
// of confidentiality. The year included in the foregoing notice is the
// year of creation of the work.
//
//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
#ifndef F32_MES_PM4_PACKETS_H
#define F32_MES_PM4_PACKETS_H
namespace pm4_profile {
namespace gfx9 {
#ifndef PM4_MES_HEADER_DEFINED
#define PM4_MES_HEADER_DEFINED
typedef union PM4_MES_TYPE_3_HEADER {
struct {
uint32_t reserved1 : 8; ///< reserved
uint32_t opcode : 8; ///< IT opcode
uint32_t count : 14; ///< number of DWORDs - 1 in the information body.
uint32_t type : 2; ///< packet identifier. It should be 3 for type 3 packets
};
uint32_t u32All;
} PM4_MES_TYPE_3_HEADER;
#endif // PM4_MES_HEADER_DEFINED
//--------------------MES_SET_RESOURCES--------------------
#ifndef PM4_MES_SET_RESOURCES_DEFINED
#define PM4_MES_SET_RESOURCES_DEFINED
enum MES_SET_RESOURCES_queue_type_enum {
queue_type__mes_set_resources__kernel_interface_queue_kiq = 0,
queue_type__mes_set_resources__hsa_interface_queue_hiq = 1,
queue_type__mes_set_resources__hsa_debug_interface_queue = 4
};
typedef struct PM4_MES_SET_RESOURCES {
union {
PM4_MES_TYPE_3_HEADER header; /// header
uint32_t ordinal1;
};
union {
struct {
uint32_t vmid_mask : 16;
uint32_t unmap_latency : 8;
uint32_t reserved1 : 5;
MES_SET_RESOURCES_queue_type_enum queue_type : 3;
} bitfields2;
uint32_t ordinal2;
};
uint32_t queue_mask_lo;
uint32_t queue_mask_hi;
uint32_t gws_mask_lo;
uint32_t gws_mask_hi;
union {
struct {
uint32_t oac_mask : 16;
uint32_t reserved2 : 16;
} bitfields7;
uint32_t ordinal7;
};
union {
struct {
uint32_t gds_heap_base : 6;
uint32_t reserved3 : 5;
uint32_t gds_heap_size : 6;
uint32_t reserved4 : 15;
} bitfields8;
uint32_t ordinal8;
};
} PM4MES_SET_RESOURCES, *PPM4MES_SET_RESOURCES;
#endif
//--------------------MES_RUN_LIST--------------------
#ifndef PM4_MES_RUN_LIST_DEFINED
#define PM4_MES_RUN_LIST_DEFINED
typedef struct PM4_MES_RUN_LIST {
union {
PM4_MES_TYPE_3_HEADER header; /// header
uint32_t ordinal1;
};
union {
struct {
uint32_t reserved1 : 2;
uint32_t ib_base_lo : 30;
} bitfields2;
uint32_t ordinal2;
};
uint32_t ib_base_hi;
union {
struct {
uint32_t ib_size : 20;
uint32_t chain : 1;
uint32_t offload_polling : 1;
uint32_t reserved2 : 1;
uint32_t valid : 1;
uint32_t process_cnt : 4;
uint32_t reserved3 : 4;
} bitfields4;
uint32_t ordinal4;
};
} PM4MES_RUN_LIST, *PPM4MES_RUN_LIST;
#endif
//--------------------MES_MAP_PROCESS--------------------
#ifndef PM4_MES_MAP_PROCESS_DEFINED
#define PM4_MES_MAP_PROCESS_DEFINED
typedef struct PM4_MES_MAP_PROCESS {
union {
PM4_MES_TYPE_3_HEADER header; /// header
uint32_t ordinal1;
};
union {
struct {
uint32_t pasid : 16;
uint32_t reserved1 : 8;
uint32_t diq_enable : 1;
uint32_t process_quantum : 7;
} bitfields2;
uint32_t ordinal2;
};
uint32_t vm_context_page_table_base_addr_lo32;
uint32_t vm_context_page_table_base_addr_hi32;
uint32_t sh_mem_bases;
uint32_t sh_mem_config;
uint32_t sq_shader_tba_lo;
uint32_t sq_shader_tba_hi;
uint32_t sq_shader_tma_lo;
uint32_t sq_shader_tma_hi;
uint32_t reserved2;
uint32_t gds_addr_lo;
uint32_t gds_addr_hi;
union {
struct {
uint32_t num_gws : 6;
uint32_t reserved3 : 1;
uint32_t sdma_enable : 1;
uint32_t num_oac : 4;
uint32_t reserved4 : 4;
uint32_t gds_size : 6;
uint32_t num_queues : 10;
} bitfields14;
uint32_t ordinal14;
};
uint32_t completion_signal_lo32;
uint32_t completion_signal_hi32;
} PM4MES_MAP_PROCESS, *PPM4MES_MAP_PROCESS;
#endif
//--------------------MES_MAP_PROCESS_VM--------------------
#ifndef PM4_MES_MAP_PROCESS_VM_DEFINED
#define PM4_MES_MAP_PROCESS_VM_DEFINED
typedef struct PM4_MES_MAP_PROCESS_VM {
union {
PM4_MES_TYPE_3_HEADER header; /// header
uint32_t ordinal1;
};
uint32_t reserved1;
uint32_t vm_context_cntl;
uint32_t reserved2;
uint32_t vm_context_page_table_end_addr_lo32;
uint32_t vm_context_page_table_end_addr_hi32;
uint32_t vm_context_page_table_start_addr_lo32;
uint32_t vm_context_page_table_start_addr_hi32;
uint32_t reserved3;
uint32_t reserved4;
uint32_t reserved5;
uint32_t reserved6;
uint32_t reserved7;
uint32_t reserved8;
uint32_t completion_signal_lo32;
uint32_t completion_signal_hi32;
} PM4MES_MAP_PROCESS_VM, *PPM4MES_MAP_PROCESS_VM;
#endif
//--------------------MES_MAP_QUEUES--------------------
#ifndef PM4_MES_MAP_QUEUES_DEFINED
#define PM4_MES_MAP_QUEUES_DEFINED
enum MES_MAP_QUEUES_queue_sel_enum {
queue_sel__mes_map_queues__map_to_specified_queue_slots = 0,
queue_sel__mes_map_queues__map_to_hws_determined_queue_slots = 1
};
enum MES_MAP_QUEUES_queue_type_enum {
queue_type__mes_map_queues__normal_compute = 0,
queue_type__mes_map_queues__debug_interface_queue = 1,
queue_type__mes_map_queues__normal_latency_static_queue = 2,
queue_type__mes_map_queues__low_latency_static_queue = 3
};
enum MES_MAP_QUEUES_alloc_format_enum {
alloc_format__mes_map_queues__one_per_pipe = 0,
alloc_format__mes_map_queues__all_on_one_pipe = 1
};
enum MES_MAP_QUEUES_engine_sel_enum {
engine_sel__mes_map_queues__compute = 0,
engine_sel__mes_map_queues__sdma0 = 2,
engine_sel__mes_map_queues__sdma1 = 3,
engine_sel__mes_map_queues__gfx = 4
};
typedef struct PM4_MES_MAP_QUEUES {
union {
PM4_MES_TYPE_3_HEADER header; /// header
uint32_t ordinal1;
};
union {
struct {
uint32_t reserved1 : 4;
MES_MAP_QUEUES_queue_sel_enum queue_sel : 2;
uint32_t reserved2 : 2;
uint32_t vmid : 4;
uint32_t reserved3 : 1;
uint32_t queue : 8;
MES_MAP_QUEUES_queue_type_enum queue_type : 3;
MES_MAP_QUEUES_alloc_format_enum alloc_format : 2;
MES_MAP_QUEUES_engine_sel_enum engine_sel : 3;
uint32_t num_queues : 3;
} bitfields2;
uint32_t ordinal2;
};
union {
struct {
uint32_t reserved4 : 1;
uint32_t check_disable : 1;
uint32_t doorbell_offset : 26;
uint32_t reserved5 : 4;
} bitfields3;
uint32_t ordinal3;
};
uint32_t mqd_addr_lo;
uint32_t mqd_addr_hi;
uint32_t wptr_addr_lo;
uint32_t wptr_addr_hi;
} PM4MES_MAP_QUEUES, *PPM4MES_MAP_QUEUES;
#endif
//--------------------MES_QUERY_STATUS--------------------
#ifndef PM4_MES_QUERY_STATUS_DEFINED
#define PM4_MES_QUERY_STATUS_DEFINED
enum MES_QUERY_STATUS_interrupt_sel_enum {
interrupt_sel__mes_query_status__completion_status = 0,
interrupt_sel__mes_query_status__process_status = 1,
interrupt_sel__mes_query_status__queue_status = 2
};
enum MES_QUERY_STATUS_command_enum {
command__mes_query_status__interrupt_only = 0,
command__mes_query_status__fence_only_immediate = 1,
command__mes_query_status__fence_only_after_write_ack = 2,
command__mes_query_status__fence_wait_for_write_ack_send_interrupt = 3
};
enum MES_QUERY_STATUS_engine_sel_enum {
engine_sel__mes_query_status__compute = 0,
engine_sel__mes_query_status__gfx = 4
};
typedef struct PM4_MES_QUERY_STATUS {
union {
PM4_MES_TYPE_3_HEADER header; /// header
uint32_t ordinal1;
};
union {
struct {
uint32_t context_id : 28;
MES_QUERY_STATUS_interrupt_sel_enum interrupt_sel : 2;
MES_QUERY_STATUS_command_enum command : 2;
} bitfields2;
uint32_t ordinal2;
};
union {
struct {
uint32_t pasid : 16;
uint32_t reserved1 : 16;
} bitfields3a;
struct {
uint32_t reserved2 : 2;
uint32_t doorbell_offset : 26;
MES_QUERY_STATUS_engine_sel_enum engine_sel : 3;
uint32_t reserved3 : 1;
} bitfields3b;
uint32_t ordinal3;
};
uint32_t addr_lo;
uint32_t addr_hi;
uint32_t data_lo;
uint32_t data_hi;
} PM4MES_QUERY_STATUS, *PPM4MES_QUERY_STATUS;
#endif
//--------------------MES_UNMAP_QUEUES--------------------
#ifndef PM4_MES_UNMAP_QUEUES_DEFINED
#define PM4_MES_UNMAP_QUEUES_DEFINED
enum MES_UNMAP_QUEUES_action_enum {
action__mes_unmap_queues__preempt_queues = 0,
action__mes_unmap_queues__reset_queues = 1,
action__mes_unmap_queues__disable_process_queues = 2,
action__mes_unmap_queues__preempt_queues_no_unmap = 3
};
enum MES_UNMAP_QUEUES_queue_sel_enum {
queue_sel__mes_unmap_queues__perform_request_on_specified_queues = 0,
queue_sel__mes_unmap_queues__perform_request_on_pasid_queues = 1,
queue_sel__mes_unmap_queues__unmap_all_queues = 2,
queue_sel__mes_unmap_queues__unmap_all_non_static_queues = 3
};
enum MES_UNMAP_QUEUES_engine_sel_enum {
engine_sel__mes_unmap_queues__compute = 0,
engine_sel__mes_unmap_queues__sdma0 = 2,
engine_sel__mes_unmap_queues__sdma1 = 3,
engine_sel__mes_unmap_queues__gfx = 4
};
typedef struct PM4_MES_UNMAP_QUEUES {
union {
PM4_MES_TYPE_3_HEADER header; /// header
uint32_t ordinal1;
};
union {
struct {
MES_UNMAP_QUEUES_action_enum action : 2;
uint32_t reserved1 : 2;
MES_UNMAP_QUEUES_queue_sel_enum queue_sel : 2;
uint32_t reserved2 : 20;
MES_UNMAP_QUEUES_engine_sel_enum engine_sel : 3;
uint32_t num_queues : 3;
} bitfields2;
uint32_t ordinal2;
};
union {
struct {
uint32_t pasid : 16;
uint32_t reserved3 : 16;
} bitfields3a;
struct {
uint32_t reserved4 : 2;
uint32_t doorbell_offset0 : 26;
uint32_t reserved5 : 4;
} bitfields3b;
uint32_t ordinal3;
};
union {
struct {
uint32_t reserved6 : 2;
uint32_t doorbell_offset1 : 26;
uint32_t reserved7 : 4;
} bitfields4a;
struct {
uint32_t rb_wptr : 20;
uint32_t reserved8 : 12;
} bitfields4b;
uint32_t ordinal4;
};
union {
struct {
uint32_t reserved9 : 2;
uint32_t doorbell_offset2 : 26;
uint32_t reserved10 : 4;
} bitfields5;
uint32_t ordinal5;
};
union {
struct {
uint32_t reserved11 : 2;
uint32_t doorbell_offset3 : 26;
uint32_t reserved12 : 4;
} bitfields6;
uint32_t ordinal6;
};
} PM4MES_UNMAP_QUEUES, *PPM4MES_UNMAP_QUEUES;
#endif
} // gfx9
} // pm4_profile
#endif
projects/rocr-runtime/runtime/hsa-ext-aql-profile/gfxip/gfx9/f32_pfp_pm4_packets_vg10.h
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projects/rocr-runtime/runtime/hsa-ext-aql-profile/gfxip/gfx9/gfx9_enum.h
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projects/rocr-runtime/runtime/hsa-ext-aql-profile/gfxip/gfx9/gfx9_mask.h
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projects/rocr-runtime/runtime/hsa-ext-aql-profile/gfxip/gfx9/gfx9_offset.h
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projects/rocr-runtime/runtime/hsa-ext-aql-profile/gfxip/gfx9/gfx9_pm4_it_opcodes.h
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//////////////////////////////////////////////////////////////////////////////////
// THIS FILE IS AUTO-GENERATED BY PITGEN (vA)
// !!!! DO NOT EDIT BY HAND !!!!
//////////////////////////////////////////////////////////////////////////////////
// Project: 10xx or later
// Description:
//
// PM4 PacketType3 IT_OpCode Definitions
// Extracted From ME and PFP F32 Microcode Jump Tables:
//
//////////////////////////////////////////////////////////////////////////////////
//
// Trade secret of ATI Technologies, Inc.
// Copyright 1999, ATI Technologies, Inc., (unpublished)
//
// All rights reserved. This notice is intended as a precaution against
// inadvertent publication and does not imply publication or any waiver
// of confidentiality. The year included in the foregoing notice is the
// year of creation of the work.
//////////////////////////////////////////////////////////////////////////////////
#ifndef PM4_IT_OPCODES_H
#define PM4_IT_OPCODES_H
namespace pm4_profile {
namespace gfx9 {
// typedef enum IT_OpCodeType {
enum IT_OpCodeType {
IT_NOP = 0x10,
IT_SET_BASE = 0x11,
IT_CLEAR_STATE = 0x12,
IT_INDEX_BUFFER_SIZE = 0x13,
IT_DISPATCH_DIRECT = 0x15,
IT_DISPATCH_INDIRECT = 0x16,
IT_INDIRECT_BUFFER_END = 0x17,
IT_INDIRECT_BUFFER_CNST_END = 0x19,
IT_ATOMIC_GDS = 0x1D,
IT_ATOMIC_MEM = 0x1E,
IT_OCCLUSION_QUERY = 0x1F,
IT_SET_PREDICATION = 0x20,
IT_REG_RMW = 0x21,
IT_COND_EXEC = 0x22,
IT_PRED_EXEC = 0x23,
IT_DRAW_INDIRECT = 0x24,
IT_DRAW_INDEX_INDIRECT = 0x25,
IT_INDEX_BASE = 0x26,
IT_DRAW_INDEX_2 = 0x27,
IT_CONTEXT_CONTROL = 0x28,
IT_INDEX_TYPE = 0x2A,
IT_DRAW_INDIRECT_MULTI = 0x2C,
IT_DRAW_INDEX_AUTO = 0x2D,
IT_NUM_INSTANCES = 0x2F,
IT_DRAW_INDEX_MULTI_AUTO = 0x30,
IT_INDIRECT_BUFFER_CNST = 0x33,
IT_STRMOUT_BUFFER_UPDATE = 0x34,
IT_DRAW_INDEX_OFFSET_2 = 0x35,
IT_WRITE_DATA = 0x37,
IT_DRAW_INDEX_INDIRECT_MULTI = 0x38,
IT_MEM_SEMAPHORE = 0x39,
IT_DRAW_INDEX_MULTI_INST = 0x3A,
IT_WAIT_REG_MEM = 0x3C,
IT_INDIRECT_BUFFER = 0x3F,
IT_COND_INDIRECT_BUFFER = 0x3F,
IT_COPY_DATA = 0x40,
IT_PFP_SYNC_ME = 0x42,
IT_ME_INITIALIZE = 0x44,
IT_COND_WRITE = 0x45,
IT_EVENT_WRITE = 0x46,
IT_RELEASE_MEM = 0x49,
IT_PREAMBLE_CNTL = 0x4A,
IT_DMA_DATA = 0x50,
IT_CONTEXT_REG_RMW = 0x51,
IT_GFX_CNTX_UPDATE = 0x52,
IT_BLK_CNTX_UPDATE = 0x53,
IT_INCR_UPDT_STATE = 0x55,
IT_ACQUIRE_MEM = 0x58,
IT_REWIND = 0x59,
IT_GEN_PDEPTE = 0x5B,
IT_PRIME_UTCL2 = 0x5D,
IT_LOAD_UCONFIG_REG = 0x5E,
IT_LOAD_SH_REG = 0x5F,
IT_LOAD_CONFIG_REG = 0x60,
IT_LOAD_CONTEXT_REG = 0x61,
IT_SET_CONFIG_REG = 0x68,
IT_SET_CONTEXT_REG = 0x69,
IT_SET_CONTEXT_REG_INDEX = 0x6A,
IT_SET_SH_REG_DI = 0x72,
IT_SET_SH_REG = 0x76,
IT_SET_SH_REG_OFFSET = 0x77,
IT_SET_QUEUE_REG = 0x78,
IT_SET_UCONFIG_REG = 0x79,
IT_SET_UCONFIG_REG_INDEX = 0x7A,
IT_FORWARD_HEADER = 0x7C,
IT_SCRATCH_RAM_WRITE = 0x7D,
IT_SCRATCH_RAM_READ = 0x7E,
IT_LOAD_CONST_RAM = 0x80,
IT_WRITE_CONST_RAM = 0x81,
IT_DUMP_CONST_RAM = 0x83,
IT_INCREMENT_CE_COUNTER = 0x84,
IT_INCREMENT_DE_COUNTER = 0x85,
IT_WAIT_ON_CE_COUNTER = 0x86,
IT_WAIT_ON_DE_COUNTER_DIFF = 0x88,
IT_SWITCH_BUFFER = 0x8B,
IT_DISPATCH_DRAW_PREAMBLE = 0x8C,
IT_DISPATCH_DRAW = 0x8D,
IT_COND_PREEMPT = 0x8E,
IT_DRAW_MULTI_PREAMBLE = 0x8F,
IT_FRAME_CONTROL = 0x90,
IT_INDEX_ATTRIBUTES_INDIRECT = 0x91,
IT_WAIT_REG_MEM64 = 0x93,
IT_GET_LOD_STATS = 0x94,
IT_COPY_DATA_RB = 0x96,
IT_DMA_DATA_FILL_MULTI = 0x9A,
IT_SET_SH_REG_INDEX = 0x9B,
IT_EOP_BUFFER_END = 0x18,
IT_INTR_BUFFER_END = 0x1A,
IT_CP_DMA = 0x41,
IT_SURFACE_SYNC = 0x43,
IT_EVENT_WRITE_EOP = 0x47,
IT_EVENT_WRITE_EOS = 0x48,
IT_INTERRUPT = 0x5A,
IT_INDIRECT_BUFFER_PASID = 0x5C,
IT_LOAD_COMPUTE_STATE = 0x62,
IT_SET_CONTEXT_REG_INDIRECT = 0x73,
IT_DISPATCH_DRAW_PREAMBLE_ACE = 0x8C,
IT_DISPATCH_DRAW_ACE = 0x8D,
IT_HDP_FLUSH = 0x95,
IT_SECURE_CONTROL = 0x97,
IT_INVALIDATE_TLBS = 0x98,
IT_AQL_PACKET = 0x99,
IT_SET_RESOURCES = 0xA0,
IT_MAP_PROCESS = 0xA1,
IT_MAP_QUEUES = 0xA2,
IT_UNMAP_QUEUES = 0xA3,
IT_QUERY_STATUS = 0xA4,
IT_RUN_LIST = 0xA5,
IT_MAP_PROCESS_VM = 0xA6
};
//} IT_OpCodeType;
#define PM4_TYPE_0 0
#define PM4_TYPE_2 2
#define PM4_TYPE_3 3
} // gfx9
} // pm4_profile
#endif // PM4_IT_OPCODES_H
projects/rocr-runtime/runtime/hsa-ext-aql-profile/gfxip/gfx9/gfx9_pm4defs.h
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/*
***************************************************************************************************
*
* Trade secret of Advanced Micro Devices, Inc.
* Copyright (c) 2010 Advanced Micro Devices, Inc. (unpublished)
*
* All rights reserved. This notice is intended as a precaution against inadvertent publication and
* does not imply publication or any waiver of confidentiality. The year included in the foregoing
* notice is the year of creation of the work.
*
***************************************************************************************************
*/
#ifndef _GFX9_PM4DEFS_H_
#define _GFX9_PM4DEFS_H_
/******************************************************************************
*
* gfx9_pm4defs.h
*
* GFX9 PM4 definitions, typedefs, and enumerations.
*
******************************************************************************/
#define COPY_DATA_SEL_COUNT_1DW 0 ///< Copy 1 word (32 bits)
#define COPY_DATA_SEL_SRC_SYS_PERF_COUNTER 4 ///< Privileged memory performance counter
#endif // _GFX9_PM4DEFS_H_
projects/rocr-runtime/runtime/hsa-ext-aql-profile/gfxip/gfx9/gfx9_shift.h
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projects/rocr-runtime/runtime/hsa-ext-aql-profile/gfxip/gfx9/gfx9_typedef.h
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projects/rocr-runtime/runtime/hsa-ext-aql-profile/gfxip/gfx9/gfx9_utils.h
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/*
***********************************************************************************************************************
*
* Trade secret of Advanced Micro Devices, Inc.
* Copyright (c) 2016, Advanced Micro Devices, Inc., (unpublished)
*
* All rights reserved. This notice is intended as a precaution against inadvertent publication and
*does not imply
* publication or any waiver of confidentiality. The year included in the foregoing notice is the
*year of creation of
* the work.
*
**********************************************************************************************************************/
#ifndef _GFX9_UTILS_H_
#define _GFX9_UTILS_H_
namespace pm4_profile {
namespace gfx9 {
/*
* PM4 packet helper constants and macros.
* Constructed from header file:
* core/hw/gfxip/gfx9/chip/gfx9_f32_pfp_pm4_packets_gr.h
*/
// Shift amounts for each field of a type-3 PM4 header:
#define PM4_PREDICATE_SHIFT 0
#define PM4_SHADERTYPE_SHIFT 1
#define PM4_TYPE_SHIFT 30
#define PM4_COUNT_SHIFT 16
#define PM4_OPCODE_SHIFT 8
/*
* Constructs a PM4 type-3 header and packs it into a uint.
*/
#define PM4_TYPE3_HDR(_opc_, _count_) \
(uint32_t)((3) << PM4_TYPE_SHIFT | ((_count_)-2) << PM4_COUNT_SHIFT | (_opc_) << PM4_OPCODE_SHIFT)
// Packet shader types:
#define PM4_SHADER_GRAPHICS 0
#define PM4_SHADER_COMPUTE 1
// Indices into VGT event type table
#define EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP 0
#define EVENT_WRITE_INDEX_ZPASS_DONE 1
#define EVENT_WRITE_INDEX_SAMPLE_PIPELINESTAT 2
#define EVENT_WRITE_INDEX_SAMPLE_STREAMOUTSTATS 3
#define EVENT_WRITE_INDEX_VS_PS_PARTIAL_FLUSH 4
#define EVENT_WRITE_INDEX_ANY_EOP_TIMESTAMP 5
#define EVENT_WRITE_INDEX_ANY_EOS_TIMESTAMP 6
#define EVENT_WRITE_EOS_INDEX_CSDONE_PSDONE 6
#define EVENT_WRITE_INDEX_CACHE_FLUSH_EVENT 7
#define EVENT_WRITE_INDEX_INVALID 0xffffffff
static const uint8_t EventTypeToIndexTable[] = {
0, // Reserved_0x00 0x00000000
EVENT_WRITE_INDEX_SAMPLE_STREAMOUTSTATS, // SAMPLE_STREAMOUTSTATS1
// 0x00000001
EVENT_WRITE_INDEX_SAMPLE_STREAMOUTSTATS, // SAMPLE_STREAMOUTSTATS2
// 0x00000002
EVENT_WRITE_INDEX_SAMPLE_STREAMOUTSTATS, // SAMPLE_STREAMOUTSTATS3
// 0x00000003
EVENT_WRITE_INDEX_ANY_EOP_TIMESTAMP, // CACHE_FLUSH_TS 0x00000004
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // CONTEXT_DONE 0x00000005
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // CACHE_FLUSH 0x00000006
EVENT_WRITE_INDEX_VS_PS_PARTIAL_FLUSH, // CS_PARTIAL_FLUSH 0x00000007
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // VGT_STREAMOUT_SYNC 0x00000008
0, // Reserved_0x09 0x00000009
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // VGT_STREAMOUT_RESET 0x0000000a
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // END_OF_PIPE_INCR_DE 0x0000000b
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // END_OF_PIPE_IB_END 0x0000000c
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // RST_PIX_CNT 0x0000000d
0, // Reserved_0x0E 0x0000000e
EVENT_WRITE_INDEX_VS_PS_PARTIAL_FLUSH, // VS_PARTIAL_FLUSH 0x0000000f
EVENT_WRITE_INDEX_VS_PS_PARTIAL_FLUSH, // PS_PARTIAL_FLUSH 0x00000010
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // FLUSH_HS_OUTPUT 0x00000011
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // FLUSH_LS_OUTPUT 0x00000012
0, // Reserved_0x13 0x00000013
EVENT_WRITE_INDEX_ANY_EOP_TIMESTAMP, // CACHE_FLUSH_AND_INV_TS_EVENT
// 0x00000014
EVENT_WRITE_INDEX_ZPASS_DONE, // ZPASS_DONE 0x00000015
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // CACHE_FLUSH_AND_INV_EVENT
// 0x00000016
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // PERFCOUNTER_START 0x00000017
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // PERFCOUNTER_STOP 0x00000018
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // PIPELINESTAT_START 0x00000019
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // PIPELINESTAT_STOP 0x0000001a
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // PERFCOUNTER_SAMPLE 0x0000001b
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // FLUSH_ES_OUTPUT 0x0000001c
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // FLUSH_GS_OUTPUT 0x0000001d
EVENT_WRITE_INDEX_SAMPLE_PIPELINESTAT, // SAMPLE_PIPELINESTAT 0x0000001e
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // SO_VGTSTREAMOUT_FLUSH 0x0000001f
EVENT_WRITE_INDEX_SAMPLE_STREAMOUTSTATS, // SAMPLE_STREAMOUTSTATS
// 0x00000020
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // RESET_VTX_CNT 0x00000021
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // BLOCK_CONTEXT_DONE 0x00000022
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // CS_CONTEXT_DONE 0x00000023
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // VGT_FLUSH 0x00000024
0, // Reserved_0x25 0x00000025
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // SQ_NON_EVENT 0x00000026
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // SC_SEND_DB_VPZ 0x00000027
EVENT_WRITE_INDEX_ANY_EOP_TIMESTAMP, // BOTTOM_OF_PIPE_TS 0x00000028
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // FLUSH_SX_TS 0x00000029
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // DB_CACHE_FLUSH_AND_INV 0x0000002a
EVENT_WRITE_INDEX_ANY_EOP_TIMESTAMP, // FLUSH_AND_INV_DB_DATA_TS 0x0000002b
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // FLUSH_AND_INV_DB_META 0x0000002c
EVENT_WRITE_INDEX_ANY_EOP_TIMESTAMP, // FLUSH_AND_INV_CB_DATA_TS 0x0000002d
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // FLUSH_AND_INV_CB_META 0x0000002e
EVENT_WRITE_EOS_INDEX_CSDONE_PSDONE, // CS_DONE 0x0000002f
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // PS_DONE 0x00000030
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // FLUSH_AND_INV_CB_PIXEL_DATA
// 0x00000031
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // SX_CB_RAT_ACK_REQUEST 0x00000032
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // THREAD_TRACE_START 0x00000033
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // THREAD_TRACE_STOP 0x00000034
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // THREAD_TRACE_MARKER 0x00000035
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // THREAD_TRACE_FLUSH 0x00000036
EVENT_WRITE_INDEX_ANY_NON_TIMESTAMP, // THREAD_TRACE_FINISH 0x00000037
};
/// @brief Enum specifying the size of elements of a buffer
enum BufElementSize {
kBufElementSize2 = 0,
kBufElementSize4 = 1,
kBufElementSize8 = 2,
kBufElementSize16 = 3
};
/// @brief Enum specifying the striding of a buffer
enum BufIndexStride {
kBufIndexStride8 = 0,
kBufIndexStride16 = 1,
kBufIndexStride32 = 2,
kBufIndexStride64 = 3
};
} // gfx9
} // pm4_profile
#endif // _GFX9_UTILS_H_
projects/rocr-runtime/runtime/hsa-ext-aql-profile/test/simple_convolution/gfx8_simpleConvolution.hsaco
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projects/rocr-runtime/runtime/hsa-ext-aql-profile/test/simple_convolution/gfx9_simpleConvolution.hsaco
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