SWDEV-306642 - [ABI Break] Add texture/surface/device capabilities device struct entries
- Remove directed test which use gcnArch because they have been ported
to catch.
Change-Id: Ie4062b58572962a841c72831453e65685c3193ac
[ROCm/hip commit: 7156532286]
Cette révision appartient à :
Jatin Chaudhary
révisé par
Rahul Garg
Rahul Garg
Parent
8a1939c80f
révision
f6a1ad4ca1
@@ -88,76 +88,150 @@ typedef struct hipUUID_t {
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//---
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// Common headers for both NVCC and HCC paths:
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#define hipGetDeviceProperties hipGetDevicePropertiesR0600
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#define hipDeviceProp_t hipDeviceProp_tR0600
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/**
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* hipDeviceProp
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*
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*/
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typedef struct hipDeviceProp_t {
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char name[256]; ///< Device name.
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size_t totalGlobalMem; ///< Size of global memory region (in bytes).
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size_t sharedMemPerBlock; ///< Size of shared memory region (in bytes).
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int regsPerBlock; ///< Registers per block.
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int warpSize; ///< Warp size.
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int maxThreadsPerBlock; ///< Max work items per work group or workgroup max size.
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int maxThreadsDim[3]; ///< Max number of threads in each dimension (XYZ) of a block.
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int maxGridSize[3]; ///< Max grid dimensions (XYZ).
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int clockRate; ///< Max clock frequency of the multiProcessors in khz.
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int memoryClockRate; ///< Max global memory clock frequency in khz.
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int memoryBusWidth; ///< Global memory bus width in bits.
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size_t totalConstMem; ///< Size of shared memory region (in bytes).
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char name[256]; ///< Device name.
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hipUUID uuid; ///< UUID of a device
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char luid[8]; ///< 8-byte unique identifier. Only valid on windows
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unsigned int luidDeviceNodeMask; ///< LUID node mask
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size_t totalGlobalMem; ///< Size of global memory region (in bytes).
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size_t sharedMemPerBlock; ///< Size of shared memory region (in bytes).
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int regsPerBlock; ///< Registers per block.
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int warpSize; ///< Warp size.
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size_t memPitch; ///< Maximum pitch in bytes allowed by memory copies
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///< pitched memory
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int maxThreadsPerBlock; ///< Max work items per work group or workgroup max size.
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int maxThreadsDim[3]; ///< Max number of threads in each dimension (XYZ) of a block.
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int maxGridSize[3]; ///< Max grid dimensions (XYZ).
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int clockRate; ///< Max clock frequency of the multiProcessors in khz.
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size_t totalConstMem; ///< Size of shared memory region (in bytes).
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int major; ///< Major compute capability. On HCC, this is an approximation and features may
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///< differ from CUDA CC. See the arch feature flags for portable ways to query
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///< feature caps.
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int minor; ///< Minor compute capability. On HCC, this is an approximation and features may
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///< differ from CUDA CC. See the arch feature flags for portable ways to query
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///< feature caps.
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int multiProcessorCount; ///< Number of multi-processors (compute units).
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int l2CacheSize; ///< L2 cache size.
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int maxThreadsPerMultiProcessor; ///< Maximum resident threads per multi-processor.
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int computeMode; ///< Compute mode.
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size_t textureAlignment; ///< Alignment requirement for textures
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size_t texturePitchAlignment; ///< Pitch alignment requirement for texture references bound to
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int deviceOverlap; ///< Deprecated. Use asyncEngineCount instead
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int multiProcessorCount; ///< Number of multi-processors (compute units).
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int kernelExecTimeoutEnabled; ///< Run time limit for kernels executed on the device
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int integrated; ///< APU vs dGPU
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int canMapHostMemory; ///< Check whether HIP can map host memory
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int computeMode; ///< Compute mode.
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int maxTexture1D; ///< Maximum number of elements in 1D images
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int maxTexture1DMipmap; ///< Maximum 1D mipmap texture size
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int maxTexture1DLinear; ///< Maximum size for 1D textures bound to linear memory
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int maxTexture2D[2]; ///< Maximum dimensions (width, height) of 2D images, in image elements
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int maxTexture2DMipmap[2]; ///< Maximum number of elements in 2D array mipmap of images
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int maxTexture2DLinear[3]; ///< Maximum 2D tex dimensions if tex are bound to pitched memory
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int maxTexture2DGather[2]; ///< Maximum 2D tex dimensions if gather has to be performed
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int maxTexture3D[3]; ///< Maximum dimensions (width, height, depth) of 3D images, in image
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///< elements
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int maxTexture3DAlt[3]; ///< Maximum alternate 3D texture dims
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int maxTextureCubemap; ///< Maximum cubemap texture dims
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int maxTexture1DLayered[2]; ///< Maximum number of elements in 1D array images
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int maxTexture2DLayered[3]; ///< Maximum number of elements in 2D array images
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int maxTextureCubemapLayered[2]; ///< Maximum cubemaps layered texture dims
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int maxSurface1D; ///< Maximum 1D surface size
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int maxSurface2D[2]; ///< Maximum 2D surface size
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int maxSurface3D[3]; ///< Maximum 3D surface size
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int maxSurface1DLayered[2]; ///< Maximum 1D layered surface size
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int maxSurface2DLayered[3]; ///< Maximum 2D layared surface size
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int maxSurfaceCubemap; ///< Maximum cubemap surface size
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int maxSurfaceCubemapLayered[2]; ///< Maximum cubemap layered surface size
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size_t surfaceAlignment; ///< Alignment requirement for surface
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int concurrentKernels; ///< Device can possibly execute multiple kernels concurrently.
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int ECCEnabled; ///< Device has ECC support enabled
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int pciBusID; ///< PCI Bus ID.
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int pciDeviceID; ///< PCI Device ID.
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int pciDomainID; ///< PCI Domain ID
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int tccDriver; ///< 1:If device is Tesla device using TCC driver, else 0
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int asyncEngineCount; ///< Number of async engines
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int unifiedAddressing; ///< Does device and host share unified address space
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int memoryClockRate; ///< Max global memory clock frequency in khz.
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int memoryBusWidth; ///< Global memory bus width in bits.
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int l2CacheSize; ///< L2 cache size.
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int persistingL2CacheMaxSize; ///< Device's max L2 persisting lines in bytes
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int maxThreadsPerMultiProcessor; ///< Maximum resident threads per multi-processor.
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int streamPrioritiesSupported; ///< Device supports stream priority
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int globalL1CacheSupported; ///< Indicates globals are cached in L1
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int localL1CacheSupported; ///< Locals are cahced in L1
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size_t sharedMemPerMultiprocessor; ///< Amount of shared memory available per multiprocessor.
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int regsPerMultiprocessor; ///< registers available per multiprocessor
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int managedMemory; ///< Device supports allocating managed memory on this system
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int isMultiGpuBoard; ///< 1 if device is on a multi-GPU board, 0 if not.
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int multiGpuBoardGroupID; ///< Unique identifier for a group of devices on same multiboard GPU
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int hostNativeAtomicSupported; ///< Link between host and device supports native atomics
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int singleToDoublePrecisionPerfRatio; ///< Deprecated. CUDA only.
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int pageableMemoryAccess; ///< Device supports coherently accessing pageable memory
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///< without calling hipHostRegister on it
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int concurrentManagedAccess; ///< Device can coherently access managed memory concurrently with
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///< the CPU
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int computePreemptionSupported; ///< Is compute preemption supported on the device
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int canUseHostPointerForRegisteredMem; ///< Device can access host registered memory with same
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///< address as the host
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int cooperativeLaunch; ///< HIP device supports cooperative launch
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int cooperativeMultiDeviceLaunch; ///< HIP device supports cooperative launch on multiple
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///< devices
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size_t
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sharedMemPerBlockOptin; ///< Per device m ax shared mem per block usable by special opt in
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int pageableMemoryAccessUsesHostPageTables; ///< Device accesses pageable memory via the host's
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///< page tables
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int directManagedMemAccessFromHost; ///< Host can directly access managed memory on the device
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///< without migration
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int maxBlocksPerMultiProcessor; ///< Max number of blocks on CU
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int accessPolicyMaxWindowSize; ///< Max value of access policy window
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size_t reservedSharedMemPerBlock; ///< Shared memory reserved by driver per block
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int hostRegisterSupported; ///< Device supports hipHostRegister
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int sparseHipArraySupported; ///< Indicates if device supports sparse hip arrays
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int hostRegisterReadOnlySupported; ///< Device supports using the hipHostRegisterReadOnly flag
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///< with hipHostRegistger
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int timelineSemaphoreInteropSupported; ///< Indicates external timeline semaphore support
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int memoryPoolsSupported; ///< Indicates if device supports hipMallocAsync and hipMemPool APIs
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int gpuDirectRDMASupported; ///< Indicates device support of RDMA APIs
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unsigned int gpuDirectRDMAFlushWritesOptions; ///< Bitmask to be interpreted according to
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///< hipFlushGPUDirectRDMAWritesOptions
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int gpuDirectRDMAWritesOrdering; ///< value of hipGPUDirectRDMAWritesOrdering
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unsigned int
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memoryPoolSupportedHandleTypes; ///< Bitmask of handle types support with mempool based IPC
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int deferredMappingHipArraySupported; ///< Device supports deferred mapping HIP arrays and HIP
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///< mipmapped arrays
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int ipcEventSupported; ///< Device supports IPC events
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int clusterLaunch; ///< Device supports cluster launch
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int unifiedFunctionPointers; ///< Indicates device supports unified function pointers
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int reserved[63]; ///< CUDA Reserved.
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int hipReserved[32]; ///< Reserved for adding new entries for HIP/CUDA.
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/* HIP Only struct members */
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char gcnArchName[256]; ///< AMD GCN Arch Name. HIP Only.
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size_t maxSharedMemoryPerMultiProcessor; ///< Maximum Shared Memory Per CU. HIP Only.
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int clockInstructionRate; ///< Frequency in khz of the timer used by the device-side "clock*"
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///< instructions. New for HIP.
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hipDeviceArch_t arch; ///< Architectural feature flags. New for HIP.
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int concurrentKernels; ///< Device can possibly execute multiple kernels concurrently.
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int pciDomainID; ///< PCI Domain ID
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int pciBusID; ///< PCI Bus ID.
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int pciDeviceID; ///< PCI Device ID.
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size_t maxSharedMemoryPerMultiProcessor; ///< Maximum Shared Memory Per Multiprocessor.
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int isMultiGpuBoard; ///< 1 if device is on a multi-GPU board, 0 if not.
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int canMapHostMemory; ///< Check whether HIP can map host memory
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int gcnArch; ///< DEPRECATED: use gcnArchName instead
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char gcnArchName[256]; ///< AMD GCN Arch Name.
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int integrated; ///< APU vs dGPU
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int cooperativeLaunch; ///< HIP device supports cooperative launch
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int cooperativeMultiDeviceLaunch; ///< HIP device supports cooperative launch on multiple devices
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int maxTexture1DLinear; ///< Maximum size for 1D textures bound to linear memory
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int maxTexture1D; ///< Maximum number of elements in 1D images
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int maxTexture2D[2]; ///< Maximum dimensions (width, height) of 2D images, in image elements
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int maxTexture3D[3]; ///< Maximum dimensions (width, height, depth) of 3D images, in image elements
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unsigned int* hdpMemFlushCntl; ///< Addres of HDP_MEM_COHERENCY_FLUSH_CNTL register
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unsigned int* hdpRegFlushCntl; ///< Addres of HDP_REG_COHERENCY_FLUSH_CNTL register
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size_t memPitch; ///<Maximum pitch in bytes allowed by memory copies
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size_t textureAlignment; ///<Alignment requirement for textures
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size_t texturePitchAlignment; ///<Pitch alignment requirement for texture references bound to pitched memory
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int kernelExecTimeoutEnabled; ///<Run time limit for kernels executed on the device
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int ECCEnabled; ///<Device has ECC support enabled
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int tccDriver; ///< 1:If device is Tesla device using TCC driver, else 0
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int cooperativeMultiDeviceUnmatchedFunc; ///< HIP device supports cooperative launch on multiple
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///devices with unmatched functions
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int cooperativeMultiDeviceUnmatchedGridDim; ///< HIP device supports cooperative launch on multiple
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///devices with unmatched grid dimensions
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int cooperativeMultiDeviceUnmatchedBlockDim; ///< HIP device supports cooperative launch on multiple
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///devices with unmatched block dimensions
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int cooperativeMultiDeviceUnmatchedSharedMem; ///< HIP device supports cooperative launch on multiple
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///devices with unmatched shared memories
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int isLargeBar; ///< 1: if it is a large PCI bar device, else 0
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int asicRevision; ///< Revision of the GPU in this device
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int managedMemory; ///< Device supports allocating managed memory on this system
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int directManagedMemAccessFromHost; ///< Host can directly access managed memory on the device without migration
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int concurrentManagedAccess; ///< Device can coherently access managed memory concurrently with the CPU
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int pageableMemoryAccess; ///< Device supports coherently accessing pageable memory
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///< without calling hipHostRegister on it
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int pageableMemoryAccessUsesHostPageTables; ///< Device accesses pageable memory via the host's page tables
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unsigned int* hdpMemFlushCntl; ///< Addres of HDP_MEM_COHERENCY_FLUSH_CNTL register
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unsigned int* hdpRegFlushCntl; ///< Addres of HDP_REG_COHERENCY_FLUSH_CNTL register
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int cooperativeMultiDeviceUnmatchedFunc; ///< HIP device supports cooperative launch on
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///< multiple
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/// devices with unmatched functions
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int cooperativeMultiDeviceUnmatchedGridDim; ///< HIP device supports cooperative launch on
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///< multiple
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/// devices with unmatched grid dimensions
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int cooperativeMultiDeviceUnmatchedBlockDim; ///< HIP device supports cooperative launch on
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///< multiple
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/// devices with unmatched block dimensions
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int cooperativeMultiDeviceUnmatchedSharedMem; ///< HIP device supports cooperative launch on
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///< multiple
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/// devices with unmatched shared memories
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int isLargeBar; ///< 1: if it is a large PCI bar device, else 0
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int asicRevision; ///< Revision of the GPU in this device
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} hipDeviceProp_t;
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/**
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@@ -341,33 +415,34 @@ typedef enum hipDeviceAttribute_t {
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hipDeviceAttributeEccEnabled = hipDeviceAttributeCudaCompatibleBegin, ///< Whether ECC support is enabled.
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hipDeviceAttributeAccessPolicyMaxWindowSize, ///< Cuda only. The maximum size of the window policy in bytes.
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hipDeviceAttributeAsyncEngineCount, ///< Cuda only. Asynchronous engines number.
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hipDeviceAttributeAsyncEngineCount, ///< Asynchronous engines number.
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hipDeviceAttributeCanMapHostMemory, ///< Whether host memory can be mapped into device address space
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hipDeviceAttributeCanUseHostPointerForRegisteredMem,///< Cuda only. Device can access host registered memory
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hipDeviceAttributeCanUseHostPointerForRegisteredMem,///< Device can access host registered memory
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///< at the same virtual address as the CPU
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hipDeviceAttributeClockRate, ///< Peak clock frequency in kilohertz.
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hipDeviceAttributeComputeMode, ///< Compute mode that device is currently in.
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hipDeviceAttributeComputePreemptionSupported, ///< Cuda only. Device supports Compute Preemption.
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hipDeviceAttributeComputePreemptionSupported, ///< Device supports Compute Preemption.
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hipDeviceAttributeConcurrentKernels, ///< Device can possibly execute multiple kernels concurrently.
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hipDeviceAttributeConcurrentManagedAccess, ///< Device can coherently access managed memory concurrently with the CPU
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hipDeviceAttributeCooperativeLaunch, ///< Support cooperative launch
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hipDeviceAttributeCooperativeMultiDeviceLaunch, ///< Support cooperative launch on multiple devices
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hipDeviceAttributeDeviceOverlap, ///< Cuda only. Device can concurrently copy memory and execute a kernel.
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hipDeviceAttributeHostRegisterSupported, ///< Can device support host memory registration via hipHostRegister
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hipDeviceAttributeDeviceOverlap, ///< Device can concurrently copy memory and execute a kernel.
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///< Deprecated. Use instead asyncEngineCount.
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hipDeviceAttributeDirectManagedMemAccessFromHost, ///< Host can directly access managed memory on
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///< the device without migration
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hipDeviceAttributeGlobalL1CacheSupported, ///< Cuda only. Device supports caching globals in L1
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hipDeviceAttributeHostNativeAtomicSupported, ///< Cuda only. Link between the device and the host supports native atomic operations
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hipDeviceAttributeGlobalL1CacheSupported, ///< Device supports caching globals in L1
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hipDeviceAttributeHostNativeAtomicSupported, ///< Link between the device and the host supports native atomic operations
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hipDeviceAttributeIntegrated, ///< Device is integrated GPU
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hipDeviceAttributeIsMultiGpuBoard, ///< Multiple GPU devices.
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hipDeviceAttributeKernelExecTimeout, ///< Run time limit for kernels executed on the device
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hipDeviceAttributeL2CacheSize, ///< Size of L2 cache in bytes. 0 if the device doesn't have L2 cache.
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hipDeviceAttributeLocalL1CacheSupported, ///< caching locals in L1 is supported
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hipDeviceAttributeLuid, ///< Cuda only. 8-byte locally unique identifier in 8 bytes. Undefined on TCC and non-Windows platforms
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hipDeviceAttributeLuidDeviceNodeMask, ///< Cuda only. Luid device node mask. Undefined on TCC and non-Windows platforms
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hipDeviceAttributeLuid, ///< 8-byte locally unique identifier in 8 bytes. Undefined on TCC and non-Windows platforms
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hipDeviceAttributeLuidDeviceNodeMask, ///< Luid device node mask. Undefined on TCC and non-Windows platforms
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hipDeviceAttributeComputeCapabilityMajor, ///< Major compute capability version number.
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hipDeviceAttributeManagedMemory, ///< Device supports allocating managed memory on this system
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hipDeviceAttributeMaxBlocksPerMultiProcessor, ///< Cuda only. Max block size per multiprocessor
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hipDeviceAttributeMaxBlocksPerMultiProcessor, ///< Max block size per multiprocessor
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hipDeviceAttributeMaxBlockDimX, ///< Max block size in width.
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hipDeviceAttributeMaxBlockDimY, ///< Max block size in height.
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hipDeviceAttributeMaxBlockDimZ, ///< Max block size in depth.
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@@ -382,22 +457,22 @@ typedef enum hipDeviceAttribute_t {
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hipDeviceAttributeMaxSurfaceCubemap, ///< Cuda only. Maximum dimensions of Cubemap surface.
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hipDeviceAttributeMaxSurfaceCubemapLayered, ///< Cuda only. Maximum dimension of Cubemap layered surface.
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hipDeviceAttributeMaxTexture1DWidth, ///< Maximum size of 1D texture.
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hipDeviceAttributeMaxTexture1DLayered, ///< Cuda only. Maximum dimensions of 1D layered texture.
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hipDeviceAttributeMaxTexture1DLayered, ///< Maximum dimensions of 1D layered texture.
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hipDeviceAttributeMaxTexture1DLinear, ///< Maximum number of elements allocatable in a 1D linear texture.
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///< Use cudaDeviceGetTexture1DLinearMaxWidth() instead on Cuda.
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hipDeviceAttributeMaxTexture1DMipmap, ///< Cuda only. Maximum size of 1D mipmapped texture.
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hipDeviceAttributeMaxTexture1DMipmap, ///< Maximum size of 1D mipmapped texture.
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hipDeviceAttributeMaxTexture2DWidth, ///< Maximum dimension width of 2D texture.
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hipDeviceAttributeMaxTexture2DHeight, ///< Maximum dimension hight of 2D texture.
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hipDeviceAttributeMaxTexture2DGather, ///< Cuda only. Maximum dimensions of 2D texture if gather operations performed.
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hipDeviceAttributeMaxTexture2DLayered, ///< Cuda only. Maximum dimensions of 2D layered texture.
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hipDeviceAttributeMaxTexture2DLinear, ///< Cuda only. Maximum dimensions (width, height, pitch) of 2D textures bound to pitched memory.
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hipDeviceAttributeMaxTexture2DMipmap, ///< Cuda only. Maximum dimensions of 2D mipmapped texture.
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hipDeviceAttributeMaxTexture2DGather, ///< Maximum dimensions of 2D texture if gather operations performed.
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hipDeviceAttributeMaxTexture2DLayered, ///< Maximum dimensions of 2D layered texture.
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hipDeviceAttributeMaxTexture2DLinear, ///< Maximum dimensions (width, height, pitch) of 2D textures bound to pitched memory.
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hipDeviceAttributeMaxTexture2DMipmap, ///< Maximum dimensions of 2D mipmapped texture.
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hipDeviceAttributeMaxTexture3DWidth, ///< Maximum dimension width of 3D texture.
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hipDeviceAttributeMaxTexture3DHeight, ///< Maximum dimension height of 3D texture.
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hipDeviceAttributeMaxTexture3DDepth, ///< Maximum dimension depth of 3D texture.
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hipDeviceAttributeMaxTexture3DAlt, ///< Cuda only. Maximum dimensions of alternate 3D texture.
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hipDeviceAttributeMaxTextureCubemap, ///< Cuda only. Maximum dimensions of Cubemap texture
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hipDeviceAttributeMaxTextureCubemapLayered, ///< Cuda only. Maximum dimensions of Cubemap layered texture.
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hipDeviceAttributeMaxTexture3DAlt, ///< Maximum dimensions of alternate 3D texture.
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hipDeviceAttributeMaxTextureCubemap, ///< Maximum dimensions of Cubemap texture
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hipDeviceAttributeMaxTextureCubemapLayered, ///< Maximum dimensions of Cubemap layered texture.
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hipDeviceAttributeMaxThreadsDim, ///< Maximum dimension of a block
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hipDeviceAttributeMaxThreadsPerBlock, ///< Maximum number of threads per block.
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hipDeviceAttributeMaxThreadsPerMultiProcessor, ///< Maximum resident threads per multiprocessor.
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@@ -405,7 +480,7 @@ typedef enum hipDeviceAttribute_t {
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hipDeviceAttributeMemoryBusWidth, ///< Global memory bus width in bits.
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hipDeviceAttributeMemoryClockRate, ///< Peak memory clock frequency in kilohertz.
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hipDeviceAttributeComputeCapabilityMinor, ///< Minor compute capability version number.
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hipDeviceAttributeMultiGpuBoardGroupID, ///< Cuda only. Unique ID of device group on the same multi-GPU board
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hipDeviceAttributeMultiGpuBoardGroupID, ///< Unique ID of device group on the same multi-GPU board
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hipDeviceAttributeMultiprocessorCount, ///< Number of multiprocessors on the device.
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hipDeviceAttributeUnused1, ///< Previously hipDeviceAttributeName
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hipDeviceAttributePageableMemoryAccess, ///< Device supports coherently accessing pageable memory
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@@ -414,17 +489,17 @@ typedef enum hipDeviceAttribute_t {
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hipDeviceAttributePciBusId, ///< PCI Bus ID.
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hipDeviceAttributePciDeviceId, ///< PCI Device ID.
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hipDeviceAttributePciDomainID, ///< PCI Domain ID.
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hipDeviceAttributePersistingL2CacheMaxSize, ///< Cuda11 only. Maximum l2 persisting lines capacity in bytes
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hipDeviceAttributePersistingL2CacheMaxSize, ///< Maximum l2 persisting lines capacity in bytes
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hipDeviceAttributeMaxRegistersPerBlock, ///< 32-bit registers available to a thread block. This number is shared
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///< by all thread blocks simultaneously resident on a multiprocessor.
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hipDeviceAttributeMaxRegistersPerMultiprocessor, ///< 32-bit registers available per block.
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hipDeviceAttributeReservedSharedMemPerBlock, ///< Cuda11 only. Shared memory reserved by CUDA driver per block.
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hipDeviceAttributeReservedSharedMemPerBlock, ///< Shared memory reserved by CUDA driver per block.
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hipDeviceAttributeMaxSharedMemoryPerBlock, ///< Maximum shared memory available per block in bytes.
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hipDeviceAttributeSharedMemPerBlockOptin, ///< Cuda only. Maximum shared memory per block usable by special opt in.
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hipDeviceAttributeSharedMemPerMultiprocessor, ///< Cuda only. Shared memory available per multiprocessor.
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hipDeviceAttributeSharedMemPerBlockOptin, ///< Maximum shared memory per block usable by special opt in.
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hipDeviceAttributeSharedMemPerMultiprocessor, ///< Shared memory available per multiprocessor.
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hipDeviceAttributeSingleToDoublePrecisionPerfRatio, ///< Cuda only. Performance ratio of single precision to double precision.
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hipDeviceAttributeStreamPrioritiesSupported, ///< Cuda only. Whether to support stream priorities.
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hipDeviceAttributeSurfaceAlignment, ///< Cuda only. Alignment requirement for surfaces
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hipDeviceAttributeStreamPrioritiesSupported, ///< Whether to support stream priorities.
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hipDeviceAttributeSurfaceAlignment, ///< Alignment requirement for surfaces
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hipDeviceAttributeTccDriver, ///< Cuda only. Whether device is a Tesla device using TCC driver
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hipDeviceAttributeTextureAlignment, ///< Alignment requirement for textures
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hipDeviceAttributeTexturePitchAlignment, ///< Pitch alignment requirement for 2D texture references bound to pitched memory;
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@@ -435,7 +510,6 @@ typedef enum hipDeviceAttribute_t {
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hipDeviceAttributeWarpSize, ///< Warp size in threads.
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hipDeviceAttributeMemoryPoolsSupported, ///< Device supports HIP Stream Ordered Memory Allocator
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hipDeviceAttributeVirtualMemoryManagementSupported, ///< Device supports HIP virtual memory management
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hipDeviceAttributeHostRegisterSupported, ///< Host memory registeration through device support
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||||
hipDeviceAttributeCudaCompatibleEnd = 9999,
|
||||
hipDeviceAttributeAmdSpecificBegin = 10000,
|
||||
@@ -477,7 +551,18 @@ enum hipComputeMode {
|
||||
hipComputeModeExclusiveProcess = 3
|
||||
};
|
||||
|
||||
#if (defined(__HIP_PLATFORM_HCC__) || defined(__HIP_PLATFORM_AMD__)) && !(defined(__HIP_PLATFORM_NVCC__) || defined(__HIP_PLATFORM_NVIDIA__))
|
||||
enum hipFlushGPUDirectRDMAWritesOptions {
|
||||
hipFlushGPUDirectRDMAWritesOptionHost = 1 << 0,
|
||||
hipFlushGPUDirectRDMAWritesOptionMemOps = 1 << 1
|
||||
};
|
||||
|
||||
enum hipGPUDirectRDMAWritesOrdering {
|
||||
hipGPUDirectRDMAWritesOrderingNone = 0,
|
||||
hipGPUDirectRDMAWritesOrderingOwner = 100,
|
||||
hipGPUDirectRDMAWritesOrderingAllDevices = 200
|
||||
};
|
||||
|
||||
#if defined(__HIP_PLATFORM_AMD__) && !defined(__HIP_PLATFORM_NVIDIA__)
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stddef.h>
|
||||
|
||||
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