SWDEV-436533 [CLI/Python API] Align Cache Info BM UI to Host

- [CLI] Refactored cache info to display
cache flags as "cache_properties" names.
Names are displayed as a list of comma-separated
cache type strings. Previously, values
were shown one by one as ENABLED.

ex.
CACHE_PROPERTIES = <a,b,c>

- [JSON] mirrors CLI fields.
No longer display "cache_flags", renamed
field as "cache_properties" dictionary. This
allows users to better understand the
list of names provided.

- [Python API] Updated amdsmi_get_gpu_cache_info
to mirror Host return.

README.md - updated to reflect all changes.

Change-Id: Ife2ef5adcef30058937d1376efb01749e45c02fb
Signed-off-by: Charis Poag <Charis.Poag@amd.com>
This commit is contained in:
Charis Poag authored and Maisam Arif committed 2024-01-24 06:21:55 -05:00
1 parent c260819003
commit fe86afed8c
4 files changed
+87 -73

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+41 -52
View File
@@ -657,33 +657,30 @@ VRAM:
VRAM_SIZE_MB: 96432 MB
CACHE:
CACHE 0:
CACHE_PROPERTIES: DATA_CACHE, SIMD_CACHE
CACHE_SIZE: 32 KB
CACHE_LEVEL: 1
MAX_NUM_CU_SHARED: 2
NUM_CACHE_INSTANCE: 348
DATA_CACHE: ENABLED
SIMD_CACHE: ENABLED
NUM_CACHE_INSTANCE: 464
CACHE 1:
CACHE_PROPERTIES: INST_CACHE, SIMD_CACHE
CACHE_SIZE: 64 KB
CACHE_LEVEL: 1
MAX_NUM_CU_SHARED: 2
NUM_CACHE_INSTANCE: 120
INST_CACHE: ENABLED
SIMD_CACHE: ENABLED
NUM_CACHE_INSTANCE: 160
CACHE 2:
CACHE_SIZE: 24576 KB
CACHE_PROPERTIES: DATA_CACHE, SIMD_CACHE
CACHE_SIZE: 32768 KB
CACHE_LEVEL: 2
MAX_NUM_CU_SHARED: 228
MAX_NUM_CU_SHARED: 304
NUM_CACHE_INSTANCE: 1
DATA_CACHE: ENABLED
SIMD_CACHE: ENABLED
CACHE 3:
CACHE_PROPERTIES: DATA_CACHE, SIMD_CACHE
CACHE_SIZE: 262144 KB
CACHE_LEVEL: 3
MAX_NUM_CU_SHARED: 228
MAX_NUM_CU_SHARED: 304
NUM_CACHE_INSTANCE: 1
DATA_CACHE: ENABLED
SIMD_CACHE: ENABLED
RAS:
EEPROM_VERSION: 0x0
PARITY_SCHEMA: DISABLED
@@ -770,34 +767,31 @@ VRAM:
VRAM_VENDOR: HYNIX
VRAM_SIZE_MB: 96432 MB
CACHE:
CACHE:
CACHE 0:
CACHE_PROPERTIES: DATA_CACHE, SIMD_CACHE
CACHE_SIZE: 32 KB
CACHE_LEVEL: 1
MAX_NUM_CU_SHARED: 2
NUM_CACHE_INSTANCE: 348
DATA_CACHE: ENABLED
SIMD_CACHE: ENABLED
NUM_CACHE_INSTANCE: 464
CACHE 1:
CACHE_PROPERTIES: INST_CACHE, SIMD_CACHE
CACHE_SIZE: 64 KB
CACHE_LEVEL: 1
MAX_NUM_CU_SHARED: 2
NUM_CACHE_INSTANCE: 120
INST_CACHE: ENABLED
SIMD_CACHE: ENABLED
NUM_CACHE_INSTANCE: 160
CACHE 2:
CACHE_SIZE: 24576 KB
CACHE_PROPERTIES: DATA_CACHE, SIMD_CACHE
CACHE_SIZE: 32768 KB
CACHE_LEVEL: 2
MAX_NUM_CU_SHARED: 228
MAX_NUM_CU_SHARED: 304
NUM_CACHE_INSTANCE: 1
DATA_CACHE: ENABLED
SIMD_CACHE: ENABLED
CACHE 3:
CACHE_PROPERTIES: DATA_CACHE, SIMD_CACHE
CACHE_SIZE: 262144 KB
CACHE_LEVEL: 3
MAX_NUM_CU_SHARED: 228
MAX_NUM_CU_SHARED: 304
NUM_CACHE_INSTANCE: 1
DATA_CACHE: ENABLED
SIMD_CACHE: ENABLED
RAS:
EEPROM_VERSION: 0x0
PARITY_SCHEMA: DISABLED
@@ -884,34 +878,31 @@ VRAM:
VRAM_VENDOR: HYNIX
VRAM_SIZE_MB: 96432 MB
CACHE:
CACHE:
CACHE 0:
CACHE_PROPERTIES: DATA_CACHE, SIMD_CACHE
CACHE_SIZE: 32 KB
CACHE_LEVEL: 1
MAX_NUM_CU_SHARED: 2
NUM_CACHE_INSTANCE: 348
DATA_CACHE: ENABLED
SIMD_CACHE: ENABLED
NUM_CACHE_INSTANCE: 464
CACHE 1:
CACHE_PROPERTIES: INST_CACHE, SIMD_CACHE
CACHE_SIZE: 64 KB
CACHE_LEVEL: 1
MAX_NUM_CU_SHARED: 2
NUM_CACHE_INSTANCE: 120
INST_CACHE: ENABLED
SIMD_CACHE: ENABLED
NUM_CACHE_INSTANCE: 160
CACHE 2:
CACHE_SIZE: 24576 KB
CACHE_PROPERTIES: DATA_CACHE, SIMD_CACHE
CACHE_SIZE: 32768 KB
CACHE_LEVEL: 2
MAX_NUM_CU_SHARED: 228
MAX_NUM_CU_SHARED: 304
NUM_CACHE_INSTANCE: 1
DATA_CACHE: ENABLED
SIMD_CACHE: ENABLED
CACHE 3:
CACHE_PROPERTIES: INST_CACHE, SIMD_CACHE
CACHE_SIZE: 262144 KB
CACHE_LEVEL: 3
MAX_NUM_CU_SHARED: 228
MAX_NUM_CU_SHARED: 304
NUM_CACHE_INSTANCE: 1
DATA_CACHE: ENABLED
SIMD_CACHE: ENABLED
RAS:
EEPROM_VERSION: 0x0
PARITY_SCHEMA: DISABLED
@@ -999,33 +990,31 @@ VRAM:
VRAM_SIZE_MB: 96432 MB
CACHE:
CACHE 0:
CACHE:
CACHE 0:
CACHE_PROPERTIES: INST_CACHE, SIMD_CACHE
CACHE_SIZE: 32 KB
CACHE_LEVEL: 1
MAX_NUM_CU_SHARED: 2
NUM_CACHE_INSTANCE: 348
DATA_CACHE: ENABLED
SIMD_CACHE: ENABLED
NUM_CACHE_INSTANCE: 464
CACHE 1:
CACHE_PROPERTIES: INST_CACHE, SIMD_CACHE
CACHE_SIZE: 64 KB
CACHE_LEVEL: 1
MAX_NUM_CU_SHARED: 2
NUM_CACHE_INSTANCE: 120
INST_CACHE: ENABLED
SIMD_CACHE: ENABLED
NUM_CACHE_INSTANCE: 160
CACHE 2:
CACHE_SIZE: 24576 KB
CACHE_PROPERTIES: DATA_CACHE, SIMD_CACHE
CACHE_SIZE: 32768 KB
CACHE_LEVEL: 2
MAX_NUM_CU_SHARED: 228
MAX_NUM_CU_SHARED: 304
NUM_CACHE_INSTANCE: 1
DATA_CACHE: ENABLED
SIMD_CACHE: ENABLED
CACHE 3:
CACHE_PROPERTIES: DATA_CACHE, SIMD_CACHE
CACHE_SIZE: 262144 KB
CACHE_LEVEL: 3
MAX_NUM_CU_SHARED: 228
MAX_NUM_CU_SHARED: 304
NUM_CACHE_INSTANCE: 1
DATA_CACHE: ENABLED
SIMD_CACHE: ENABLED
RAS:
EEPROM_VERSION: 0x0
PARITY_SCHEMA: DISABLED
+18 -8
View File
@@ -559,16 +559,26 @@ class AMDSMICommands():
if args.cache:
try:
cache_info = amdsmi_interface.amdsmi_get_gpu_cache_info(args.gpu)
for cache_key, cache_dict in cache_info.items():
for key, value in cache_dict.items():
if key == 'cache_size' or key == 'cache_level' or \
key == 'max_num_cu_shared' or key == 'num_cache_instance':
continue
if value:
cache_info[cache_key][key] = "ENABLED"
logging.debug("Before dictionary modify | cache_info = " + str(cache_info))
for key, cache_values in cache_info.items():
cache_properties = "N/A"
if 'cache_flags' in list(cache_info[key].keys()):
if isinstance(cache_values['cache_flags'], list):
cache_properties = list(cache_values['cache_flags'])
cache_values.pop('cache_flags') # remove cache_flags from output
cache_info[key] = { # add properties to top of key's dictionary
'cache_properties': list(cache_properties),
**cache_info[key] # append remaining key's dictionary
}
logging.debug("After dictionary modify | cache_info = " + str(cache_info))
if self.logger.is_human_readable_format():
for _ , cache_values in cache_info.items():
for key, cache_values in cache_info.items():
cache_values['cache_size'] = f"{cache_values['cache_size']} KB"
# take cache_properties out of list -> display as string, removing brackets
update_cache_properties = str(cache_values['cache_properties'])
update_cache_properties = update_cache_properties.replace("[","").replace("]", "")
cache_values['cache_properties'] = update_cache_properties
logging.debug("After human_readable | cache_info = " + str(cache_info))
except amdsmi_exception.AmdSmiLibraryException as e:
cache_info = "N/A"