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Συγγραφέας SHA1 Μήνυμα Ημερομηνία
Danylo Lytovchenko f7338717ae SWDEV-470698 - fix formatting, add format check workflow (#657) 2025-08-20 19:58:06 +05:30
Jatin Jaikishan Chaudhary 8b1d0cff83 Revert "SWDEV-505971 - change setArgument arg from uint32_t to uint64_t" 
This reverts commit 0830d95f6d.

Reason for revert: There needs to be memcpy size change

Change-Id: If4f51769731e54743ac705b19b4f81b2d5925d5a


[ROCm/clr commit: 446ed661a0]
 2025-01-06 18:03:23 -05:00
Jatin Chaudhary 0830d95f6d SWDEV-505971 - change setArgument arg from uint32_t to uint64_t 
We are passing this arg as an address, and memcpy complains about
overreading (8 bytes instead of 4).

Change-Id: Ica9207f6c5f6056a4bfc968280c76e779ded13ae


[ROCm/clr commit: a6f2a2c2af]
 2025-01-06 08:16:59 -05:00
Sourabh Betigeri 7261404002 SWDEV-440866 - [hip-roclr] Adds support to batch memory operations APIs 
Change-Id: I5ac63a6626af8c2b4ac382c52dfe1aaf0b3716b8


[ROCm/clr commit: 03dbcd8ca7]
 2024-12-12 19:29:24 -05:00
Sourabh Betigeri 1712acdd2e Revert "SWDEV-440866 - [hip-roclr] Adds support to batch memory operations APIs" 
This reverts commit ab0ff9163d.

Reason for revert: hipInfo fails on windows. Updating llvm amd-mainline-closed

Change-Id: I57e1fa1945188b0bc0a799c4f3d540f2b7713003


[ROCm/clr commit: 2ca644cf22]
 2024-12-02 16:46:12 -05:00
Sourabh Betigeri ab0ff9163d SWDEV-440866 - [hip-roclr] Adds support to batch memory operations APIs 
Change-Id: I449ffca44bbb04d13348d112e896d603c70fd485


[ROCm/clr commit: bd5d8e9baf]
 2024-11-30 17:54:32 -05:00
Ioannis Assiouras 407d1346f2 SWDEV-463865 - changed device,roc and pal namespaces to be nested under amd 
Change-Id: Icad342843c039c634e249a13a7aa31400730b1dd


[ROCm/clr commit: 775dc204aa]
 2024-06-07 12:23:06 -04:00
Sourabh Betigeri da8bb9780e Revert "SWDEV-301667 - Disable HostBlit copy for HIP" 
This reverts commit 96e25898c8.

Reason for revert: SWDEV-455075, SWDEV-461507 - This change forces to
use ROCr's copy path. Reintroducing hostBlit copy path for
host-to-host copies.


Change-Id: Ic3c45b49e481c9dcdaa7611f61071778790b7e6c


[ROCm/clr commit: a9f05e22db]
 2024-05-28 06:31:10 +00:00
German Andryeyev e390ec044f SWDEV-432174 - Change the fillBuffer kernel 
- Add the new fillBuffer kernel, which allows to launch a limited
number of workgroups for memory fill operation
- Switch fill memory to 16 bytes write by default
- Allow to limit the workgroups with DEBUG_CLR_LIMIT_BLIT_WG

Change-Id: Ibad1822f2d42b2fc71bcfc1917c31409c0623e8e


[ROCm/clr commit: f1dc81f427]
 2023-11-16 14:25:55 -04:00
Saleel Kudchadker 96e25898c8 SWDEV-301667 - Disable HostBlit copy for HIP 
Change-Id: I46333ff42e8c1d402ece97e3ead7b539a27c3f82


[ROCm/clr commit: 5447cf8872]
 2023-07-17 17:49:11 -04:00
Anusha GodavarthySurya 379781ea65 SWDEV-364576 - initialize device malloc heap state using blit kernel 
Change-Id: I5d0172aff7d2c04b322a4d828b8a2b438158b80f


[ROCm/clr commit: 274f2de391]
 2023-01-07 06:53:53 +00:00
Ioannis Assiouras 733c8d1d1c SWDEV-369581 - Convey copy API metadata to ROCclr 
Change-Id: I569462d6d268700d419510255e201bf7d80d6714


[ROCm/clr commit: 72b45e2a1f]
 2022-12-09 00:27:15 -05:00
Ajay c2a7fe7bd6 SWDEV-347670 - GPU StreamWait and StreamWrite support in Windows PAL backend 
Change-Id: Ic4881305b6332e217f3d3127dce7e9d9d0a7df11


[ROCm/clr commit: 373a7d1195]
 2022-09-15 13:57:40 -04:00
German Andryeyev 0ecf22bb53 SWDEV-336024 - Clear device heap to 0 
This reverts commit 8624574866.

Reason for revert: Fix regressions

Change-Id: I7d883e1c3cbd27bb64b581ec800243ad7dfe24fd


[ROCm/clr commit: 07c1b9a998]
 2022-05-19 09:10:08 -04:00
German Andryeyev 8624574866 SWDEV-336024 - Clear device heap to 0 
The heap must be cleared once per device, but ROCclr doesn't
create a queue per device in HIP. Hence, the clear operation will
be performed during the first queue creation.

Change-Id: I52ceb06d67d11cde6d019c5ab510059f426a9bfb


[ROCm/clr commit: 04bfd93569]
 2022-05-11 11:03:56 -04:00
kjayapra-amd 31c0525344 SWDEV-305527 - Changes to handle memset blit kernel that takes width, height and depth. This also fixes SWDEV-317261. 
Change-Id: Ic85f63a95d9d8f48884fc8c7fd95cbb496dfbbca


[ROCm/clr commit: 7fb80a027a]
 2022-03-31 09:02:33 -04:00
kjayapra-amd f74515778c SWDEV-312822 - Revert "SWDEV-310187 - Change flag to keep track of aligned sizes instead of expanded patterns." 
This reverts commit 7220267211.

Change-Id: I022c2a8375f9929e9723cec66e1e0b960263fc39


[ROCm/clr commit: 2e9bc8f793]
 2021-11-28 23:39:40 -05:00
kjayapra-amd 7220267211 SWDEV-310187 - Change flag to keep track of aligned sizes instead of expanded patterns. 
Change-Id: I763feda8688bb1b7b11033a2a8cba0f69f07167d


[ROCm/clr commit: 8307886644]
 2021-11-19 10:32:40 -05:00
kjayapra-amd 9f68891f68 SWDEV-232903 - Change pattern64 to uint64_t from size_t to handle 32 bit machines. 
Change-Id: I423cd14d145556544563027931562d7b8bf9442d


[ROCm/clr commit: 4c8b32b13c]
 2021-10-18 14:31:09 -04:00
kjayapra-amd 6f62f832cb SWDEV-232903 - Move hipmemset Dword optimization to ROCclr. 
Change-Id: I3eae61720cbc6364f1aaac4865bfd8b6ded08097


[ROCm/clr commit: 88ed58735d]
 2021-10-13 11:32:15 -04:00
agunashe 49f0546637 SWDEV-293742 - Update copyright end year VDI repo 
Change-Id: I69d2fea4a7a43adf96ccea794270e4af991c5261


[ROCm/clr commit: d96481fb36]
 2021-08-22 23:56:07 -07:00
Ravi C Akkenapally 6629930067 SWDEV-179105 - Stream Operations: Add support for Wait and Write 
Change-Id: Ibffa1d6d573826b64763da280074a77271d66808


[ROCm/clr commit: 0a5f9a3b10]
 2021-02-15 17:02:38 -08:00
Laurent Morichetti b3297f189d Replace cl_* integral types with standard types. 
cl_bool -> bool
cl_int -> int32_t
cl_uint -> uint32_t
cl_long -> int64_t
cl_ulong -> uint64_t
cl_float -> float
cl_double -> double
cl_bitfield -> uint64_t

Change-Id: I840c8993b55f98f5b745d21e27f5f28233647a58


[ROCm/clr commit: d9d9c69399]
 2020-02-12 13:16:06 -08:00
Laurent Morichetti e284923583 Update copyright info 
Change-Id: Ia4f9ff0f5f873b4223a8cca154188bb0d2f1abba


[ROCm/clr commit: b4c6143a2f]
 2020-02-04 09:26:14 -08:00
Laurent Morichetti 011f3e945b Merge branch 'origin/pghafari/vdi-prototype' into lmoriche/amd-master 
Change-Id: Id3b833d405596735becb3346f3b08c6da57033fe


[ROCm/clr commit: 20c7173849]
 2020-01-30 20:12:13 -08:00