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18 Commits

Autor SHA1 Mensaje Fecha
Karthik Jayaprakash 740a06d567 SWDEV-559267 - Use CLPrint to DevLogPrintf with Log Level - detail debug. (#1160) 2025-11-25 19:25:32 -05:00
Ioannis Assiouras 4f91b68988 SWDEV-559166 - Remove obsolete member execInfoOffset from KernelParameters (#1790) 2025-11-12 17:20:36 +00:00
Ioannis Assiouras 6d6b136374 SWDEV-559166 - Fix data races in GetSubmissionBatch, CaptureAndSet and SetQueueStatus (#1441) 2025-10-23 12:18:31 +01:00
Danylo Lytovchenko 2ff2316227 Adjust clang format to the new versions, revert broken macro layout (#714) 2025-08-22 17:23:22 +02:00
Danylo Lytovchenko f7338717ae SWDEV-470698 - fix formatting, add format check workflow (#657) 2025-08-20 19:58:06 +05:30
Betigeri, Sourabh 40999496c1 SWDEV-545273 - Respect HIP_LAUNCH_PARAM_BUFFER_SIZE (#770) 
[ROCm/clr commit: 2a02d2c2f3]
 2025-08-03 17:32:52 -07:00
Zhang, Victor fbabd2b69d SWDEV-528142 - add error check for KernelParameters::capture (#276) 
* SWDEV-528142 - add error check for KernelParameters::capture

* Update kernel.cpp

---------

Co-authored-by: victzhan <victzhan@amd.com>

[ROCm/clr commit: f960433dcd]
 2025-05-07 09:52:09 -04:00
kjayapra-amd 41cb6dadf9 SWDEV-460948 - Changes to alloc, set, capture under single function. 
Change-Id: I7b2d40e99e812b97c53535c5e63c41ad64a8f543


[ROCm/clr commit: 892071aeb2]
 2024-06-06 16:57:53 -04:00
Ioannis Assiouras 1ad1fccdfa SWDEV-385050 - Fixed possible invalid queue access from kernelCommand::releaseResources 
Change-Id: I7c5d99987cb7ab4fa0aa634f2bb6a4d60331b3af


[ROCm/clr commit: 2e9f6fb49b]
 2023-02-23 16:39:27 +00:00
German Andryeyev 7821cddb3e SWDEV-257789 - Initial change to skip kernel arg copy 
The optimization is controlled with ROCR_SKIP_KERNEL_ARG_COPY.
This is initial check-in for experiments. Extra changes are
necessary for full support:
- handle graph capture with the original sysmem alloc
- avoid memobject references, otherwise there is a race condition with
reusage of the arg buffer
- Remove arg setup from hip

Change-Id: Ib0af710f93e79834711fa4049a7c66093711e68b


[ROCm/clr commit: 7e12cf6318]
 2021-10-28 20:35:35 -04:00
jujiang 7c7a6ee346 SWDEV-286322 - clean up trailing white space 
Change-Id: I01f3a559cbd1835aa2fdad7abe2bd685d90fc6a8


[ROCm/clr commit: f63115cec6]
 2021-09-01 11:45:47 -04:00
agunashe 49f0546637 SWDEV-293742 - Update copyright end year VDI repo 
Change-Id: I69d2fea4a7a43adf96ccea794270e4af991c5261


[ROCm/clr commit: d96481fb36]
 2021-08-22 23:56:07 -07:00
agodavar b1eb35e730 SWDEV-245381 : Updated guarantee error messages to print based on BUILD_TYPE 
Change-Id: Ia21039326b440f6d807a6495a9a05dd52b384c76


[ROCm/clr commit: 69a786e8d1]
 2021-01-05 05:49:09 -05:00
Michael LIAO b785d25506 Clear executable permission. 
Change-Id: Ia0d363b1ba89d7947e5b5a55cb67edba86f0515e


[ROCm/clr commit: 503ef06555]
 2020-05-07 10:38:58 -04:00
kjayapra-amd 236705c62f SWDEV-229840 - Improve error messages on ROCCLR Layer. 
Change-Id: Iab7d9156cdc206db86385aa05023a0095ed40f92


[ROCm/clr commit: 7458bf9964]
 2020-04-19 20:01:49 -04:00
Laurent Morichetti b3297f189d Replace cl_* integral types with standard types. 
cl_bool -> bool
cl_int -> int32_t
cl_uint -> uint32_t
cl_long -> int64_t
cl_ulong -> uint64_t
cl_float -> float
cl_double -> double
cl_bitfield -> uint64_t

Change-Id: I840c8993b55f98f5b745d21e27f5f28233647a58


[ROCm/clr commit: d9d9c69399]
 2020-02-12 13:16:06 -08:00
Laurent Morichetti e284923583 Update copyright info 
Change-Id: Ia4f9ff0f5f873b4223a8cca154188bb0d2f1abba


[ROCm/clr commit: b4c6143a2f]
 2020-02-04 09:26:14 -08:00
Laurent Morichetti 011f3e945b Merge branch 'origin/pghafari/vdi-prototype' into lmoriche/amd-master 
Change-Id: Id3b833d405596735becb3346f3b08c6da57033fe


[ROCm/clr commit: 20c7173849]
 2020-01-30 20:12:13 -08:00