17 Коммитов

Автор SHA1 Сообщение Дата
Tao Sang 163e44d0a8 SWDEV-555889 - Support mipmap on rocr (#2082)
* SWDEV-555889 - Support mipmap on rocr

Support mipmap in hip-rt on rocr backend.
Enable all mipmap tests in Windows.
Some other minor improvement.

Add some SRD logs that will be removed finally.

* Add sampler.mipFilter to fix sampler issues on mipmap in rocr.
Fix format issues of view of leveled image and  mipmap image in blit kernel in rocr.
Enabled disabled mipmap tests.

* Rewrite view logic

* Set word4.f.PITCH = 0 for mipmap SRD on navi31 to fix unstable test issues.
Reset last error in nagative tests.

* Remove SRD dump log from hip-rt
Let Rocr mipmap log be in condition.

* minor format chang

* Exclude mipmap tests for mi200+ which don't support mipmap.
2026-01-21 09:10:29 -08:00
Apurv Mishra be375c2dbf rocr: Add support for Mipmapped Array (#1847)
SWDEV-539526 - Add support for Mipmapped Array in Rocr

Add support for Mipmapped Array functionality in Rocr Runtimeenabling GPU applications to work with multi-level texture mipmaps. The implementation introduces new public APIs for creating, querying, and managing mipmapped arrays across different GPU architectures.

Signed-off-by: Apurv Mishra <Apurv.Mishra@amd.com>
Co-authored-by: Shweta Khatri <shweta.khatri@amd.com>
Co-authored-by: taosang2 <tao.sang@amd.com>
2026-01-08 17:14:39 -06:00
Mario Limonciello bc5d48e76c Run pre-commit's whitespace related hooks on projects/rocr-runtime (#2130)
* Run pre-commit's whitespace related hooks on projects/rocr-runtime

In order for pre-commit to be useful, everything needs to meet a common
baseline.

Signed-off-by: Mario Limonciello (AMD) <superm1@kernel.org>

* Add missing semicolon which would block compilation on big endian CPUs

Signed-off-by: Mario Limonciello (AMD) <superm1@kernel.org>

---------

Signed-off-by: Mario Limonciello (AMD) <superm1@kernel.org>
2025-12-08 07:56:50 -06:00
MachineTom 3b1c0c3464 SWDEV-558845 - Support image in rocr on Windows (#1582)
Enable image build in Windows.
Remove some useless codes that fail building in Windows.
Some minor improvement.
Temporarily exclude mipmap test files.
Prevent negative tests affect some tests.
Move some catch info log codes into failed cases.
2025-11-05 09:33:41 -05:00
Khatri, Shweta 9816c2ecd3 rocr: GFX9, GFX10, GFX11: Use view3dAs2dArray flag, for thick/3D swizzle modes. (#58)
A HSA_IMAGE_ENABLE_3D_SWIZZLE_DEBUG environment flag exists already to
enable/disable this. Default value is false (view3dAs2dArray = 1)
Enabling this flag will enable support for swizzles that do 3D
interleaving on GFX9, GF10 and GFX11. By default support for swizzles that
do 3D interleaving is disabled.

[ROCm/ROCR-Runtime commit: 0984a1f0fd]
2025-02-26 09:38:17 -05:00
taosang2 a5de0f048d rocr: Support different address modes
Support different address modes in X, Y, Z directions

Change-Id: If1db5a8af33c92ddc4b48968c3d8eceb97daea6a


[ROCm/ROCR-Runtime commit: df250a49a5]
2024-12-02 09:07:56 -05:00
David Yat Sin 590cac0321 Fix clang compile warnings
Change-Id: Iea9afc3d998a6c5db28af6c7b54939960b11ae95


[ROCm/ROCR-Runtime commit: 3ee6c9b0e2]
2023-09-07 12:00:02 -04:00
Shweta Khatri 811c411e78 Fixed GFX11 Texture, Buffer and Sampler Resource Descriptor definitions
Change-Id: I101806f9f91ec2ad78339dabc98375bd09946dd0


[ROCm/ROCR-Runtime commit: e72329ab76]
2023-01-05 15:40:47 -05:00
David Yat Sin 2affd1a1f6 Fix compile warnings and remove unused variables
Change-Id: I7acaee5e9cf218b358ffaf0e3af6067faf6f3d2a


[ROCm/ROCR-Runtime commit: 9cb10a3dd8]
2022-10-06 10:11:17 -04:00
David Yat Sin 51a3a22e4b Fix image LUT for gfx11
For gfx11 the image type table has some different values compared to
previous asic families (e.g TYPE_SRGB). Creating a new LUT class to
use these new values.

Change-Id: Ifdfc6cd29bfd5f4ec2643c848fcb9986eb874f9e


[ROCm/ROCR-Runtime commit: 117495fe88]
2022-08-04 11:23:28 -04:00
Sean Keely c96272841b Adjust include paths for new header locations.
Thunk and rocm_smi_lib paths have been updated.

Change-Id: If2948172f8064dd992cbccbc2a80f9161ad4d457


[ROCm/ROCR-Runtime commit: 752cfd5ffd]
2022-05-09 14:44:32 -04:00
Sean Keely abd712f33f Update copyright date.
Change-Id: If4bf4c20cf051878bfe759080bb7345d884dd53d


[ROCm/ROCR-Runtime commit: ce19721c88]
2020-06-19 22:34:01 -04:00
Ramesh Errabolu ab6b820dbf Update License header and Cleanup IP references
Change-Id: I0a6636e1d8457045d034d05383cfb5d4e7680fee


[ROCm/ROCR-Runtime commit: 42b38daa22]
2020-06-19 22:33:36 -04:00
Ramesh Errabolu c9f453a8a8 Build ROCr core and image libraries as one shared object
Change-Id: I3a16c1227e7db2e386ab33886965596fa0fb0c87


[ROCm/ROCR-Runtime commit: 0ca0691ca7]
2020-06-19 22:33:36 -04:00
Sean Keely 31268c6f4d Allow linear swizzle mode with tiled image requests.
Mesa address lib faults if the only acceptable swizzle modes are
forbidden.  The old address lib simply ignored the forbidden list
in this case.  Mesa addrlib will not select linear unless there
is no other option so allowing linear mode for tiled images will
still use tiled modes when possible.

Change-Id: I1aa44d072db902c968484dbff67b482af03b45d9


[ROCm/ROCR-Runtime commit: c60364e1e0]
2020-05-11 23:34:44 -04:00
Sean Keely 2269234579 Remove dead code from image_manager_xx.cpp
Image swizzle mode will be set by the preferred surface info
function.

Change-Id: I41e639be53cafbb4db6cf15c159aa2bd457ec5be


[ROCm/ROCR-Runtime commit: 1440da3e15]
2020-05-01 20:32:45 -04:00
Sean Keely 1fc7f2dec7 Move Images code to hsa-runtime folder
Change-Id: I53c1845d985ac3e9708d952865009c0021f3bb4f


[ROCm/ROCR-Runtime commit: 7e3db20826]
2020-04-30 19:35:57 -05:00