3115 Commits

Author SHA1 Message Date
David Yat Sin 52fc6e8619 PC Sampling: Convert timestamps to system time
Convert timestamps inside samples to system time

Change-Id: I5fad9a6887fa27c0ded9aa9b5f251cba2868f88f


[ROCm/ROCR-Runtime commit: 49e56ce782]
2024-04-11 12:53:37 -04:00
David Yat Sin a84d407118 PC Sampling: Implement lost sample count
Change-Id: Idfdfbac71c1813dd7a97c301619cf8ce83713c53


[ROCm/ROCR-Runtime commit: 547c9cb143]
2024-04-11 12:53:31 -04:00
David Yat Sin 3d13db3c39 PC Sampling: Implement flush
Flush is used by the client to retrieve data that are currently stored
in the buffers. This is used by the client to retrieve current data when
the buffers are not full.

Change-Id: Ib8304dcdfb2797cb060ec72df4970d95cf6be348


[ROCm/ROCR-Runtime commit: 8abbf9475b]
2024-04-11 12:53:24 -04:00
David Yat Sin b0d88f22dd PC Sampling: Push data to PC Sampling client
Each time there is enough data to fill the client session buffer,
callback the client data ready function to transfer the buffer contents
to the client.

Change-Id: Id79775426fa6d22e00dc2ef6f55c439eacb9b2af


[ROCm/ROCR-Runtime commit: 5177d17f5d]
2024-04-11 12:53:17 -04:00
David Yat Sin d8b7c22609 PC Sampling: Retrieve data from trap handler
Retrieve data from the buffers previously set in the 2nd level trap
handler TMA. We use a double buffering mechanism to allow the 2nd level
trap handler to write to one buffer while we are copying data from the
other.

Co-authored by: Joseph Greathouse <Joseph.Greathouse@amd.com>
Co-authored by: James Zhu <James.Zhu@amd.com>

Change-Id: I252c381ea06b8cf927c4f9af6ea59dedc3717fbb


[ROCm/ROCR-Runtime commit: 855e454671]
2024-04-11 12:53:12 -04:00
David Yat Sin b11294e555 PC Sampling: Update 2nd level trap handler
Update 2nd level trap handler when PC Sampling is enabled

Change-Id: I95bf2bca8057d2f8313923c7f012f033e12ccc3a


[ROCm/ROCR-Runtime commit: efdb72fd71]
2024-04-11 12:53:06 -04:00
David Yat Sin bb10ff65c2 PC Sampling: Allocate resources to retrieve data from trap handler
Allocate required device and host buffers to be able to interact with
the 2nd level trap handler.

Change-Id: If99de5aacf956ca57ecafc7b04b797be9c9decaa


[ROCm/ROCR-Runtime commit: 8d666dea01]
2024-04-11 12:53:00 -04:00
Joseph Greathouse 5c61936483 PC Sampling: Add gfx9 2nd trap handler for PC Sampling
Code is valid for gfx9 GPUs excluding gfx94x.

1st level trap handler will use TTMP13[22] to indicate host trap and
TTMP13[21] to indicate stochastic trap.

For each PC sampling method (hosttrap and stochastic), we use a double
buffering mechanism to transfer data between GPU and host.
The GPU will dump data into one buffer while CPU may be reading data
from the other buffer. There are 2 separate signals, one for each
buffer.
When signal != 0, the buffer belongs to the GPU and the GPU can write
to it. Once the buffer has reached the high watermark, the GPU will
set the signal to 0 to wake up the host and so that the host can try
to switch the buffers and read the data.

Co-authored-by: David Yat Sin <David.YatSin@amd.com>
Change-Id: If3eb0913e52fb4788059a71e5feca334612f3d5d


[ROCm/ROCR-Runtime commit: 431a70471e]
2024-04-11 12:52:54 -04:00
David Yat Sin c3f9368b8f PC Sampling: Create dedicated CP queue
Create dedicated CP queue with highest priority for PC Sampling. Reduce
the highest priority that LRT's can set for existing API so that PC
Sampling queue will always have highest priority over any other CP
queues

Change-Id: Ia70d74415edc83b4862a3e18dbdbd7cebe73ab47


[ROCm/ROCR-Runtime commit: a83f872a23]
2024-04-11 12:52:48 -04:00
David Yat Sin bcdecc7ff4 PC Sampling: Add start stop and flush APIs
Create PC Sampling APIs for start and stop functions. And create stub
for flush function.

Change-Id: I7a093b29dc87e34ac06faaae6cac2be50e4663e1


[ROCm/ROCR-Runtime commit: a842247482]
2024-04-11 12:52:42 -04:00
David Yat Sin 566e2c60fd PC Sampling: Add create and destroy APIs
Implement PC Sampling session create and destroy APIs.

Change-Id: I93370d3d01b74ee15e71b8b0e20feb8f0066a3dc

Signed-off-by: David Yat Sin <David.YatSin@amd.com>
Signed-off-by: Vladimir Indic <Vladimir.Indic@amd.com>
Change-Id: Ib0c64356a1a4616b12d5dbeebe16273fe2a84abe


[ROCm/ROCR-Runtime commit: 632f9e60f7]
2024-04-11 12:52:35 -04:00
David Yat Sin 0a4415f202 PC Sampling: API to list supported configurations
Add new PC Sampling API to list the supported PC Sampling methods and
options on a specific agent. If there is already a PC Sampling session
active on this agent, the list of methods returned will be reduced to
methods that can be run simultaneously with the current active session.

Change-Id: I42ac2b8f30d5c368faf8ed4cf37ca4134db22985


[ROCm/ROCR-Runtime commit: 295acf6b27]
2024-04-11 12:52:30 -04:00
David Yat Sin 8165c03e7b PC Sampling: Create PC Sampling interfaces
Create new interface group for PC Sampling

Change-Id: I59b4cfe9f8d1ae313dc28be1d2ed49f750d8212b


[ROCm/ROCR-Runtime commit: 0bc244e10a]
2024-04-11 12:52:23 -04:00
David Yat Sin b79e044711 PC Sampling: Update public headers for new APIs
Change-Id: Ib9987efdb41d5f6d203e7e86f9b26809d020e04e


[ROCm/ROCR-Runtime commit: 6a7122b183]
2024-04-11 12:52:16 -04:00
David Yat Sin bc77ec44f6 Create fine-grained allocator
Create allocator helper function to provide fine-grained memory on
a specific agent.

Change-Id: I32ba9aceb9c9dc708b140a0c45158e6e7a018844


[ROCm/ROCR-Runtime commit: 71f1a6726c]
2024-04-11 12:52:10 -04:00
David Yat Sin 6b38aecae9 Extend ExecutePM4() to accept completion signal and fences
ExecutePM4() function can optionally accept extra arguments for
acquire fence scope, release fence scope andcompletion signal. When
a completion signal is provided, ExecutePM4() does not wait for the
commands to complete.

Change-Id: Ib2a433b7bce1cb6260be8b76fe902335bd5dfada


[ROCm/ROCR-Runtime commit: 721e56ef5c]
2024-04-11 12:51:52 -04:00
David Yat Sin f3db911e3c Add limit checks for HSA_SINGLE_SCRATCH_LIMIT
Hard limit for scratch is 4GB per XCC and checks in case user specifies
values exceeding this value

Change-Id: Ib3cade762ff66c7e7d6a2d311e482cacbcf2b0de


[ROCm/ROCR-Runtime commit: d7adc94e3f]
2024-04-11 14:03:25 +00:00
Konstantin Zhuravlyov 45eafcf4ea loader: allow but skip static relocations for code object v2+
Change-Id: I4ae14cb5e740d7d45810b75038b15a0b94d2bf0b


[ROCm/ROCR-Runtime commit: 08c94463de]
2024-04-09 11:39:18 -04:00
Konstantin Zhuravlyov ae24ca1528 Switch to per-executable contexts in the loader
- Per-executable contexts should be used from now on
  - Global contexts are left as is for now for backwards
    compatibility and will be phased out in follow up
    patches.

Change-Id: I6291abf865c7ed24ee71f5065e539afc23f5ce64


[ROCm/ROCR-Runtime commit: b983c19729]
2024-04-09 10:31:51 -04:00
Shweta Khatri 89e51e1f63 Revert "Use HybridMutex for IPC locks"
This reverts commit 5c520f4544c654e5f18e05cabd1c63d64473cfab.

Reason for revert: This patch is introducing a synchronization related bug in Unit_hipGetSetDevice_MultiThreaded testcase.

Change-Id: I367e4d4f1d75b21658ac1127c58982894a97cedb


[ROCm/ROCR-Runtime commit: 244ad319ac]
2024-04-02 12:27:55 -04:00
Stella Laurenzo 2fea138040 Properly nest build time headers to match arrangement at install time.
The build tree was missing a level of nesting, causing diversions based
on in-tree/out-of-tree use.
KR: Also fixed kfdtest paths

Change-Id: I8638b6d6227daabddd8eaa2aa387ba578b8dfab8
Signed-off-by: Stella Laurenzo <stellaraccident@gmail.com>
Signed-off-by: Kent Russell <kent.russell@amd.com>


[ROCm/ROCR-Runtime commit: a180fea5ad]
2024-04-01 17:10:40 -04:00
David Yat Sin b19929b090 Temporary: Set AllocateGTTAccess and node_id for MES
Temporary change to set the AllocateGTTAccess flag and node_id
on MES devices.

Change-Id: I22385d11b17b76cfb44278fa0d8a09bc8721cea6


[ROCm/ROCR-Runtime commit: efe455c2fa]
2024-03-29 19:38:19 +00:00
David Yat Sin 78ad630632 Set NUMA region to 0 when using GTTAccess flag
When allocating memory for MES AQL queue structure, the PreferredNode
is set to the device index of GPU to hint the location where the BO
needs to be created. But we need to ignore the device index when calling
bind_mem_to_numa.

Change-Id: Iae69fe02bfd48c5a3bd495319f6f2706d6e8aea2


[ROCm/ROCR-Runtime commit: 541d0dbbae]
2024-03-29 17:17:56 +00:00
Konstantin Zhuravlyov 2a7fb7a808 Add R_AMDGPU_ABS32 support
Change-Id: I0ee0302d919ede44765adf02eab15015573efef2


[ROCm/ROCR-Runtime commit: 9e8f185397]
2024-03-26 18:47:29 -04:00
Konstantin Zhuravlyov 853ccdecbb Add dynamic relocation types (NFC)
Change-Id: I1b443003077ba241f34444da293e362266c2ae92


[ROCm/ROCR-Runtime commit: c5e74b7d0a]
2024-03-26 18:47:05 -04:00
Konstantin Zhuravlyov ec66509986 Rename existing relocation types to legacy/v1 (NFC)
Change-Id: Ided7f656c34131b8067a19c0d3b2955fc8823628


[ROCm/ROCR-Runtime commit: b2c32ad6cb]
2024-03-26 18:46:50 -04:00
Shweta.Khatri 565dbac2d4 Replace lazy_ptr's Init() with reset() method
The function Init() called by one of the constructors of lazy_ptr is undefined.
Replacing with reset method sets the object to an uninitialized state and assigns a new constructor function

Fix submitted on github by zhoumin2 - https://github.com/ROCm/ROCR-Runtime/pull/184

Change-Id: I7d906d526ce7fe7e2548b01810e6395b13497bf3


[ROCm/ROCR-Runtime commit: 00b63f7452]
2024-03-26 15:07:34 -04:00
Mihai Preda 69c283ef3d Free the malloc'ed event on page alloc failure
Change-Id: I009a9a6e2f67545c51470e86eac1adb78d6181b4
Signed-off-by: Mihai Preda <preda@users.noreply.github.com>
Signed-off-by: Kent Russell <kent.russell@amd.com>


[ROCm/ROCR-Runtime commit: fa0c182325]
2024-03-26 09:57:26 -04:00
James Zhu 8fd711ac59 kfdtest: add kfdtest test cases for pc sampling
Add kfdtest test cases for pc sampling.

Change-Id: I49f4f8ebfa6569803acdc7dec895c1902ce0b280
Signed-off-by: James Zhu <James.Zhu@amd.com>


[ROCm/ROCR-Runtime commit: daf99471a4]
2024-03-26 02:06:19 -04:00
David Yat Sin 19c7b5b4f6 libhsakmt: add PC sampling support
Add pc sampling support.

Change-Id: I08199024ba5a8eb2845c048d499fc8fcd260d2e8
Signed-off-by: David Yat Sin <David.YatSin@amd.com>
Signed-off-by: James Zhu <James.Zhu@amd.com>


[ROCm/ROCR-Runtime commit: f94e2530fb]
2024-03-25 15:53:38 +00:00
Shweta.Khatri cef0e09844 Convert some comments to Doxygen-style comments
hsa_ext_amd.h - Fix provided by github developer - Mátyás Aradi
Github request - https://github.com/ROCm/ROCR-Runtime/pull/187

Change-Id: I63e4175caebd10be0151f21bd5f048dd011aaf06


[ROCm/ROCR-Runtime commit: 02a40e9272]
2024-03-25 11:47:14 -04:00
David Yat Sin a88194702c libhsakmt: Update Linux header for PC Sampling
Add pc sampling support

Change-Id: I2c472ce00ff8648904cf7e585687e81d3f493049
Signed-off-by: David Yat Sin <David.YatSin@amd.com>
Signed-off-by: James Zhu <James.Zhu@amd.com>


[ROCm/ROCR-Runtime commit: 4f554988b6]
2024-03-22 15:06:10 +00:00
Philip Yang 96206ef888 libhsakmt: Add memory alloc flag GTTAccess
To allocate GTT memory for MES AQL queue structure, KFD will create GART
mapping for the memory to be accessed by MES.

Change-Id: Iae7b33d1e70861109f1551d3a71dc60dfde9de61
Signed-off-by: Philip Yang <Philip.Yang@amd.com>


[ROCm/ROCR-Runtime commit: 9fbe853fea]
2024-03-20 10:41:51 -04:00
Ori Messinger 6d04547b22 kfdtest: Exclude KFDQMTest.QueueLatency test
The purpose of this patch is to add KFDQMTest.QueueLatency to
kfdtest.exclude file temporarily for the following ASIC filters:
  -GFX940
  -GFX941
  -GFX942

This test is failing due to an issue with the way it was coded,
not due to an issue with the ASICs it is now blacklisted on.

Signed-off-by: Ori Messinger <Ori.Messinger@amd.com>
Change-Id: Ic993629a2400449f598e73fe616a4572a38e2310


[ROCm/ROCR-Runtime commit: 656234abb8]
2024-03-19 14:37:49 -04:00
David Belanger ddcccab5ba kfdtest: Update QueuePriority* tests for emulation
Reduce test case size if running on emulator.
Also, refactor code as both test cases had more than 80% same code.

Signed-off-by: David Belanger <david.belanger@amd.com>
Change-Id: I5899ee24244a6f0aa6b56fa8a4701b0b1e344b9f


[ROCm/ROCR-Runtime commit: e738648c8f]
2024-03-19 11:30:05 -04:00
David Belanger dd4079f8f1 kfdtest: Update PM4EventInterrupt for emulation
Reduce number of iteration for test case to run in reasonable amount of
time.

Signed-off-by: David Belanger <david.belanger@amd.com>
Change-Id: I19a7ec0d5f03c54d6691aae3cf7432754c7481cc


[ROCm/ROCR-Runtime commit: 66e3a09a42]
2024-03-19 11:29:38 -04:00
David Yat Sin 7382f5b5b3 Fix uninialized variables
Change-Id: Ie5da4547fa764e55162aff287cbb338ed4324093


[ROCm/ROCR-Runtime commit: 9d842dd1d8]
2024-03-14 15:20:56 -04:00
Xinmudotmoe 3b6146e7db Update doorbell->size to support large default PAGE_SIZE kernels
Change-Id: I6fbe10ae3309f2f935d6782366cedb56dc1438c3
Signed-off-by: Xinmudotmoe <xinmu@xinmu.moe>
Signed-off-by: Kent Russell <kent.russell@amd.com>


[ROCm/ROCR-Runtime commit: 0c06bec272]
2024-03-13 09:18:42 -04:00
Stella Laurenzo 4fbec4e774 Link CMAKE_DL_LIBS.
Was failing to link on AlmaLinux8.

Change-Id: Id7df245f1063c2bebd0f07efc352f1b9017eda0e
Signed-off-by: Stella Laurenzo <stellaraccident@gmail.com>
Signed-off-by: Kent Russell <kent.russell@amd.com>


[ROCm/ROCR-Runtime commit: 7c10e1e4f5]
2024-03-13 09:18:03 -04:00
pvanhout 8e43aaab04 [libamdhsacode] Support COV6/Generic Targets
Change-Id: I4680577eb56dc436fbc134b169f172dd476bff37


[ROCm/ROCR-Runtime commit: a93c18dc90]
2024-03-12 07:37:32 -04:00
Jonathan R. Madsen 64d380d125 Add hsa_api_trace_version.h
- hsa_api_trace.h contains C++
- rocprofiler-sdk needs to include the table version number defines (*_MAJOR_VERSION and *_STEP_VERSION) for the HSA API in it's public headers
- rocprofiler-sdk needs it's public headers to be C-compatible so hsa_api_trace_version.h was created

Change-Id: Ieece990b3b7775cb0446b545c9e3391c5f691c61


[ROCm/ROCR-Runtime commit: 5402842d5f]
2024-03-12 01:17:34 -04:00
Sv. Lockal 760647dd19 Fix compilation on musl-based systems
This allows to build ROCT-Thunk-Interface for Alpine Linux, Gentoo with musl profile and so on.

List of changes:
* Fix redefinition of PAGE_SIZE from limits.h
* Use NAME_MAX from limits.h

Closes #65

Change-Id: Ibdb0ef5668a07b7b403fcc4a44cd2658e00a584a
Signed-off-by: Sv. Lockal <lockalsash@gmail.com>
Signed-off-by: Kent Russell <kent.russell@amd.com>


[ROCm/ROCR-Runtime commit: 9a89997b5f]
2024-03-11 10:46:55 -04:00
Jonathan Kim 5cfa60e03e Fix deferred dmabuf export on IPC due to GEM object loss
When deferring a dmabuf export on an import call, there may be a
failure to export as the GEM object is not referenced by the kernel
mode driver.  To get around this, do a non-deferred export and
immediately close the dmabuf FD to keep FD creation to a minimum.
This way, the GEM object will have a kernel mode driver reference
when a deferred export is done.

Also a bad dmabuf FD sent over a socket may not be received by an import
reader and this can cause a hang.
Set a 10 second timer so that importer is not blocking indefinitely.

Change-Id: I11a9b5ec64aa2e16fd6aecdf46c34e4eb56ccfd0


[ROCm/ROCR-Runtime commit: eb2100daad]
2024-03-07 12:12:06 -05:00
Alex Sierra 7721aadf66 core dump: Generates a core dump from a fault event
Extracts and creates a core dump ELF file from a fault event, using
core dump front end. GFX11 is not supported.

Signed-off-by: Alex Sierra <Alex.Sierra@amd.com>
Change-Id: I5ae154e886f39ab3ce7bbae5803efb27a96c7e2e


[ROCm/ROCR-Runtime commit: cbeddf9eb6]
2024-03-05 09:28:44 -05:00
Lancelot SIX 7f763d499a trap_handler: Set status.skip_export when halting a wave
When inspecting waves on architectures where SPI may not initialize TTMP
registers, the debugger cannot reliably know if the trap handler was
entered and if it saved valuable information in TTMP registers.

This patch uses the status.skip_export bit (unused by the compute
shaders) to indicate that it got executed before halting a wave.
This is done except for gfx940, where ttmp11[31] can be used (as long as
TTMP registers are always initialized by SPI for this architecture).  It
could be possible to be more selective as architectures always
initializing TTMP registers do not require this step, but always doing
is makes maintenance simpler.

Change-Id: I5c4148c78062f7ffa049ac7856c2edc82dbc77d1


[ROCm/ROCR-Runtime commit: 5d3f6a63f1]
2024-03-05 09:28:33 -05:00
Jonathan Kim f9a6578b6b Disable SDMA ganging on non-APU multi-partition modes
Work around SDMA hang in non-SPX modes for non-APU devices by disabling
ganging.
Root cause of hang not found.
non-APU xGMI modes have only 1 link between socket devices anyways so
there's likely no real system level gain in ganging intra-socket.

Change-Id: Ia4eda2f85cbf25151d3dbcf50cc45b8b775c60e2


[ROCm/ROCR-Runtime commit: ed462035fa]
2024-02-28 14:52:01 -05:00
Jonathan Kim 1e46d28ee6 Fix gang item wait on dependency signals
Gang items have to wait on dependency signals as well as the leader.
Copies should not start if shaders are still operating on memory
to be copied.

Change-Id: I99703b420045ebcba2c9da39ec64678129dc140f


[ROCm/ROCR-Runtime commit: ed260ea970]
2024-02-27 12:45:41 -05:00
Harish Kasiviswanathan 2f05682f29 libhsakmt: Associate correct GPU with queue memory
Pass the correct gpu_id to KFD for system memory that is allocated for
the queue and eop buffer

Change-Id: I43bb6333560a7d9d38293c191303161ab1443b5d
Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>


[ROCm/ROCR-Runtime commit: 341ecaf1d9]
2024-02-26 14:20:16 -05:00
Shweta Khatri a0ebf06e6e Record interop mapped object in allocation_map_
This allows the VA to be recorded in ROCr so that they are not
treated as an invalid pointer in future API calls.

Change-Id: I8d1d8ef9816a984c89d30a2179b0ce8940fef1da


[ROCm/ROCR-Runtime commit: f2006d6899]
2024-02-26 13:40:55 -05:00
Harish Kasiviswanathan de1c7daba7 libhsakmt: Move global zfb_support to globals.c
zfb_support needs to accessed from multiple places, so move to globals.c
file

Change-Id: I40b487c26a13e7cc6fc01b671d6166e7114e02d2
Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>


[ROCm/ROCR-Runtime commit: 191caf46ac]
2024-02-26 09:08:11 -05:00