SWDEV-2 - Change OpenCL version number from 2844 to 2845.
Affected files ...
... //depot/stg/opencl/drivers/opencl/runtime/utils/versions.hpp#2592 edit
[ROCm/clr commit: 0b988784ec]
SWDEV-2 - Change OpenCL version number from 2844 to 2845.
Affected files ...
... //depot/stg/opencl/drivers/opencl/runtime/utils/versions.hpp#2592 edit
SWDEV-2 - Change OpenCL version number from 2843 to 2844.
Affected files ...
... //depot/stg/opencl/drivers/opencl/runtime/utils/versions.hpp#2591 edit
[ROCm/clr commit: 3bbc2654e4]
SWDEV-2 - Change OpenCL version number from 2843 to 2844.
Affected files ...
... //depot/stg/opencl/drivers/opencl/runtime/utils/versions.hpp#2591 edit
This patch separates the build version (i.e. ROCm version) from the
library version used to set the SONAME of the shared objects. This
prevents the SONAME from getting bumped each time there is a new ROCm
release without any change to the libhsakmt ABI.
1.0.6 was choosen as the library version since this was the
last library version used prior to switching to the ROCm version
numbers.
Change-Id: I7c29ae84d8a362a831e804569d8147ca65155cad
1. RAS error injection debugfs interface has been changed which
is using ras_ctrl instead of *_err_inject.
2. Remove ASSERT_SUCCESS for fwrite, because fwrite returns
the size of written item but not the error number.
3. Using throw exception instead of return to avoid a segment fault.
Change-Id: I6c4d9c2f7e66719faec99abd1552105a08c238a4
Signed-off-by: Eric Huang <JinhuiEric.Huang@amd.com>
While this may not be supported in the runtime, the kernel/firmware
support it
Change-Id: I7fe4536a6b3055f39e25f453060e899938645d91
Signed-off-by: Kent Russell <kent.russell@amd.com>
This reverts commit d00ec779ce.
Fixes for HMM change corner cases are merged in from drm-next.
Tests are passed on gfx900 with the latest amd-kfd-staging.
Change-Id: I6c00d1eacf6b3f1ce715e085ae622b4e9ff1b7ff
Signed-off-by: Philip Yang <Philip.Yang@amd.com>
While adding x2APIC support, apicid for non-x2apic was missing out by
mistake.
Change-Id: I25eed362c035c0e9fb9ea948899c49f70311f269
Signed-off-by: Amber Lin <Amber.Lin@amd.com>
Add SDMA engine info fields to node properties and
modify get node properties API to read SDMA engine
info from sysfs
Change-Id: Iea877b5bc008cc9df9405daf564a359535f1bc9f
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
Current processor/cache topology code implements xAPIC architecture, which
is 8 bits addressability. This is not enough for a system having more than
255 processors. x2APIC is the extension of xAPIC architecture to support
32 bit addressability of processors. This patch detects the x2APIC
enablement and uses the extension leaf to get apicid when detected.
Change-Id: I0826585d02f696a46cd5efb9a6630c60af01e2d8
Signed-off-by: Amber Lin <Amber.Lin@amd.com>
This patch separates the build version (i.e. ROCm version) from the
library version used to set the SONAME of the shared objects. This
prevents the SONAME from getting bumped each time there is a new ROCm
release without any change to the libhsakmt ABI.
1.0.6 was choosen as the library version since this was the
last library version used prior to switching to the ROCm version
numbers.
Change-Id: I7c29ae84d8a362a831e804569d8147ca65155cad
[ROCm/ROCR-Runtime commit: 006c2c248d]
1. RAS error injection debugfs interface has been changed which
is using ras_ctrl instead of *_err_inject.
2. Remove ASSERT_SUCCESS for fwrite, because fwrite returns
the size of written item but not the error number.
3. Using throw exception instead of return to avoid a segment fault.
Change-Id: I6c4d9c2f7e66719faec99abd1552105a08c238a4
Signed-off-by: Eric Huang <JinhuiEric.Huang@amd.com>
[ROCm/ROCR-Runtime commit: e5b215570b]
It is aligned with RAS changes in KFD.
Change-Id: I52816da01a4001158a40a1207d1fbe6ec3271343
Signed-off-by: Eric Huang <JinhuiEric.Huang@amd.com>
[ROCm/ROCR-Runtime commit: d6cde5bf08]
While this may not be supported in the runtime, the kernel/firmware
support it
Change-Id: I7fe4536a6b3055f39e25f453060e899938645d91
Signed-off-by: Kent Russell <kent.russell@amd.com>
[ROCm/ROCR-Runtime commit: 1304a92e17]
This reverts commit a349805264.
Fixes for HMM change corner cases are merged in from drm-next.
Tests are passed on gfx900 with the latest amd-kfd-staging.
Change-Id: I6c00d1eacf6b3f1ce715e085ae622b4e9ff1b7ff
Signed-off-by: Philip Yang <Philip.Yang@amd.com>
[ROCm/ROCR-Runtime commit: 0bd9f35563]
While adding x2APIC support, apicid for non-x2apic was missing out by
mistake.
Change-Id: I25eed362c035c0e9fb9ea948899c49f70311f269
Signed-off-by: Amber Lin <Amber.Lin@amd.com>
[ROCm/ROCR-Runtime commit: cfa47ac1f9]
Add SDMA engine info fields to node properties and
modify get node properties API to read SDMA engine
info from sysfs
Change-Id: Iea877b5bc008cc9df9405daf564a359535f1bc9f
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
[ROCm/ROCR-Runtime commit: 414a3508d6]
A new SDMA queue type for XGMI was added
Change-Id: Iad065c1a7c053a58e0d86becfb374215e316a611
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
[ROCm/ROCR-Runtime commit: e4109de26d]
Current processor/cache topology code implements xAPIC architecture, which
is 8 bits addressability. This is not enough for a system having more than
255 processors. x2APIC is the extension of xAPIC architecture to support
32 bit addressability of processors. This patch detects the x2APIC
enablement and uses the extension leaf to get apicid when detected.
Change-Id: I0826585d02f696a46cd5efb9a6630c60af01e2d8
Signed-off-by: Amber Lin <Amber.Lin@amd.com>
[ROCm/ROCR-Runtime commit: f8028a40fd]
Rahul Garg
foreman
Chris Freehill
Chris Freehill
Maneesh Gupta
Jenkins
Tom Stellard
Eric Huang
Sean Keely
Kent Russell
Philip Yang
Amber Lin
Oak Zeng
Wilkin Chau