76333 Commity

Autor SHA1 Wiadomość Data
Yiltan 0cde5f53dc Update GTEST version (#68)
[ROCm/rocshmem commit: e16ca7a1e3]
2025-03-31 08:58:30 -04:00
Yiltan e16ca7a1e3 Update GTEST version (#68) 2025-03-31 08:58:30 -04:00
Lancelot SIX 6a4785f650 Fix Stochastic sampling trap handler
The trap handler should read the PERF_SNAPSHOT_DATA after all of
PERF_SNAPSHOT_DATA, PERF_SNAPSHOT_PC_LO and PERF_SNAPSHOT_PC_HI.  This
patch fixes this.

Change-Id: I7f78e16d7a0d8bfebb34906b4dff73c2eaeb5658
2025-03-31 10:20:19 +01:00
Lancelot SIX fff4455589 Fix Stochastic sampling trap handler
The trap handler should read the PERF_SNAPSHOT_DATA after all of
PERF_SNAPSHOT_DATA, PERF_SNAPSHOT_PC_LO and PERF_SNAPSHOT_PC_HI.  This
patch fixes this.

Change-Id: I7f78e16d7a0d8bfebb34906b4dff73c2eaeb5658


[ROCm/ROCR-Runtime commit: 6a4785f650]
2025-03-31 10:20:19 +01:00
Lancelot SIX eece210a5c trap_handler.s: Clear PERF_SNAPSHOT/HOST_TRAP before returning
Make sure to clear the HOST_TRAP and PERF_SNAPSHOT bits before returning
from the second level trap handler.  As those bits are sticky, this
ensures future re-entry to the trap handler (for context save for
example) will not be confused with a sampling trap.

Change-Id: I05e5e58779a650b324ac6e30d574dc6931340f13
Signed-off-by: Lancelot SIX <lancelot.six@amd.com>
2025-03-31 10:20:19 +01:00
Lancelot SIX 23254f7a1d trap_handler.s: Clear PERF_SNAPSHOT/HOST_TRAP before returning
Make sure to clear the HOST_TRAP and PERF_SNAPSHOT bits before returning
from the second level trap handler.  As those bits are sticky, this
ensures future re-entry to the trap handler (for context save for
example) will not be confused with a sampling trap.

Change-Id: I05e5e58779a650b324ac6e30d574dc6931340f13
Signed-off-by: Lancelot SIX <lancelot.six@amd.com>


[ROCm/ROCR-Runtime commit: eece210a5c]
2025-03-31 10:20:19 +01:00
Yuan, Perry 3bdca8b8b6 Implement CPU discovery support (#77)
* Implement CPU discovery support

SWDEV-482949:

enable the CPU model name info support to the RDC, rdci command
can detect GPU and CPU modules at the same time.
It will query the CPU info through the amdsmi interface like below:

1 GPUs found.
-----------------------------------------------------------------
GPU Index        Device Information
0               AMD Radeon PRO W7800
=================================================================
1 CPUs found.
-----------------------------------------------------------------
CPU Index        Device Information
0               AMD Ryzen Threadripper PRO 7995WX 96-Cores
-----------------------------------------------------------------

Change-Id: Ibc6533c9a61000cd86c45b1bae14c3eb6788c119
Signed-off-by: Perry Yuan <perry.yuan@amd.com>

* CMAKE - Add required version for amdsmi

Change-Id: I341a89351d196ec66cce215a5d1d3953302fcc66
Signed-off-by: Galantsev, Dmitrii <dmitrii.galantsev@amd.com>

---------

Signed-off-by: Perry Yuan <perry.yuan@amd.com>
Signed-off-by: Galantsev, Dmitrii <dmitrii.galantsev@amd.com>
Co-authored-by: Galantsev, Dmitrii <dmitrii.galantsev@amd.com>
2025-03-31 10:58:36 +08:00
Yuan, Perry f0f44d977f Implement CPU discovery support (#77)
* Implement CPU discovery support

SWDEV-482949:

enable the CPU model name info support to the RDC, rdci command
can detect GPU and CPU modules at the same time.
It will query the CPU info through the amdsmi interface like below:

1 GPUs found.
-----------------------------------------------------------------
GPU Index        Device Information
0               AMD Radeon PRO W7800
=================================================================
1 CPUs found.
-----------------------------------------------------------------
CPU Index        Device Information
0               AMD Ryzen Threadripper PRO 7995WX 96-Cores
-----------------------------------------------------------------

Change-Id: Ibc6533c9a61000cd86c45b1bae14c3eb6788c119
Signed-off-by: Perry Yuan <perry.yuan@amd.com>

* CMAKE - Add required version for amdsmi

Change-Id: I341a89351d196ec66cce215a5d1d3953302fcc66
Signed-off-by: Galantsev, Dmitrii <dmitrii.galantsev@amd.com>

---------

Signed-off-by: Perry Yuan <perry.yuan@amd.com>
Signed-off-by: Galantsev, Dmitrii <dmitrii.galantsev@amd.com>
Co-authored-by: Galantsev, Dmitrii <dmitrii.galantsev@amd.com>

[ROCm/rdc commit: 3bdca8b8b6]
2025-03-31 10:58:36 +08:00
Galantsev, Dmitrii 80ee980cdb CMAKE - Fix build types
Addresses issue https://github.com/ROCm/rdc/issues/43

Change-Id: I456184358524a6feef4bf83eecb655678c3bc42d
Signed-off-by: Galantsev, Dmitrii <dmitrii.galantsev@amd.com>
2025-03-30 18:54:54 -05:00
Galantsev, Dmitrii 874a7b438f CMAKE - Fix build types
Addresses issue https://github.com/ROCm/rdc/issues/43

Change-Id: I456184358524a6feef4bf83eecb655678c3bc42d
Signed-off-by: Galantsev, Dmitrii <dmitrii.galantsev@amd.com>


[ROCm/rdc commit: 80ee980cdb]
2025-03-30 18:54:54 -05:00
Arif, Maisam d7416c98d7 Update quick start tool (#219)
Added CLI libs to amdsmi_quick_start.py

Change-Id: I72428d083dbff6224e57a97b954f602c72d323e8

Signed-off-by: Maisam Arif <Maisam.Arif@amd.com>
2025-03-29 12:06:02 -05:00
Arif, Maisam 56fa8ec779 Update quick start tool (#219)
Added CLI libs to amdsmi_quick_start.py

Change-Id: I72428d083dbff6224e57a97b954f602c72d323e8

Signed-off-by: Maisam Arif <Maisam.Arif@amd.com>

[ROCm/amdsmi commit: d7416c98d7]
2025-03-29 12:06:02 -05:00
Galantsev, Dmitrii b0129c390c Bump Version 25.4.0
Change-Id: Ief60ff2270e7e73d4e14b5181fa6fb18e32bcc1e
Signed-off-by: Galantsev, Dmitrii <dmitrii.galantsev@amd.com>
2025-03-28 21:50:38 -05:00
Galantsev, Dmitrii e798e5336f Bump Version 25.4.0
Change-Id: Ief60ff2270e7e73d4e14b5181fa6fb18e32bcc1e
Signed-off-by: Galantsev, Dmitrii <dmitrii.galantsev@amd.com>


[ROCm/amdsmi commit: b0129c390c]
2025-03-28 21:50:38 -05:00
Arif, Maisam 7ff8041afa Revert "[SWDEV-493519] Fix Getting Version Information (#201)"
This reverts commit df8ee3db85.
2025-03-28 21:37:14 -05:00
Arif, Maisam c5a819b6b9 Revert "[SWDEV-493519] Fix Getting Version Information (#201)"
This reverts commit ebdfe2ea21.


[ROCm/amdsmi commit: 7ff8041afa]
2025-03-28 21:37:14 -05:00
Yuan, Perry 68e44c7f66 [SWDEV-482949] Add CPU model name querying support (#33)
- Add support to check CPU vendor info which will be called by RDC to
discovery CPU information
- Move esmi headers declaration to impl/amd_smi_common.h
- remove duplicated amdsmi_cpu_util_t

---------

Signed-off-by: Perry Yuan <perry.yuan@amd.com>
Signed-off-by: Deepak Mewar <deepak.mewar@amd.com>
Signed-off-by: Maisam Arif <Maisam.Arif@amd.com>
Co-authored-by: Deepak Mewar <deepak.mewar@amd.com>
2025-03-28 21:21:39 -05:00
Yuan, Perry b92ffd2bcf [SWDEV-482949] Add CPU model name querying support (#33)
- Add support to check CPU vendor info which will be called by RDC to
discovery CPU information
- Move esmi headers declaration to impl/amd_smi_common.h
- remove duplicated amdsmi_cpu_util_t

---------

Signed-off-by: Perry Yuan <perry.yuan@amd.com>
Signed-off-by: Deepak Mewar <deepak.mewar@amd.com>
Signed-off-by: Maisam Arif <Maisam.Arif@amd.com>
Co-authored-by: Deepak Mewar <deepak.mewar@amd.com>

[ROCm/amdsmi commit: 68e44c7f66]
2025-03-28 21:21:39 -05:00
Nilesh M Negi 1a2eca1756 Revert "[GRAPH] Increase default nChannels to 112 for gfx950 (#1596)" (#1620)
* Revert "[GRAPH] Increase default nChannels to 112 for gfx950 (#1596)"

This reverts commit cf17cff5b6.

* [DOC] Update Changelog

* [DOC] Update CHANGELOG

[ROCm/rccl commit: b17338d164]
2025-03-28 17:57:06 -05:00
Nilesh M Negi b17338d164 Revert "[GRAPH] Increase default nChannels to 112 for gfx950 (#1596)" (#1620)
* Revert "[GRAPH] Increase default nChannels to 112 for gfx950 (#1596)"

This reverts commit 1df73e209e.

* [DOC] Update Changelog

* [DOC] Update CHANGELOG
2025-03-28 17:57:06 -05:00
Fei Zheng ee5df82698 Support host-trap PC Sampling on CLI (beta version)
[ROCm/rocprofiler-compute commit: 9bacad0876]
2025-03-28 16:51:49 -06:00
Fei Zheng 9bacad0876 Support host-trap PC Sampling on CLI (beta version) 2025-03-28 16:51:49 -06:00
Edgar Gabriel 2ab585ce8d add uniqueID initialization (#69)
add the interfaces required to support rocshmem initialization
through the uniqueID mechanism. At the moment this still maps to
MPI initialization underneath the hood, but adding the functions might
simplify the porting of some applications to rocshmem. In addition, if
we need to transition away from MPI one day, this is also one step into
this direction.

[ROCm/rocshmem commit: e9f6227d75]
2025-03-28 16:34:00 -05:00
Edgar Gabriel e9f6227d75 add uniqueID initialization (#69)
add the interfaces required to support rocshmem initialization
through the uniqueID mechanism. At the moment this still maps to
MPI initialization underneath the hood, but adding the functions might
simplify the porting of some applications to rocshmem. In addition, if
we need to transition away from MPI one day, this is also one step into
this direction.
2025-03-28 16:34:00 -05:00
Bertan Dogancay b737d8c222 Merge pull request #1559 from BertanDogancay/2.23
[SYNC] 2.23.4-1

[ROCm/rccl commit: 532f54c244]
2025-03-28 17:06:56 -04:00
Bertan Dogancay 532f54c244 Merge pull request #1559 from BertanDogancay/2.23
[SYNC] 2.23.4-1
2025-03-28 17:06:56 -04:00
jeffqjiangNew 13e8e15d7b * rocDecode/HEVC error resilience: Added dependant slice error handling. (#547)
[ROCm/rocdecode commit: fc01d72aea]
2025-03-28 16:35:03 -04:00
jeffqjiangNew fc01d72aea * rocDecode/HEVC error resilience: Added dependant slice error handling. (#547) 2025-03-28 16:35:03 -04:00
Nilesh M Negi a7ec191754 [TEST] Switch to googletest release 1.12.0 (#1621)
Signed-off-by: nileshnegi <Nilesh.Negi@amd.com>

[ROCm/rccl commit: 0e2c461c6c]
2025-03-28 12:39:42 -05:00
Nilesh M Negi 0e2c461c6c [TEST] Switch to googletest release 1.12.0 (#1621)
Signed-off-by: nileshnegi <Nilesh.Negi@amd.com>
2025-03-28 12:39:42 -05:00
Arif, Maisam d7e8c02428 [SWDEV-524528] Nullptr check correction for TestErrCntRead (#38)
Signed-off-by: Maisam Arif <Maisam.Arif@amd.com>

[ROCm/rocm_smi_lib commit: 91f30c5756]
2025-03-28 12:14:28 -05:00
Arif, Maisam 91f30c5756 [SWDEV-524528] Nullptr check correction for TestErrCntRead (#38)
Signed-off-by: Maisam Arif <Maisam.Arif@amd.com>
2025-03-28 12:14:28 -05:00
Baraldi, Giovanni 6301f46d13 SWDEV-520093+SWDEV-521137+SWDEV-523996: Fix for missing AMDGPU_HSA_V6 (#20)
* Adding AMDGPU_HSA_V6

* Fix segment

* Fix conflicts

* ident fix

* Symbol lookup fix

---------

Co-authored-by: Giovanni Baraldi <gbaraldi@amd.com>
2025-03-28 10:02:49 -07:00
Baraldi, Giovanni 1a3e33774c SWDEV-520093+SWDEV-521137+SWDEV-523996: Fix for missing AMDGPU_HSA_V6 (#20)
* Adding AMDGPU_HSA_V6

* Fix segment

* Fix conflicts

* ident fix

* Symbol lookup fix

---------

Co-authored-by: Giovanni Baraldi <gbaraldi@amd.com>

[ROCm/rocprofiler commit: 6301f46d13]
2025-03-28 10:02:49 -07:00
Mallya, Ameya Keshava f7601f0fe5 Added KWS check for amd-mainline
[ROCm/hipother commit: fa53966bc5]
2025-03-28 09:22:20 -07:00
Mallya, Ameya Keshava fa53966bc5 Added KWS check for amd-mainline 2025-03-28 09:22:20 -07:00
Mallya, Ameya Keshava 265ef6e71a Added KWS check for amd-mainline (#9)
[ROCm/rocminfo commit: 5c8c974e71]
2025-03-28 09:19:43 -07:00
Mallya, Ameya Keshava 5c8c974e71 Added KWS check for amd-mainline (#9) 2025-03-28 09:19:43 -07:00
Arif, Maisam 13c222a103 [SWDEV-524528] Nullptr check correction for TestErrCntRead (#211)
Signed-off-by: Maisam Arif <Maisam.Arif@amd.com>
Change-Id: I1331a69544a6f5b7b61ea4655b635b42bbb56444
2025-03-28 11:18:22 -05:00
Arif, Maisam 952bff9126 [SWDEV-524528] Nullptr check correction for TestErrCntRead (#211)
Signed-off-by: Maisam Arif <Maisam.Arif@amd.com>
Change-Id: I1331a69544a6f5b7b61ea4655b635b42bbb56444

[ROCm/amdsmi commit: 13c222a103]
2025-03-28 11:18:22 -05:00
Narlo, Joseph df8ee3db85 [SWDEV-493519] Fix Getting Version Information (#201)
Signed-off-by: Joseph Narlo <joseph.narlo@amd.com>
2025-03-28 11:12:21 -05:00
Narlo, Joseph ebdfe2ea21 [SWDEV-493519] Fix Getting Version Information (#201)
Signed-off-by: Joseph Narlo <joseph.narlo@amd.com>

[ROCm/amdsmi commit: df8ee3db85]
2025-03-28 11:12:21 -05:00
Maisam Arif 3aac3801d1 [SWDEV-524528] Nullptr check correction for TestErrCntRead
Signed-off-by: Maisam Arif <Maisam.Arif@amd.com>
Change-Id: I1331a69544a6f5b7b61ea4655b635b42bbb56444
2025-03-28 11:11:58 -05:00
Maisam Arif 27ba6fcb86 [SWDEV-524528] Nullptr check correction for TestErrCntRead
Signed-off-by: Maisam Arif <Maisam.Arif@amd.com>
Change-Id: I1331a69544a6f5b7b61ea4655b635b42bbb56444


[ROCm/amdsmi commit: 3aac3801d1]
2025-03-28 11:11:58 -05:00
Mallya, Ameya Keshava 5dfa8fb922 Added KWS check for amd-mainline (#3)
[ROCm/rocm-core commit: ecb7d612c7]
2025-03-28 08:40:22 -07:00
Mallya, Ameya Keshava ecb7d612c7 Added KWS check for amd-mainline (#3) 2025-03-28 08:40:22 -07:00
Mallya, Ameya Keshava f17b7e8c3e Added KWS check for amd-mainline 2025-03-28 08:39:23 -07:00
Mallya, Ameya Keshava be0f948018 Added KWS check for amd-mainline
[ROCm/rocprofiler commit: f17b7e8c3e]
2025-03-28 08:39:23 -07:00
Mallya, Ameya Keshava 38e4d2c78b Added KWS check for amd-mainline
[ROCm/rocm-core commit: 5da6a07d56]
2025-03-28 08:38:44 -07:00
Mallya, Ameya Keshava 5da6a07d56 Added KWS check for amd-mainline 2025-03-28 08:38:44 -07:00