76333 Commits

Autor SHA1 Nachricht Datum
Arandjelovic, Marko 1c83314659 SWDEV-517867 - Remove invalid assert (#55)
* Remove invalid assert

* Retrigger CI

* Rebase

[ROCm/clr commit: 8fcaa1ca93]
2025-04-03 11:14:32 +02:00
Arandjelovic, Marko 8fcaa1ca93 SWDEV-517867 - Remove invalid assert (#55)
* Remove invalid assert

* Retrigger CI

* Rebase
2025-04-03 11:14:32 +02:00
Lancelot SIX e0359e5d35 rocr: Replace tabs with spaces in trap handler source codes
Use spaces consistently to format the trap handler code.  This patch
does not introduce any change in the trap handler.  Using `git show -w`
on this patch shows an empty diff.

Change-Id: Ic0244dd203347146ffde65460cd87ecbcc43732a
2025-04-03 09:44:23 +01:00
Lancelot SIX c813d2c62d rocr: Replace tabs with spaces in trap handler source codes
Use spaces consistently to format the trap handler code.  This patch
does not introduce any change in the trap handler.  Using `git show -w`
on this patch shows an empty diff.

Change-Id: Ic0244dd203347146ffde65460cd87ecbcc43732a


[ROCm/ROCR-Runtime commit: e0359e5d35]
2025-04-03 09:44:23 +01:00
vedithal-amd 27585a8a2b Support MI 350 profiling (#632)
* Add MI 350 hardware information

* Refactor MI GPU YAML file and corresponding interface

* Add SoC file for gfx950 architecture

* Add analysis report configs for MI 350 containing existing metrics

* Add placeholder None valued metrics for previous architectures to make
  baseline comparison work

* Enable testing on MI 350

* Analysis config metric changes
    - SPI changes
        - Update metric formula for default SPI pipe counter
             - Use efficiently collected pipe wise SPI counters
        - Add SPI Wave Occupancy
        - Add Scheduler-Pipe Wave Utilization
        - Update formula for VGPR Writes
        - Add Scheduler-Pipe FIFO Full Rate
   - CPC changes
	- Add CPC SYNC FIFO Full Rate
	- Add CPC CANE Stall Rate
        - Add CPC ADC Utilization
   - SQ changes
        - Add VALU co-issue efficiency
        - Add F6F4 datatype metrics
        - Update formula for total FLOPs by adding F6F4 counters
        - Add LDS STORE / LOAD / ATOMIC metrics
        - Add LDS STORE / LOAD / ATOMIC bandwidth
        - Add LDS FIFO and TA ADDR / CMD / DATA FIFO full rates

* Collect TCP_TCP_LATENCY_sum only for gfx950 (MI 350)

* Do not inject SQ_ACCUM_PREV_HIRES unnecesarily

* Do not hardcode memory and shader clock speeds

* Write num_hbm_channels to sysinfo.csv instead of hbm_bw while profiling

* Move generate sysinfo.csv to pre processing step of profiling

* Add warnings to use --specs-correction for missing sysinfo.csv values during analysis phase

* Update CHANGELOG

* Analysis phase warning to use --specs-correction when needed

[ROCm/rocprofiler-compute commit: f9aa7be97c]
2025-04-03 02:21:18 -04:00
vedithal-amd f9aa7be97c Support MI 350 profiling (#632)
* Add MI 350 hardware information

* Refactor MI GPU YAML file and corresponding interface

* Add SoC file for gfx950 architecture

* Add analysis report configs for MI 350 containing existing metrics

* Add placeholder None valued metrics for previous architectures to make
  baseline comparison work

* Enable testing on MI 350

* Analysis config metric changes
    - SPI changes
        - Update metric formula for default SPI pipe counter
             - Use efficiently collected pipe wise SPI counters
        - Add SPI Wave Occupancy
        - Add Scheduler-Pipe Wave Utilization
        - Update formula for VGPR Writes
        - Add Scheduler-Pipe FIFO Full Rate
   - CPC changes
	- Add CPC SYNC FIFO Full Rate
	- Add CPC CANE Stall Rate
        - Add CPC ADC Utilization
   - SQ changes
        - Add VALU co-issue efficiency
        - Add F6F4 datatype metrics
        - Update formula for total FLOPs by adding F6F4 counters
        - Add LDS STORE / LOAD / ATOMIC metrics
        - Add LDS STORE / LOAD / ATOMIC bandwidth
        - Add LDS FIFO and TA ADDR / CMD / DATA FIFO full rates

* Collect TCP_TCP_LATENCY_sum only for gfx950 (MI 350)

* Do not inject SQ_ACCUM_PREV_HIRES unnecesarily

* Do not hardcode memory and shader clock speeds

* Write num_hbm_channels to sysinfo.csv instead of hbm_bw while profiling

* Move generate sysinfo.csv to pre processing step of profiling

* Add warnings to use --specs-correction for missing sysinfo.csv values during analysis phase

* Update CHANGELOG

* Analysis phase warning to use --specs-correction when needed
2025-04-03 02:21:18 -04:00
xuchen-amd 1273a5e2a9 Add mi350 ta td tcp tcc counters (#653)
* Add mi350 TA and TD metrics.

* Add mi350 TCC metrics, and separate write and atomic metrics.

* Add mi350 TCP metrics.

* Add none values for non-gfx950 socs, remove missing metrics in rocprofv3.

---------

Signed-off-by: xuchen-amd <xuchen@amd.com>

[ROCm/rocprofiler-compute commit: f3736778f4]
2025-04-02 21:25:47 -04:00
xuchen-amd f3736778f4 Add mi350 ta td tcp tcc counters (#653)
* Add mi350 TA and TD metrics.

* Add mi350 TCC metrics, and separate write and atomic metrics.

* Add mi350 TCP metrics.

* Add none values for non-gfx950 socs, remove missing metrics in rocprofv3.

---------

Signed-off-by: xuchen-amd <xuchen@amd.com>
2025-04-02 21:25:47 -04:00
xuchen-amd 08e083cc25 Add mi300 TCP counter tests (#644)
* Add new sample applications.

* Generalize py test launcher for additional apps.

* Add TCP pytest, and add to ctest.

* Update licensing.

* Disable for non-mi300 machines.

[ROCm/rocprofiler-compute commit: 591632dd69]
2025-04-02 20:32:13 -04:00
xuchen-amd 591632dd69 Add mi300 TCP counter tests (#644)
* Add new sample applications.

* Generalize py test launcher for additional apps.

* Add TCP pytest, and add to ctest.

* Update licensing.

* Disable for non-mi300 machines.
2025-04-02 20:32:13 -04:00
xuchen-amd 35acf4c410 remove flask debug msg (#655)
* Suppress Flask warning message in quiet mode.

* Init args.gui if dne.

[ROCm/rocprofiler-compute commit: c7202923b0]
2025-04-02 20:29:39 -04:00
xuchen-amd c7202923b0 remove flask debug msg (#655)
* Suppress Flask warning message in quiet mode.

* Init args.gui if dne.
2025-04-02 20:29:39 -04:00
Mustafa Abduljabbar 2f4cd5718e Add AllGather LL128 multi-node tuning and include LL cutoff points in tuning models (#1618)
* Enable LL/LL128 cutoff points in tuning models

* Initializing ll/ll128 model cutoffs for MI300

* Use RCCL_LL_LIMITS_UNDEFINED

---------

Co-authored-by: PedramAlizadeh <pmohamma@amd.com>

[ROCm/rccl commit: 4be06f04d8]
2025-04-02 16:26:23 -04:00
Mustafa Abduljabbar 4be06f04d8 Add AllGather LL128 multi-node tuning and include LL cutoff points in tuning models (#1618)
* Enable LL/LL128 cutoff points in tuning models

* Initializing ll/ll128 model cutoffs for MI300

* Use RCCL_LL_LIMITS_UNDEFINED

---------

Co-authored-by: PedramAlizadeh <pmohamma@amd.com>
2025-04-02 16:26:23 -04:00
xuchen-amd b21384ca60 Enable tuned performance counters for gfx950 (#652)
* Enable non-functional performance counters for gfx950.

* Update changelog.

* Add none value metrics for non-gfx950 socs

* Remove rocprofv3 missing metrics.

[ROCm/rocprofiler-compute commit: dce75f4afa]
2025-04-02 14:43:12 -04:00
xuchen-amd dce75f4afa Enable tuned performance counters for gfx950 (#652)
* Enable non-functional performance counters for gfx950.

* Update changelog.

* Add none value metrics for non-gfx950 socs

* Remove rocprofv3 missing metrics.
2025-04-02 14:43:12 -04:00
Avinash Kethineedi 426bbf525b Update Barrier_All and Sync_All APIs (#72)
* Fix deadlock in `rocshmem_ctx_wg_barrier_all` API in IPC conduit by adding per-context pSync buffers and context IDs
  - Added separate pSync buffers for each device context
  - Resolved deadlock when invoking barrier API (`rocshmem_ctx_wg_barrier_all`) concurrently from multiple contexts

* Update barrier_all functional tests for multi-context support

* Add thread, wavefront, and workgroup-level barrier_all APIs in IPC and RO conduits
  - Implemented barrier_all APIs at thread, wavefront, and workgroup granularity
  - Added support in both IPC and RO conduits
  - Updated functional tests to cover all `barrier_all` APIs

* Add thread, wavefront, and workgroup-level sync_all APIs in IPC and RO conduits
  - Implemented sync_all APIs for thread, wavefront, and workgroup scopes
  - Added support into both IPC and RO conduits
  - Added functional tests to cover all `sync_all` APIs

[ROCm/rocshmem commit: c652f58cef]
2025-04-02 11:58:55 -05:00
Avinash Kethineedi c652f58cef Update Barrier_All and Sync_All APIs (#72)
* Fix deadlock in `rocshmem_ctx_wg_barrier_all` API in IPC conduit by adding per-context pSync buffers and context IDs
  - Added separate pSync buffers for each device context
  - Resolved deadlock when invoking barrier API (`rocshmem_ctx_wg_barrier_all`) concurrently from multiple contexts

* Update barrier_all functional tests for multi-context support

* Add thread, wavefront, and workgroup-level barrier_all APIs in IPC and RO conduits
  - Implemented barrier_all APIs at thread, wavefront, and workgroup granularity
  - Added support in both IPC and RO conduits
  - Updated functional tests to cover all `barrier_all` APIs

* Add thread, wavefront, and workgroup-level sync_all APIs in IPC and RO conduits
  - Implemented sync_all APIs for thread, wavefront, and workgroup scopes
  - Added support into both IPC and RO conduits
  - Added functional tests to cover all `sync_all` APIs
2025-04-02 11:58:55 -05:00
Kandula, Venkateshwar reddy f75e7bc674 SWDEV-524130: add missing mi355 counters and derived counters (#323)
* add missing counters from public doc.
;

* add reduce sum counter for mi355 tcc, tcp, ta.

---------

Co-authored-by: Venkateshwar Reddy Kandula <vkandula@amd.com>

[ROCm/rocprofiler-sdk commit: a7f96dde29]
2025-04-02 09:44:57 -07:00
Kandula, Venkateshwar reddy a7f96dde29 SWDEV-524130: add missing mi355 counters and derived counters (#323)
* add missing counters from public doc.
;

* add reduce sum counter for mi355 tcc, tcp, ta.

---------

Co-authored-by: Venkateshwar Reddy Kandula <vkandula@amd.com>
2025-04-02 09:44:57 -07:00
raramakr 7bfc49e9f8 SWDEV-521636 - Add dependent script path to system path in rocprof-compute (#651)
In wheel environment, rocprof-compute in bin folder is not a soft link. For executing rocprof-compute from bin folder, the system path should also have the dependency script paths. Added the same

[ROCm/rocprofiler-compute commit: df2296529b]
2025-04-02 09:41:02 -07:00
raramakr df2296529b SWDEV-521636 - Add dependent script path to system path in rocprof-compute (#651)
In wheel environment, rocprof-compute in bin folder is not a soft link. For executing rocprof-compute from bin folder, the system path should also have the dependency script paths. Added the same
2025-04-02 09:41:02 -07:00
Luu, Jonathan e12743fe19 SWDEV-521313 - Streamline Version Management: Retain Only version-roc… (#4)
SWDEV-521313 Streamline Version Management: Retain Only version-rocm
File

[ROCm/rocm-core commit: cf867754b7]
2025-04-02 11:31:48 -04:00
Luu, Jonathan cf867754b7 SWDEV-521313 - Streamline Version Management: Retain Only version-roc… (#4)
SWDEV-521313 Streamline Version Management: Retain Only version-rocm
File
2025-04-02 11:31:48 -04:00
Mustafa Abduljabbar 0a81478bd9 Fix topo explorer's nccl 2.23 compatibility (#1623)
* Fix compiler issues due to broken compatibility 

* Fix segfault and pass rank instead of busid and add a pointer to cover a new algorithm

[ROCm/rccl commit: aace4e27f8]
2025-04-02 09:47:29 -04:00
Mustafa Abduljabbar aace4e27f8 Fix topo explorer's nccl 2.23 compatibility (#1623)
* Fix compiler issues due to broken compatibility 

* Fix segfault and pass rank instead of busid and add a pointer to cover a new algorithm
2025-04-02 09:47:29 -04:00
Patel, Jaydeepkumar b217d3a4e6 SWDEV-508632 - Align address to 2 MBs for hidden heap allocation. (#29)
[ROCm/clr commit: b5c9cbc236]
2025-04-02 16:33:29 +05:30
Patel, Jaydeepkumar b5c9cbc236 SWDEV-508632 - Align address to 2 MBs for hidden heap allocation. (#29) 2025-04-02 16:33:29 +05:30
dependabot[bot] 25dafc0c82 Bump rocm-docs-core from 1.17.0 to 1.18.1 in /docs/sphinx (#1599)
Bumps [rocm-docs-core](https://github.com/ROCm/rocm-docs-core) from 1.17.0 to 1.18.1.
- [Release notes](https://github.com/ROCm/rocm-docs-core/releases)
- [Changelog](https://github.com/ROCm/rocm-docs-core/blob/develop/CHANGELOG.md)
- [Commits](https://github.com/ROCm/rocm-docs-core/compare/v1.17.0...v1.18.1)

---
updated-dependencies:
- dependency-name: rocm-docs-core
  dependency-type: direct:production
  update-type: version-update:semver-minor
...

Signed-off-by: dependabot[bot] <support@github.com>
Co-authored-by: dependabot[bot] <49699333+dependabot[bot]@users.noreply.github.com>

[ROCm/rccl commit: ffe255d285]
2025-04-01 17:08:53 -06:00
dependabot[bot] ffe255d285 Bump rocm-docs-core from 1.17.0 to 1.18.1 in /docs/sphinx (#1599)
Bumps [rocm-docs-core](https://github.com/ROCm/rocm-docs-core) from 1.17.0 to 1.18.1.
- [Release notes](https://github.com/ROCm/rocm-docs-core/releases)
- [Changelog](https://github.com/ROCm/rocm-docs-core/blob/develop/CHANGELOG.md)
- [Commits](https://github.com/ROCm/rocm-docs-core/compare/v1.17.0...v1.18.1)

---
updated-dependencies:
- dependency-name: rocm-docs-core
  dependency-type: direct:production
  update-type: version-update:semver-minor
...

Signed-off-by: dependabot[bot] <support@github.com>
Co-authored-by: dependabot[bot] <49699333+dependabot[bot]@users.noreply.github.com>
2025-04-01 17:08:53 -06:00
Kanangot Balakrishnan, Bindhiya af9afacfbd [SWDEV-524528] Modify the amd-smi monitor to use drm VRAM API (#228)
Updated the amd-smi monitor to use VRAM drm API.

Signed-off-by: Bindhiya Kanangot Balakrishnan <Bindhiya.KanangotBalakrishnan@amd.com>
2025-04-01 17:05:14 -05:00
Kanangot Balakrishnan, Bindhiya 17ed406553 [SWDEV-524528] Modify the amd-smi monitor to use drm VRAM API (#228)
Updated the amd-smi monitor to use VRAM drm API.

Signed-off-by: Bindhiya Kanangot Balakrishnan <Bindhiya.KanangotBalakrishnan@amd.com>

[ROCm/amdsmi commit: af9afacfbd]
2025-04-01 17:05:14 -05:00
Arif, Maisam 35fbe2cbf1 [SWDEV-521408] Fixed call to amdsmi_get_gpu_virtualization_mode (#230)
Change-Id: I29c86f8982b53cc139004ebc06b26a5d8f430091

Signed-off-by: Maisam Arif <Maisam.Arif@amd.com>
2025-04-01 16:57:23 -05:00
Arif, Maisam 237334ef65 [SWDEV-521408] Fixed call to amdsmi_get_gpu_virtualization_mode (#230)
Change-Id: I29c86f8982b53cc139004ebc06b26a5d8f430091

Signed-off-by: Maisam Arif <Maisam.Arif@amd.com>

[ROCm/amdsmi commit: 35fbe2cbf1]
2025-04-01 16:57:23 -05:00
Jonathan Luu 6ad28c72a8 SWDEV-521313 - Streamline Version Management: Retain Only version-rocm File
[ROCm/rocm-core commit: ab95ccf1a3]
2025-04-01 16:46:04 -04:00
Jonathan Luu ab95ccf1a3 SWDEV-521313 - Streamline Version Management: Retain Only version-rocm File 2025-04-01 16:46:04 -04:00
Nusrat Islam f599690ce3 ext-src: fix mscclpp correctness issue (#1615)
* ext-src: fix mscclpp correctness issue

* ext-src: remove white-space warnings

[ROCm/rccl commit: 4a29bba3c6]
2025-04-01 15:02:16 -05:00
Nusrat Islam 4a29bba3c6 ext-src: fix mscclpp correctness issue (#1615)
* ext-src: fix mscclpp correctness issue

* ext-src: remove white-space warnings
2025-04-01 15:02:16 -05:00
David Yat Sin 2a433e2b96 rocr: Fix PC Sampling PRED_EXEC num dwords count
Fix incorrect value for number of dwords in the PRED_EXEC command.
2025-04-01 15:53:45 -04:00
David Yat Sin f46bc26cff rocr: Fix PC Sampling PRED_EXEC num dwords count
Fix incorrect value for number of dwords in the PRED_EXEC command.


[ROCm/ROCR-Runtime commit: 2a433e2b96]
2025-04-01 15:53:45 -04:00
vedithal-amd ab290f250d Weekly rebase liangdin-test on top of amd-mainline (#650)
[ROCm/rocprofiler-compute commit: a7ebbbd41e]
2025-04-01 14:18:29 -04:00
vedithal-amd a7ebbbd41e Weekly rebase liangdin-test on top of amd-mainline (#650) 2025-04-01 14:18:29 -04:00
Mallya, Ameya Keshava 935cf1bf60 fixed syntax to mainline
[ROCm/rocprofiler-sdk commit: 342223cb81]
2025-04-01 09:52:55 -07:00
Mallya, Ameya Keshava 342223cb81 fixed syntax to mainline 2025-04-01 09:52:55 -07:00
Mallya, Ameya Keshava 5fa2a43222 fixed syntax to mainline
[ROCm/hip-tests commit: d6f98eb109]
2025-04-01 09:52:08 -07:00
Mallya, Ameya Keshava d6f98eb109 fixed syntax to mainline 2025-04-01 09:52:08 -07:00
Mallya, Ameya Keshava 29be7230eb fixed syntax to mainline
[ROCm/clr commit: 98f1db181c]
2025-04-01 09:51:41 -07:00
Mallya, Ameya Keshava 98f1db181c fixed syntax to mainline 2025-04-01 09:51:41 -07:00
Mallya, Ameya Keshava 7aa37c3f93 fixed syntax to mainline
[ROCm/hip commit: e4f1c126ad]
2025-04-01 09:51:18 -07:00
Mallya, Ameya Keshava e4f1c126ad fixed syntax to mainline 2025-04-01 09:51:18 -07:00