SWDEV-3 - PR28394: For compatibility with c++11 and c++14, if a static constexpr data
member is redundantly redeclared outside the class definition in code built in
c++17 mode, ensure we emit a non-discardable definition of the data member for
c++11 and c++14 compilations to use.
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@274416 91177308-0d34-0410-b5e6-96231b3b80d8
GitHash: f82fb5beb88e841f7a00cfb2a2ceabe46bcb2a9b
Affected files ...
... //depot/stg/opencl/drivers/opencl/compiler/clang.git/include/clang/AST/ASTContext.h#3 edit
... //depot/stg/opencl/drivers/opencl/compiler/clang.git/lib/AST/ASTContext.cpp#3 edit
... //depot/stg/opencl/drivers/opencl/compiler/clang.git/lib/CodeGen/CodeGenModule.cpp#4 edit
... //depot/stg/opencl/drivers/opencl/compiler/clang.git/test/CodeGenCXX/cxx1z-inline-variables.cpp#2 edit
[ROCm/clr commit: a4177b5919]
SWDEV-3 - PR28394: For compatibility with c++11 and c++14, if a static constexpr data
member is redundantly redeclared outside the class definition in code built in
c++17 mode, ensure we emit a non-discardable definition of the data member for
c++11 and c++14 compilations to use.
git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@274416 91177308-0d34-0410-b5e6-96231b3b80d8
GitHash: f82fb5beb88e841f7a00cfb2a2ceabe46bcb2a9b
Affected files ...
... //depot/stg/opencl/drivers/opencl/compiler/clang.git/include/clang/AST/ASTContext.h#3 edit
... //depot/stg/opencl/drivers/opencl/compiler/clang.git/lib/AST/ASTContext.cpp#3 edit
... //depot/stg/opencl/drivers/opencl/compiler/clang.git/lib/CodeGen/CodeGenModule.cpp#4 edit
... //depot/stg/opencl/drivers/opencl/compiler/clang.git/test/CodeGenCXX/cxx1z-inline-variables.cpp#2 edit
SWDEV-2 - Change OpenCL version number from 2157 to 2158.
Affected files ...
... //depot/stg/opencl/drivers/opencl/runtime/utils/versions.hpp#1904 edit
[ROCm/clr commit: ac7ee9853a]
SWDEV-2 - Change OpenCL version number from 2157 to 2158.
Affected files ...
... //depot/stg/opencl/drivers/opencl/runtime/utils/versions.hpp#1904 edit
SWDEV-3 - AMDGPU: Expand unaligned accesses early
Due to visit order problems, in the case of an unaligned copy
the legalized DAG fails to eliminate extra instructions introduced
by the expansion of both unaligned parts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274397 91177308-0d34-0410-b5e6-96231b3b80d8
GitHash: d4452f8fcf496a2e19c1a1c9792f5f063f4e9703
Affected files ...
... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/lib/Target/AMDGPU/AMDGPUISelLowering.cpp#3 edit
... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/lib/Target/AMDGPU/AMDGPUISelLowering.h#3 edit
... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll#3 edit
... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/test/CodeGen/AMDGPU/sext-in-reg-failure-r600.ll#1 add
... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/test/CodeGen/AMDGPU/sext-in-reg.ll#3 edit
... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/test/CodeGen/AMDGPU/unaligned-load-store.ll#2 edit
[ROCm/clr commit: 739bdacc65]
SWDEV-3 - AMDGPU: Expand unaligned accesses early
Due to visit order problems, in the case of an unaligned copy
the legalized DAG fails to eliminate extra instructions introduced
by the expansion of both unaligned parts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274397 91177308-0d34-0410-b5e6-96231b3b80d8
GitHash: d4452f8fcf496a2e19c1a1c9792f5f063f4e9703
Affected files ...
... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/lib/Target/AMDGPU/AMDGPUISelLowering.cpp#3 edit
... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/lib/Target/AMDGPU/AMDGPUISelLowering.h#3 edit
... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll#3 edit
... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/test/CodeGen/AMDGPU/sext-in-reg-failure-r600.ll#1 add
... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/test/CodeGen/AMDGPU/sext-in-reg.ll#3 edit
... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/test/CodeGen/AMDGPU/unaligned-load-store.ll#2 edit
SWDEV-3 - [msan] Fix __msan_maybe_ for non-standard type sizes.
Fix incorrect calculation of the type size for __msan_maybe_warning_N
call that resulted in an invalid (narrowing) zext instruction and
\"Assertion `castIsValid(op, S, Ty) && \"Invalid cast!\"' failed.\"
Only happens in very large functions (with more than 3500 MSan
checks) operating on integer types that are not power-of-two.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274395 91177308-0d34-0410-b5e6-96231b3b80d8
GitHash: dcfa1b5241a1d0484ad1a67485329b1c7c13b575
Affected files ...
... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/lib/Transforms/Instrumentation/MemorySanitizer.cpp#4 edit
... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/test/Instrumentation/MemorySanitizer/with-call-type-size.ll#1 add
[ROCm/clr commit: 89153addab]
SWDEV-3 - [msan] Fix __msan_maybe_ for non-standard type sizes.
Fix incorrect calculation of the type size for __msan_maybe_warning_N
call that resulted in an invalid (narrowing) zext instruction and
\"Assertion `castIsValid(op, S, Ty) && \"Invalid cast!\"' failed.\"
Only happens in very large functions (with more than 3500 MSan
checks) operating on integer types that are not power-of-two.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274395 91177308-0d34-0410-b5e6-96231b3b80d8
GitHash: dcfa1b5241a1d0484ad1a67485329b1c7c13b575
Affected files ...
... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/lib/Transforms/Instrumentation/MemorySanitizer.cpp#4 edit
... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/test/Instrumentation/MemorySanitizer/with-call-type-size.ll#1 add
SWDEV-3 - [codeview] Don't record UDTs for anonymous structs
MSVC makes up names for these anonymous structs, but we don't (yet).
Eventually Clang should use getTypedefNameForAnonDecl() to put some name
in the debug info, and we can update the test case when that happens.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274391 91177308-0d34-0410-b5e6-96231b3b80d8
GitHash: 613f19910964eb95a63bd906b0b75d9aa20d9b06
Affected files ...
... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp#5 edit
... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/test/DebugInfo/COFF/udts.ll#2 edit
[ROCm/clr commit: 2a7b7edab9]
SWDEV-3 - [codeview] Don't record UDTs for anonymous structs
MSVC makes up names for these anonymous structs, but we don't (yet).
Eventually Clang should use getTypedefNameForAnonDecl() to put some name
in the debug info, and we can update the test case when that happens.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274391 91177308-0d34-0410-b5e6-96231b3b80d8
GitHash: 613f19910964eb95a63bd906b0b75d9aa20d9b06
Affected files ...
... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/lib/CodeGen/AsmPrinter/CodeViewDebug.cpp#5 edit
... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/test/DebugInfo/COFF/udts.ll#2 edit
SWDEV-3 - IR: Set TargetPrefix for some X86 and AArch64 intrinsics where it was missing
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274390 91177308-0d34-0410-b5e6-96231b3b80d8
GitHash: f0a4c116041f7c2aef7796c8b067f0947b69602d
Affected files ...
... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/include/llvm/IR/IntrinsicsAArch64.td#2 edit
... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/include/llvm/IR/IntrinsicsX86.td#2 edit
[ROCm/clr commit: 162c07fcb4]
SWDEV-3 - IR: Set TargetPrefix for some X86 and AArch64 intrinsics where it was missing
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274390 91177308-0d34-0410-b5e6-96231b3b80d8
GitHash: f0a4c116041f7c2aef7796c8b067f0947b69602d
Affected files ...
... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/include/llvm/IR/IntrinsicsAArch64.td#2 edit
... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/include/llvm/IR/IntrinsicsX86.td#2 edit
SWDEV-3 - Address two correctness issues in LoadStoreVectorizer
Summary:
GetBoundryInstruction returns the last instruction as the instruction which follows or end(). Otherwise the last instruction in the boundry set is not being tested by isVectorizable().
Partially solve reordering of instructions. More extensive solution to follow.
Reviewers: tstellarAMD, llvm-commits, jlebar
Subscribers: escha, arsenm, mzolotukhin
Differential Revision: http://reviews.llvm.org/D21934
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274389 91177308-0d34-0410-b5e6-96231b3b80d8
GitHash: 1e53a5fcec984e0f1cefe43dba3939e4b72a533f
Affected files ...
... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp#11 edit
... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/test/Transforms/LoadStoreVectorizer/AMDGPU/interleaved-mayalias-store.ll#2 edit
... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/test/Transforms/LoadStoreVectorizer/X86/lit.local.cfg#1 add
... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/test/Transforms/LoadStoreVectorizer/X86/preserve-order32.ll#1 add
... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/test/Transforms/LoadStoreVectorizer/X86/preserve-order64.ll#1 add
[ROCm/clr commit: cb7e7442c8]
SWDEV-3 - Address two correctness issues in LoadStoreVectorizer
Summary:
GetBoundryInstruction returns the last instruction as the instruction which follows or end(). Otherwise the last instruction in the boundry set is not being tested by isVectorizable().
Partially solve reordering of instructions. More extensive solution to follow.
Reviewers: tstellarAMD, llvm-commits, jlebar
Subscribers: escha, arsenm, mzolotukhin
Differential Revision: http://reviews.llvm.org/D21934
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274389 91177308-0d34-0410-b5e6-96231b3b80d8
GitHash: 1e53a5fcec984e0f1cefe43dba3939e4b72a533f
Affected files ...
... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/lib/Transforms/Vectorize/LoadStoreVectorizer.cpp#11 edit
... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/test/Transforms/LoadStoreVectorizer/AMDGPU/interleaved-mayalias-store.ll#2 edit
... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/test/Transforms/LoadStoreVectorizer/X86/lit.local.cfg#1 add
... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/test/Transforms/LoadStoreVectorizer/X86/preserve-order32.ll#1 add
... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/test/Transforms/LoadStoreVectorizer/X86/preserve-order64.ll#1 add
SWDEV-3 - [PM] Preparatory cleanups to ArgumentPromotion.
This pulls some obvious changes out of http://reviews.llvm.org/D21921 to
minimize the diff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274445 91177308-0d34-0410-b5e6-96231b3b80d8
GitHash: 197a7516a32b69da7d1243308cb8eb6c5f29de0c
Affected files ...
... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/lib/Transforms/IPO/ArgumentPromotion.cpp#2 edit
[ROCm/clr commit: 719ebdcc13]
SWDEV-3 - [PM] Preparatory cleanups to ArgumentPromotion.
This pulls some obvious changes out of http://reviews.llvm.org/D21921 to
minimize the diff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274445 91177308-0d34-0410-b5e6-96231b3b80d8
GitHash: 197a7516a32b69da7d1243308cb8eb6c5f29de0c
Affected files ...
... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/lib/Transforms/IPO/ArgumentPromotion.cpp#2 edit
SWDEV-3 - [PM] Fix a small typo from when I ported JumpThreading
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274440 91177308-0d34-0410-b5e6-96231b3b80d8
GitHash: ea9886a5909183770b8d0baa9061150adf664b1a
Affected files ...
... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/lib/Transforms/Scalar/JumpThreading.cpp#2 edit
SWDEV-3 - [Hexagon] Create global std::map lazily.
This could of course be a simple binary search with no global state
involved at all if someone cares enough. Just don't make everyone
linking the hexagon backend pay for it on process startup and shutdown.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274437 91177308-0d34-0410-b5e6-96231b3b80d8
GitHash: b4e53350f9349677e2a0178bde5b8b0c3b743b5e
Affected files ...
... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp#2 edit
[ROCm/clr commit: d32e5e2c1f]
SWDEV-3 - [Hexagon] Create global std::map lazily.
This could of course be a simple binary search with no global state
involved at all if someone cares enough. Just don't make everyone
linking the hexagon backend pay for it on process startup and shutdown.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274437 91177308-0d34-0410-b5e6-96231b3b80d8
GitHash: b4e53350f9349677e2a0178bde5b8b0c3b743b5e
Affected files ...
... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp#2 edit
SWDEV-3 - CodeGen: Use MachineInstr& in SlotIndexes.cpp, NFC
Avoid implicit conversions from iterator to pointer by preferring
MachineInstr& and using range-based for loops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274354 91177308-0d34-0410-b5e6-96231b3b80d8
GitHash: effa4cc200078395a74decd1ae2d1e380c79a2f7
Affected files ...
... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/lib/CodeGen/SlotIndexes.cpp#2 edit
[ROCm/clr commit: e6f8cce17c]
SWDEV-3 - CodeGen: Use MachineInstr& in SlotIndexes.cpp, NFC
Avoid implicit conversions from iterator to pointer by preferring
MachineInstr& and using range-based for loops.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274354 91177308-0d34-0410-b5e6-96231b3b80d8
GitHash: effa4cc200078395a74decd1ae2d1e380c79a2f7
Affected files ...
... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/lib/CodeGen/SlotIndexes.cpp#2 edit
SWDEV-3 - CodeGen: Use MachineInstr& in RegAllocFast, NFC
Use MachineInstr& instead of MachineInstr* in RegAllocFast to avoid
implicit conversions from MachineInstrBundleIterator. RAFast::spillAll
and RAFast::spillVirtReg still take iterators, since their argument may
be an end iterator from MachineBasicBlock::getFirstTerminator.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274353 91177308-0d34-0410-b5e6-96231b3b80d8
GitHash: ce5fdc00e7ed9f05c643b056d0561a8133b5438b
Affected files ...
... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/lib/CodeGen/RegAllocFast.cpp#2 edit
[ROCm/clr commit: b846d72de1]
SWDEV-3 - CodeGen: Use MachineInstr& in RegAllocFast, NFC
Use MachineInstr& instead of MachineInstr* in RegAllocFast to avoid
implicit conversions from MachineInstrBundleIterator. RAFast::spillAll
and RAFast::spillVirtReg still take iterators, since their argument may
be an end iterator from MachineBasicBlock::getFirstTerminator.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@274353 91177308-0d34-0410-b5e6-96231b3b80d8
GitHash: ce5fdc00e7ed9f05c643b056d0561a8133b5438b
Affected files ...
... //depot/stg/opencl/drivers/opencl/compiler/llvm.git/lib/CodeGen/RegAllocFast.cpp#2 edit
Sylvain Jeaugey
foreman