76333 Commits

Author SHA1 Message Date
Shweta Khatri 6361466baa rocr: Use view3dAs2dArray flag, for thick/3D swizzle modes.
Added HSA_IMAGE_ENABLE_3D_SWIZZLE_DEBUG environment flag to
enable/disable this. Default value is false (view3dAs2dArray = 1)
Enabling this flag will enable support for swizzles that do 3D
interleaving. Note that all features of 3D images are supported
with 2D swizzles,it's just that the access patterns are different
and therefore cache hit-rates may be better or worse, depending
on how it's used. Volumetric algorithms do better with 3D and apps
that tend to access a single slice at a time do better with 2D.

Change-Id: Id8574a6710fe4333a1ee331e5ce9195a81434198
2025-01-27 09:28:33 -05:00
Shweta Khatri 4325142db1 rocr: Use view3dAs2dArray flag, for thick/3D swizzle modes.
Added HSA_IMAGE_ENABLE_3D_SWIZZLE_DEBUG environment flag to
enable/disable this. Default value is false (view3dAs2dArray = 1)
Enabling this flag will enable support for swizzles that do 3D
interleaving. Note that all features of 3D images are supported
with 2D swizzles,it's just that the access patterns are different
and therefore cache hit-rates may be better or worse, depending
on how it's used. Volumetric algorithms do better with 3D and apps
that tend to access a single slice at a time do better with 2D.

Change-Id: Id8574a6710fe4333a1ee331e5ce9195a81434198


[ROCm/ROCR-Runtime commit: 6361466baa]
2025-01-27 09:28:33 -05:00
Tony Gutierrez 8a38f121ea rocr: Add WaitMultiple to core Signal
Replaces WaitAny with WaitMultiple to more closely align with the
underlying driver API for waiting on multiple events.

WaitMultiple adds a single parameter, wait_on_all, to the WaitAny
interface providing a single function for waiting on multiple
events when we only need AND and OR semantics for the signal
checking logic.

Change-Id: I68a4a45d48151d9d69aef02fd8f7263b9e6c0e75
2025-01-27 09:21:43 -05:00
Tony Gutierrez ff52d6fc13 rocr: Add WaitMultiple to core Signal
Replaces WaitAny with WaitMultiple to more closely align with the
underlying driver API for waiting on multiple events.

WaitMultiple adds a single parameter, wait_on_all, to the WaitAny
interface providing a single function for waiting on multiple
events when we only need AND and OR semantics for the signal
checking logic.

Change-Id: I68a4a45d48151d9d69aef02fd8f7263b9e6c0e75


[ROCm/ROCR-Runtime commit: 8a38f121ea]
2025-01-27 09:21:43 -05:00
Ioannis Assiouras aaecd3e058 SWDEV-493278 - Fix error codes in Unit_hipStreamBatchMemOp_Negative_Tests
Change-Id: I560da08d94b2ec41bbb5d5dc96561b79daa410a5


[ROCm/hip-tests commit: 22946cd158]
2025-01-27 14:00:24 +00:00
Ioannis Assiouras 22946cd158 SWDEV-493278 - Fix error codes in Unit_hipStreamBatchMemOp_Negative_Tests
Change-Id: I560da08d94b2ec41bbb5d5dc96561b79daa410a5
2025-01-27 14:00:24 +00:00
Aryan Salmanpour 2f754d1ffb Eliminate the use of std::fs (#497)
[ROCm/rocdecode commit: bca75cf2b7]
2025-01-27 08:10:11 -05:00
Aryan Salmanpour bca75cf2b7 Eliminate the use of std::fs (#497) 2025-01-27 08:10:11 -05:00
Sylvain Jeaugey 70bd1af305 NCCL 2.25.1-1
Add Blackwell/SM100 support
 * Add compilation for sm100
 * Add graph search speeds for Blackwell
 * Optimize graph search to converge on large NVLink domains
 * Limit NVLS heads to 32
 * Increase various limits to fit large NVLink domains
 * Add extra checks for IMEX setup, needed for MNNVL
 * Increase MAXCHANNELS to 64

Extend NVTX instrumentation to track NCCL communicators
 * Add communicator ID to NVTX traces to allow for correlation
   between ranks.

RAS fixes


[ROCm/rccl commit: 80f6bda437]
2025-01-27 03:33:57 -08:00
Sylvain Jeaugey 80f6bda437 NCCL 2.25.1-1
Add Blackwell/SM100 support
 * Add compilation for sm100
 * Add graph search speeds for Blackwell
 * Optimize graph search to converge on large NVLink domains
 * Limit NVLS heads to 32
 * Increase various limits to fit large NVLink domains
 * Add extra checks for IMEX setup, needed for MNNVL
 * Increase MAXCHANNELS to 64

Extend NVTX instrumentation to track NCCL communicators
 * Add communicator ID to NVTX traces to allow for correlation
   between ranks.

RAS fixes
2025-01-27 03:33:57 -08:00
Marko Arandjelovic 8b956db8db SWDEV-489619 - Added checks for memcpy capture path
Change-Id: I0e156099282f0b6393bcbcee2e9b96c31034a851


[ROCm/clr commit: 269ec54252]
2025-01-27 03:51:34 -05:00
Marko Arandjelovic 269ec54252 SWDEV-489619 - Added checks for memcpy capture path
Change-Id: I0e156099282f0b6393bcbcee2e9b96c31034a851
2025-01-27 03:51:34 -05:00
Jacob Lambert d7371306b0 SWDEV-360440 - Prepare CLR CMake for Comgr V3 transition
Change-Id: Ia279928fd3549a45bae561d0d2d8fcf110d8c245


[ROCm/clr commit: 1fc7c6bb9a]
2025-01-27 01:09:23 -05:00
Jacob Lambert 1fc7c6bb9a SWDEV-360440 - Prepare CLR CMake for Comgr V3 transition
Change-Id: Ia279928fd3549a45bae561d0d2d8fcf110d8c245
2025-01-27 01:09:23 -05:00
Lancelot Six c51aa0d155 libhsakmt: Use the node info to determine LDS size
The CWSR area size needs to take into account the size of LDS each
active workgroup can have.  The current implementation uses a constant
for that.  This patch refactors this to use the HsaNodeProperties of the
device's the CWSR area is for to figure out the size of LDS.

Change-Id: Ib8585b2b7140ec5c99e7b7d62e67f785697c028a
Signed-off-by: Lancelot Six <Lancelot.Six@amd.com>
Signed-off-by: Amber Lin <Amber.Lin@amd.com>
2025-01-26 21:46:32 -05:00
Lancelot Six c7b1fd714e libhsakmt: Use the node info to determine LDS size
The CWSR area size needs to take into account the size of LDS each
active workgroup can have.  The current implementation uses a constant
for that.  This patch refactors this to use the HsaNodeProperties of the
device's the CWSR area is for to figure out the size of LDS.

Change-Id: Ib8585b2b7140ec5c99e7b7d62e67f785697c028a
Signed-off-by: Lancelot Six <Lancelot.Six@amd.com>
Signed-off-by: Amber Lin <Amber.Lin@amd.com>


[ROCm/ROCR-Runtime commit: c51aa0d155]
2025-01-26 21:46:32 -05:00
Alex Sierra 268054cd28 kfdtest: add support for gfx9.5.0 in shader store
Signed-off-by: Alex Sierra <alex.sierra@amd.com>
Change-Id: I48b98ff631bd1aa1a044b60583ff256e43b17423
2025-01-26 21:45:07 -05:00
Alex Sierra da483d7588 kfdtest: add support for gfx9.5.0 in shader store
Signed-off-by: Alex Sierra <alex.sierra@amd.com>
Change-Id: I48b98ff631bd1aa1a044b60583ff256e43b17423


[ROCm/ROCR-Runtime commit: 268054cd28]
2025-01-26 21:45:07 -05:00
Alex Sierra e94ff8a36c kfdtest: Add gfx 9.5 as FAMILY_AV
Signed-off-by: Alex Sierra <alex.sierra@amd.com>
Change-Id: Ib5696eee1d4f64c9c87d714eae7c80fbbd1e2b23
2025-01-26 21:43:55 -05:00
Alex Sierra 840a613723 kfdtest: Add gfx 9.5 as FAMILY_AV
Signed-off-by: Alex Sierra <alex.sierra@amd.com>
Change-Id: Ib5696eee1d4f64c9c87d714eae7c80fbbd1e2b23


[ROCm/ROCR-Runtime commit: e94ff8a36c]
2025-01-26 21:43:55 -05:00
David Yat Sin dab8f2fc65 rocr: Add support for gfx950
<squashed with patch for gfx950 generic targets>

Signed-off-by: Chris Freehill <Chris.Freehill@amd.com>

Change-Id: Ifec6d93cf46c7fbf736c6572882299e279260af6
2025-01-26 13:04:58 -05:00
David Yat Sin d0ae8b2eb5 rocr: Add support for gfx950
<squashed with patch for gfx950 generic targets>

Signed-off-by: Chris Freehill <Chris.Freehill@amd.com>

Change-Id: Ifec6d93cf46c7fbf736c6572882299e279260af6


[ROCm/ROCR-Runtime commit: dab8f2fc65]
2025-01-26 13:04:58 -05:00
Vladana Stojiljkovic 08e2b6a15d SWDEV-486969 - Reuse existing tests to verify behavior of capturing sync Memcpy APis
Change-Id: I7e94743d6957ffaadae9cff297e3f0d93f9ff806


[ROCm/hip-tests commit: 6c5468f802]
2025-01-26 07:56:32 -05:00
Vladana Stojiljkovic 6c5468f802 SWDEV-486969 - Reuse existing tests to verify behavior of capturing sync Memcpy APis
Change-Id: I7e94743d6957ffaadae9cff297e3f0d93f9ff806
2025-01-26 07:56:32 -05:00
Vladana Stojiljkovic cfc21116a6 SWDEV-491280 - Create capture tests for Peer APIs
Change-Id: Ib35ab1155b19e00f7f297e6eaf395709d5767d7c


[ROCm/hip-tests commit: 59ace1e080]
2025-01-26 07:56:15 -05:00
Vladana Stojiljkovic 59ace1e080 SWDEV-491280 - Create capture tests for Peer APIs
Change-Id: Ib35ab1155b19e00f7f297e6eaf395709d5767d7c
2025-01-26 07:56:15 -05:00
David Addison 6f2e0f8a21 Update CUDA gencodes
Add support for Blackwell sm100 and sm120 from CUDA 12.8

Add support for Hopper sm90 from CUDA 12.0


[ROCm/rccl-tests commit: cb6a46fdd6]
2025-01-25 17:32:16 -08:00
David Addison cb6a46fdd6 Update CUDA gencodes
Add support for Blackwell sm100 and sm120 from CUDA 12.8

Add support for Hopper sm90 from CUDA 12.0
2025-01-25 17:32:16 -08:00
Ioannis Assiouras 8169855390 SWDEV-510319 - Fixed random segfaults in graph tests
This change fixes random segfaults in graph tests that
are seen after the change make internal callbacks non-blocking.
The callback thread that decreases the GraphExec ref count
may now run after the runtime shutdown. This can cause a segfault
because the hip::device that is accessed in GraphExec destructor
is already destroyed during runtime shutdown. This patch ensures
that the hip::device object  stays alive until after the
callback thread completes.

Change-Id: I75a6ac01f27a0b2250bbd10ed389ebfb322927af


[ROCm/clr commit: 21c223f8df]
2025-01-25 09:54:15 -05:00
Ioannis Assiouras 21c223f8df SWDEV-510319 - Fixed random segfaults in graph tests
This change fixes random segfaults in graph tests that
are seen after the change make internal callbacks non-blocking.
The callback thread that decreases the GraphExec ref count
may now run after the runtime shutdown. This can cause a segfault
because the hip::device that is accessed in GraphExec destructor
is already destroyed during runtime shutdown. This patch ensures
that the hip::device object  stays alive until after the
callback thread completes.

Change-Id: I75a6ac01f27a0b2250bbd10ed389ebfb322927af
2025-01-25 09:54:15 -05:00
Sam Wu c95cfc9bd8 Update documentation requirements (#540)
[ROCm/rocprofiler-compute commit: f58070aff1]
2025-01-24 16:34:03 -07:00
Sam Wu f58070aff1 Update documentation requirements (#540) 2025-01-24 16:34:03 -07:00
Sourabh Betigeri e3c4a81b69 SWDEV-502219 - Adds validity checks for negative parameters passed
Change-Id: Ib8a531533306a27143d74b81c074de81051eb896


[ROCm/clr commit: c460b0541b]
2025-01-24 16:32:29 -05:00
Sourabh Betigeri c460b0541b SWDEV-502219 - Adds validity checks for negative parameters passed
Change-Id: Ib8a531533306a27143d74b81c074de81051eb896
2025-01-24 16:32:29 -05:00
Ajay d0d2204a53 SWDEV-465215 - fixes for hipFuncGetAttribute tests
Fixes SWDEV-465215, SWDEV-465213, SWDEV-465212

Change-Id: I08b114bf647366abcf900d6b2a17f77ca608fc46


[ROCm/hip-tests commit: 6059eaa7c1]
2025-01-24 16:08:09 -05:00
Ajay 6059eaa7c1 SWDEV-465215 - fixes for hipFuncGetAttribute tests
Fixes SWDEV-465215, SWDEV-465213, SWDEV-465212

Change-Id: I08b114bf647366abcf900d6b2a17f77ca608fc46
2025-01-24 16:08:09 -05:00
Tao Sang 2a5f431380 SWDEV-479138 - Enable different address modes
Enable different address modes in tests

Change-Id: Idf69477718172614ba9c349735d3230ae765923b


[ROCm/hip-tests commit: 58d4bd27a3]
2025-01-24 13:49:27 -05:00
Tao Sang 58d4bd27a3 SWDEV-479138 - Enable different address modes
Enable different address modes in tests

Change-Id: Idf69477718172614ba9c349735d3230ae765923b
2025-01-24 13:49:27 -05:00
SrinivasaRao 93b661d9b0 SWDEV-493278-[catch2][dtest]-Negative Tests for the hipStreamBatchMemOp API
Change-Id: I408aa01e279817b44ff05571f3251a281dd5a4f6


[ROCm/hip-tests commit: 7d2ed4bd39]
2025-01-24 13:47:16 -05:00
SrinivasaRao 7d2ed4bd39 SWDEV-493278-[catch2][dtest]-Negative Tests for the hipStreamBatchMemOp API
Change-Id: I408aa01e279817b44ff05571f3251a281dd5a4f6
2025-01-24 13:47:16 -05:00
Rambabu Swargam ce3f70c1d5 SWDEV-506876 - [catch2][dtest] Enable stress tests for hipStreamLegacy
Change-Id: Ica8d0e68f4ec19af48d6d417f018b9d8f375125d


[ROCm/hip-tests commit: 94f5907371]
2025-01-24 13:34:29 -05:00
Rambabu Swargam 94f5907371 SWDEV-506876 - [catch2][dtest] Enable stress tests for hipStreamLegacy
Change-Id: Ica8d0e68f4ec19af48d6d417f018b9d8f375125d
2025-01-24 13:34:29 -05:00
Jaydeep Patel 569616832a SWDEV-496544 - Memory needs visibility system wide as CPU and GPU both needs to see updated value by each other.
Change-Id: Ia80e69455aeb06b9281f75313ba39b621d6929c5


[ROCm/hip-tests commit: 5244a426c7]
2025-01-24 13:28:17 -05:00
Jaydeep Patel 5244a426c7 SWDEV-496544 - Memory needs visibility system wide as CPU and GPU both needs to see updated value by each other.
Change-Id: Ia80e69455aeb06b9281f75313ba39b621d6929c5
2025-01-24 13:28:17 -05:00
Tao Sang 2d122ae751 SWDEV-506090 - Fix Unit_hipMemAdvise_TstAlignedAllocMem
Change-Id: I651c25f011d24d0190c62586722b81ddc580655f


[ROCm/hip-tests commit: 5f2992a546]
2025-01-24 13:16:27 -05:00
Tao Sang 5f2992a546 SWDEV-506090 - Fix Unit_hipMemAdvise_TstAlignedAllocMem
Change-Id: I651c25f011d24d0190c62586722b81ddc580655f
2025-01-24 13:16:27 -05:00
Galantsev, Dmitrii 99d4d77e20 CMAKE - Move rdc_options into share/rdc/conf/
Change-Id: Ib2e792aef180f0f267d86d68c57b852b2cdc8ea6
Signed-off-by: Galantsev, Dmitrii <dmitrii.galantsev@amd.com>
2025-01-24 12:06:05 -06:00
Galantsev, Dmitrii d5ce61d95e CMAKE - Move rdc_options into share/rdc/conf/
Change-Id: Ib2e792aef180f0f267d86d68c57b852b2cdc8ea6
Signed-off-by: Galantsev, Dmitrii <dmitrii.galantsev@amd.com>


[ROCm/rdc commit: 99d4d77e20]
2025-01-24 12:06:05 -06:00
Ben Vanik 7d64fe49fa rocr: Fix HostQueue to obey the alignment requirement
Change-Id: I06542e9ff94e826ca0abba0328b301fec50a95ea
2025-01-24 12:08:11 -05:00
Ben Vanik bda034bb82 rocr: Fix HostQueue to obey the alignment requirement
Change-Id: I06542e9ff94e826ca0abba0328b301fec50a95ea


[ROCm/ROCR-Runtime commit: 7d64fe49fa]
2025-01-24 12:08:11 -05:00