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Автор SHA1 Сообщение Дата
avinashkethineedi 10eb11c1d5 Use C++ iota function to reset buffers and use its values for verification 
* Update functional test script to include new tests


[ROCm/rocshmem commit: 18a1bdd0ac]
 2024-10-15 20:23:25 +00:00
avinashkethineedi 18a1bdd0ac Use C++ iota function to reset buffers and use its values for verification 
* Update functional test script to include new tests
 2024-10-15 20:23:25 +00:00
Joe Narlo b5887c2f05 SWDEV-487604 [AMD SMI][Unified Header] integration_test.py is failing with unified header 
The script generator.py was not handling all of the anonymous and unnamed structures.
Logic was added to correct the errors seen in the script amdsmi_wrapper.py

Removed adding _ to structure definitions

Change-Id: I51958d23b3da40ec67e883e13dc74feaeaf1d58e
Signed-off-by: Joe Narlo <Joseph.Narlo@amd.com>
 2024-10-15 16:22:02 -04:00
Joe Narlo 06ef0819a3 SWDEV-487604 [AMD SMI][Unified Header] integration_test.py is failing with unified header 
The script generator.py was not handling all of the anonymous and unnamed structures.
Logic was added to correct the errors seen in the script amdsmi_wrapper.py

Removed adding _ to structure definitions

Change-Id: I51958d23b3da40ec67e883e13dc74feaeaf1d58e
Signed-off-by: Joe Narlo <Joseph.Narlo@amd.com>


[ROCm/amdsmi commit: b5887c2f05]
 2024-10-15 16:22:02 -04:00
David Yat Sin d58c9dea0a rocr: Add executable flag for memory allocations 
Change-Id: I8307cd3562c3ab9c12fef8c457a59916e33b7923
 2024-10-15 16:52:00 +00:00
David Yat Sin 35187a00df rocr: Add executable flag for memory allocations 
Change-Id: I8307cd3562c3ab9c12fef8c457a59916e33b7923


[ROCm/ROCR-Runtime commit: d58c9dea0a]
 2024-10-15 16:52:00 +00:00
David Galiffi 489eda995d Rename Omnitrace to ROCm Systems Profiler (#4) 
The Omnitrace program is being renamed. 

Full name: "ROCm Systems Profiler"
Package name: "rocprofiler-systems"
Binary / Library names: "rocprof-sys-*"

---------
Co-authored-by: Xuan Chen <xuchen@amd.com>
Signed-off-by: David Galiffi <David.Galiffi@amd.com>

[ROCm/rocprofiler-systems commit: d07bf508a9]
 2024-10-15 11:20:40 -04:00
David Galiffi d07bf508a9 Rename Omnitrace to ROCm Systems Profiler (#4) 
The Omnitrace program is being renamed. 

Full name: "ROCm Systems Profiler"
Package name: "rocprofiler-systems"
Binary / Library names: "rocprof-sys-*"

---------
Co-authored-by: Xuan Chen <xuchen@amd.com>
Signed-off-by: David Galiffi <David.Galiffi@amd.com>
 2024-10-15 11:20:40 -04:00
Wenkai Du bd0cdf5a50 Add back missing net flush (#1376) 
[ROCm/rccl commit: c8d3543d3f]
 2024-10-15 08:12:26 -07:00
Wenkai Du c8d3543d3f Add back missing net flush (#1376) 2024-10-15 08:12:26 -07:00
sdashmiz 4432d9458f SWDEV-462585 - Add initial test for hipStreamLegacy 
Signed-off-by: sdashmiz <shadi.dashmiz@amd.com>
Change-Id: Idf38f2e8c49e9011ede73e6222db68ccdc74ed80


[ROCm/hip-tests commit: 4e4cde6d70]
 2024-10-15 11:11:12 -04:00
sdashmiz 4e4cde6d70 SWDEV-462585 - Add initial test for hipStreamLegacy 
Signed-off-by: sdashmiz <shadi.dashmiz@amd.com>
Change-Id: Idf38f2e8c49e9011ede73e6222db68ccdc74ed80
 2024-10-15 11:11:12 -04:00
Ajay b747d0986f SWDEV-482751 - add distro path to find package AMD_ICD 
Change-Id: I0d21f6ba6ade3ed932b134da503f639fd5d0d552


[ROCm/clr commit: ff306ce9d8]
 2024-10-14 15:27:34 -07:00
Ajay ff306ce9d8 SWDEV-482751 - add distro path to find package AMD_ICD 
Change-Id: I0d21f6ba6ade3ed932b134da503f639fd5d0d552
 2024-10-14 15:27:34 -07:00
Wenkai Du 5f8571dcbc msccl: disable 1-shot xmls (#1375) 
MSCCL 1-shot xmls may cause different output values on different ranks.
Disabling them for now to avoid undefined behavior in applications.

[ROCm/rccl commit: 62d10fdc25]
 2024-10-14 15:10:53 -07:00
Wenkai Du 62d10fdc25 msccl: disable 1-shot xmls (#1375) 
MSCCL 1-shot xmls may cause different output values on different ranks.
Disabling them for now to avoid undefined behavior in applications.
 2024-10-14 15:10:53 -07:00
Manjunath-Jakaraddi f84ecfe99b SWDEV-481162: Updating MfmaUtil metric RDC 
Change-Id: I60efa183edc14b6f870f7b6a82f223ea2c9789e5
 2024-10-14 16:48:56 -05:00
Manjunath-Jakaraddi 17fac40bae SWDEV-481162: Updating MfmaUtil metric RDC 
Change-Id: I60efa183edc14b6f870f7b6a82f223ea2c9789e5


[ROCm/rocprofiler commit: f84ecfe99b]
 2024-10-14 16:48:56 -05:00
Avinash Kethineedi 1a5536bfaa Merge branch 'ROCm:develop' into functional_tests/puts_gets 
[ROCm/rocshmem commit: e981f61693]
 2024-10-14 10:27:54 -05:00
Avinash Kethineedi e981f61693 Merge branch 'ROCm:develop' into functional_tests/puts_gets 2024-10-14 10:27:54 -05:00
Khader Basha Shaik 8308ede9e8 amdsmi [CPU]: Add implementation to get cpu handles and core handles API 
- Update the API names, parameters to return cpu handles and core
handles in the system.
  - Update the amdsmi_wrapper.py.
  - Update the amdsmi_interface.py to use the processor handles and
    core handles API.

Change-Id: Ie24f62f345864f8b6773fdb3c6369993bca7e25b
 2024-10-14 05:41:19 -04:00
Khader Basha Shaik 806d1a25c3 amdsmi [CPU]: Add implementation to get cpu handles and core handles API 
- Update the API names, parameters to return cpu handles and core
handles in the system.
  - Update the amdsmi_wrapper.py.
  - Update the amdsmi_interface.py to use the processor handles and
    core handles API.

Change-Id: Ie24f62f345864f8b6773fdb3c6369993bca7e25b


[ROCm/amdsmi commit: 8308ede9e8]
 2024-10-14 05:41:19 -04:00
Wenkai Du 9ad1fe571b Temporarily disable MSCCL all gather XMLs due to UT failure (#1373) 
[ROCm/rccl commit: a680e329e6]
 2024-10-12 08:43:16 -07:00
Wenkai Du a680e329e6 Temporarily disable MSCCL all gather XMLs due to UT failure (#1373) 2024-10-12 08:43:16 -07:00
Giovanni LB e5e2c6041d SWDEV-310289: Adding SPI pipe selection 
Change-Id: I4856d284df3dccaa100a2341211ae09e11c63ecd
 2024-10-12 01:14:49 -04:00
Giovanni LB 896404efb3 SWDEV-310289: Adding SPI pipe selection 
Change-Id: I4856d284df3dccaa100a2341211ae09e11c63ecd


[ROCm/rocprofiler commit: e5e2c6041d]
 2024-10-12 01:14:49 -04:00
Benjamin Welton 6d80088c84 Added FP64_ACTIVE and ENGINE_ACTIVE 
Should replicate DCGM_FI_PROF_EVAL_FLOPS_64 and
DCGM_FI_PROF_GR_ENGINE_ACTIVE respectively. See
https://ontrack-internal.amd.com/browse/SWDEV-490046
and
https://ontrack-internal.amd.com/browse/SWDEV-490031

Change-Id: Ia79f6a1601beac48a350493f2e83ce322c1d8d33
 2024-10-11 15:51:09 -07:00
Benjamin Welton 4dd298f312 Added FP64_ACTIVE and ENGINE_ACTIVE 
Should replicate DCGM_FI_PROF_EVAL_FLOPS_64 and
DCGM_FI_PROF_GR_ENGINE_ACTIVE respectively. See
https://ontrack-internal.amd.com/browse/SWDEV-490046
and
https://ontrack-internal.amd.com/browse/SWDEV-490031

Change-Id: Ia79f6a1601beac48a350493f2e83ce322c1d8d33


[ROCm/rocprofiler commit: 6d80088c84]
 2024-10-11 15:51:09 -07:00
Yiltan Hassan Temucin 31fe937259 updated atomic_fetch() parameters 
[ROCm/rocshmem commit: 8b3854b252]
 2024-10-11 13:34:28 -07:00
Yiltan Hassan Temucin 8b3854b252 updated atomic_fetch() parameters 2024-10-11 13:34:28 -07:00
Yiltan Hassan Temucin 3d0fca0387 updated *_wait* APIs to use int rather than roc_shmem_cmps 
[ROCm/rocshmem commit: 722a5f0731]
 2024-10-11 13:34:28 -07:00
Yiltan Hassan Temucin 722a5f0731 updated *_wait* APIs to use int rather than roc_shmem_cmps 2024-10-11 13:34:28 -07:00
Yiltan Hassan Temucin 496f06dd2b *_wait* routines changed parameter from ptr to ivars to match OpenSHMEM 
[ROCm/rocshmem commit: bcf3fdff10]
 2024-10-11 13:34:28 -07:00
Yiltan Hassan Temucin bcf3fdff10 *_wait* routines changed parameter from ptr to ivars to match OpenSHMEM 2024-10-11 13:34:28 -07:00
coleramos425 38df31b863 Update CODEOWNERS for product team 
Signed-off-by: coleramos425 <colramos@amd.com>


[ROCm/rocprofiler-compute commit: e633d17372]
 2024-10-11 20:25:43 +00:00
coleramos425 e633d17372 Update CODEOWNERS for product team 
Signed-off-by: coleramos425 <colramos@amd.com>
 2024-10-11 20:25:43 +00:00
German Andryeyev faea40cbb3 SWDEV-486602 - Optimize HSA callback performance 
- Don't generate callbacks for HIP events
- Don't process profiling info in the callback for HIP events
- Wait for CPU status update of the submitted commands
every 50 calls. That will allow to drain the commands and
destroy HSA signals.

Change-Id: Ib601a350e7e7c2b6c6209a172385389baccf73a9


[ROCm/clr commit: 364dfb0ed1]
 2024-10-11 14:50:25 -04:00
German Andryeyev 364dfb0ed1 SWDEV-486602 - Optimize HSA callback performance 
- Don't generate callbacks for HIP events
- Don't process profiling info in the callback for HIP events
- Wait for CPU status update of the submitted commands
every 50 calls. That will allow to drain the commands and
destroy HSA signals.

Change-Id: Ib601a350e7e7c2b6c6209a172385389baccf73a9
 2024-10-11 14:50:25 -04:00
Brandon Potter 7f19a42778 Merge branch 'ROCm:develop' into ipc_parameterized_simple_tests_10-01-24 
[ROCm/rocshmem commit: ce0ca36d37]
 2024-10-11 12:49:56 -05:00
Brandon Potter ce0ca36d37 Merge branch 'ROCm:develop' into ipc_parameterized_simple_tests_10-01-24 2024-10-11 12:49:56 -05:00
Wenkai Du 09acdb6b49 Allow zero byte sendrecv in alltoallv (#1349) 
* Allow zero byte sendrecv in alltoallv

* Fix previous merge error

[ROCm/rccl commit: 821d2e1f30]
 2024-10-11 10:40:32 -07:00
Wenkai Du 821d2e1f30 Allow zero byte sendrecv in alltoallv (#1349) 
* Allow zero byte sendrecv in alltoallv

* Fix previous merge error
 2024-10-11 10:40:32 -07:00
Brandon Potter 5b47cf482d Merge pull request #29 from ROCm/improve-ib-latency 
Vectorize WQE segments writes

[ROCm/rocshmem commit: e419a8b963]
 2024-10-11 11:55:48 -05:00
Brandon Potter e419a8b963 Merge pull request #29 from ROCm/improve-ib-latency 
Vectorize WQE segments writes
 2024-10-11 11:55:48 -05:00
Yiltan 9eb928d520 Merge pull request #36 from Yiltan/LWPRHMEM-71-add-coop-groups 
Add cooperative groups for sync collective

[ROCm/rocshmem commit: 8015a453ff]
 2024-10-11 12:55:33 -04:00
Yiltan 8015a453ff Merge pull request #36 from Yiltan/LWPRHMEM-71-add-coop-groups 
Add cooperative groups for sync collective
 2024-10-11 12:55:33 -04:00
Wenkai Du 4cd1b3a9f5 Improve model matching for GPUs with alltoall XGMI connection (#1372) 
[ROCm/rccl commit: 5c367a21d0]
 2024-10-11 09:53:14 -07:00
Wenkai Du 5c367a21d0 Improve model matching for GPUs with alltoall XGMI connection (#1372) 2024-10-11 09:53:14 -07:00
Arm Patinyasakdikul ef54dd7cbc Increase default number of channels for MI300A in multi-node scenario. (#1366) 
This commit changed the default of channels of MI300A from 8 upto 24.
This helps bring up multi-node performance to the expected level.

[ROCm/rccl commit: 133ea201cf]
 2024-10-11 11:37:48 -05:00
Arm Patinyasakdikul 133ea201cf Increase default number of channels for MI300A in multi-node scenario. (#1366) 
This commit changed the default of channels of MI300A from 8 upto 24.
This helps bring up multi-node performance to the expected level.
 2024-10-11 11:37:48 -05:00