76333 Commits

Author SHA1 Message Date
Galantsev, Dmitrii f66e4585c7 Fix issues introduced in 41f5a26408
- std=c++.. is not required because CMAKE_CXX_STANDARD is set
- nullptr check breaks the test because we rely on nullptr as an api for
  checking feature availability.
- enum number setting is unnecessary

Change-Id: I393e6dd3f292b7fa4198302f140c0443ba5e50f5
Signed-off-by: Galantsev, Dmitrii <dmitrii.galantsev@amd.com>


[ROCm/amdsmi commit: a099f0682a]
2023-11-03 17:54:35 -05:00
Nusrat Islam b6f47bad7c msccl: remove cases from numReduction switch statement
[ROCm/rccl commit: f545b94d4b]
2023-11-03 16:56:51 -05:00
Nusrat Islam f545b94d4b msccl: remove cases from numReduction switch statement 2023-11-03 16:56:51 -05:00
Rakesh Roy 1f343c299d SWDEV-426219 - Disable Unit_hipLaunchParm on MI100
- Unit_hipLaunchParm fails in integrity test & in PSDB on MI100.
- Disable it until the failure is fixed.

Change-Id: Id055860e067189c0ef85c77583c73269db9d2b51


[ROCm/hip-tests commit: 31dbd1970a]
2023-11-03 14:35:04 -04:00
Rakesh Roy 31dbd1970a SWDEV-426219 - Disable Unit_hipLaunchParm on MI100
- Unit_hipLaunchParm fails in integrity test & in PSDB on MI100.
- Disable it until the failure is fixed.

Change-Id: Id055860e067189c0ef85c77583c73269db9d2b51
2023-11-03 14:35:04 -04:00
gilbertlee-amd d8471eaddf Adding LaunchBench tool (#952)
[ROCm/rccl commit: d50bab28bf]
2023-11-03 12:04:52 -06:00
gilbertlee-amd d50bab28bf Adding LaunchBench tool (#952) 2023-11-03 12:04:52 -06:00
Wenkai Du 1557a1f258 msccl: use 32-bit LDS access and add RCCL_MSCCL_FORCE_FULLOPS (#953)
[ROCm/rccl commit: bb84345943]
2023-11-03 10:38:02 -07:00
Wenkai Du bb84345943 msccl: use 32-bit LDS access and add RCCL_MSCCL_FORCE_FULLOPS (#953) 2023-11-03 10:38:02 -07:00
gobhardw 9954f937d0 Fixing build for opensuse
Change-Id: I7b68382224221e899f64c06cec67b969a212f21a
2023-11-03 17:04:08 +00:00
gobhardw 67e16c37c1 Fixing build for opensuse
Change-Id: I7b68382224221e899f64c06cec67b969a212f21a


[ROCm/rocprofiler commit: 9954f937d0]
2023-11-03 17:04:08 +00:00
Julia Jiang 8717d01588 SWDEV-368819 - Adding more info for hip memory APIs
Change-Id: Ia1ab540580cd8a2967263adcb23c888007a22ac6


[ROCm/hip commit: d1d95ca0db]
2023-11-03 12:01:07 -04:00
Julia Jiang d1d95ca0db SWDEV-368819 - Adding more info for hip memory APIs
Change-Id: Ia1ab540580cd8a2967263adcb23c888007a22ac6
2023-11-03 12:01:07 -04:00
akolliasAMD 4cd86b185c MSCCL stream fix (#948)
[ROCm/rccl commit: 988efe605a]
2023-11-03 09:10:52 -06:00
akolliasAMD 988efe605a MSCCL stream fix (#948) 2023-11-03 09:10:52 -06:00
Bill(Shuzhou) Liu 1ab4110d46 RDC crash when exit
Join the signal handling thread instead of cancel it to prevent
crash with "terminate called without an active exception".

Change-Id: I2e18eb825728fd3a94f67b1b0049516bb7b6ebbc
2023-11-03 09:10:22 -04:00
Bill(Shuzhou) Liu a59c9e655b RDC crash when exit
Join the signal handling thread instead of cancel it to prevent
crash with "terminate called without an active exception".

Change-Id: I2e18eb825728fd3a94f67b1b0049516bb7b6ebbc


[ROCm/rdc commit: 1ab4110d46]
2023-11-03 09:10:22 -04:00
Ammar ELWazir 489bef5ed1 Update .gitignore (#33)
* Update .gitignore

* Update .gitignore

[ROCm/rocprofiler-register commit: 6af827cd91]
2023-11-03 07:02:04 -05:00
Ammar ELWazir 6af827cd91 Update .gitignore (#33)
* Update .gitignore

* Update .gitignore
2023-11-03 07:02:04 -05:00
Maisam Arif 816752cde9 Merge amd-dev into amd-master 20231103
Signed-off-by: Maisam Arif <maisarif@amd.com>
Change-Id: If9f6982021b89c8fc41da437b9805eeb61eb5e0a
2023-11-03 05:10:54 -05:00
Maisam Arif bbe7073dee Merge amd-dev into amd-master 20231103
Signed-off-by: Maisam Arif <maisarif@amd.com>
Change-Id: If9f6982021b89c8fc41da437b9805eeb61eb5e0a


[ROCm/amdsmi commit: 816752cde9]
2023-11-03 05:10:54 -05:00
Deepak Mewar 6d46e20598 Updated esmi python wrappers to amdsmi python library
Change-Id: Icf2576926d3649929d2aa580b476a013204daf95
2023-11-03 04:58:19 -04:00
Deepak Mewar 5845c75e51 Updated esmi python wrappers to amdsmi python library
Change-Id: Icf2576926d3649929d2aa580b476a013204daf95


[ROCm/amdsmi commit: 6d46e20598]
2023-11-03 04:58:19 -04:00
Maisam Arif 9bfebc6f1c Handle GPU Not detected
Signed-off-by: Maisam Arif <Maisam.Arif@amd.com>
Change-Id: I988b0dddde23b83c1a8e402233b6aa08ce55d0c7
2023-11-03 04:58:11 -04:00
Maisam Arif 11b1e5fb42 Handle GPU Not detected
Signed-off-by: Maisam Arif <Maisam.Arif@amd.com>
Change-Id: I988b0dddde23b83c1a8e402233b6aa08ce55d0c7


[ROCm/amdsmi commit: 9bfebc6f1c]
2023-11-03 04:58:11 -04:00
Galantsev, Dmitrii fc02ebc5f2 DOCS - Fix 'failed to reach any of the inventories'
Change-Id: I7edd1fad17bd0f3e0946a6712410cf6549afc729
Signed-off-by: Galantsev, Dmitrii <dmitrii.galantsev@amd.com>
2023-11-03 03:59:48 -04:00
Galantsev, Dmitrii 1128c1f246 DOCS - Fix 'failed to reach any of the inventories'
Change-Id: I7edd1fad17bd0f3e0946a6712410cf6549afc729
Signed-off-by: Galantsev, Dmitrii <dmitrii.galantsev@amd.com>


[ROCm/amdsmi commit: fc02ebc5f2]
2023-11-03 03:59:48 -04:00
Galantsev, Dmitrii 1010787865 CMake - Bump version
Change-Id: Idc3c07b5f37309d03b46df7a6400793bc8953f61
Signed-off-by: Galantsev, Dmitrii <dmitrii.galantsev@amd.com>
2023-11-03 03:57:35 -04:00
Galantsev, Dmitrii 9b3d9f61b3 CMake - Bump version
Change-Id: Idc3c07b5f37309d03b46df7a6400793bc8953f61
Signed-off-by: Galantsev, Dmitrii <dmitrii.galantsev@amd.com>


[ROCm/amdsmi commit: 1010787865]
2023-11-03 03:57:35 -04:00
Galantsev, Dmitrii 513dd8a445 Merge rocmsmi/amd-staging into amd-dev 20231103
Change-Id: Ie70ab54a63b25649b6b9d30620c5546dc66cd766
Signed-off-by: Galantsev, Dmitrii <dmitrii.galantsev@amd.com>
2023-11-03 02:55:02 -05:00
Galantsev, Dmitrii e5d0ba249d Merge rocmsmi/amd-staging into amd-dev 20231103
Change-Id: Ie70ab54a63b25649b6b9d30620c5546dc66cd766
Signed-off-by: Galantsev, Dmitrii <dmitrii.galantsev@amd.com>


[ROCm/amdsmi commit: 513dd8a445]
2023-11-03 02:55:02 -05:00
Saleel Kudchadker 5f009b7cb1 SWDEV-422207 - Track commands for capture
- Track all captured commands under a new AccumulateCommand
- Add begin() and end() methods to capture commands
- Explicit TS object now passed to certain methods because
profilingBegin() and profilingEnd() now happen separately and thus can
run into threading issues

Change-Id: I171106bdcad72b057836cb2f3fc398db3533119f


[ROCm/clr commit: 40f41f4d0b]
2023-11-03 05:09:04 +00:00
Saleel Kudchadker 40f41f4d0b SWDEV-422207 - Track commands for capture
- Track all captured commands under a new AccumulateCommand
- Add begin() and end() methods to capture commands
- Explicit TS object now passed to certain methods because
profilingBegin() and profilingEnd() now happen separately and thus can
run into threading issues

Change-Id: I171106bdcad72b057836cb2f3fc398db3533119f
2023-11-03 05:09:04 +00:00
Aryan Salmanpour 0c7e31bbfa Add support for gfx1100 - update the vcn lookup table (#34)
[ROCm/rocdecode commit: f47fd89f62]
2023-11-02 22:05:17 -04:00
Aryan Salmanpour f47fd89f62 Add support for gfx1100 - update the vcn lookup table (#34) 2023-11-02 22:05:17 -04:00
Wenkai Du 297023a7a6 msccl: add templated kernel (#945)
* msccl: add templated kernel

* Use defines to improve code readability

* Fix kernel indexing and review feedback

[ROCm/rccl commit: f484ff17b9]
2023-11-02 17:21:53 -07:00
Wenkai Du f484ff17b9 msccl: add templated kernel (#945)
* msccl: add templated kernel

* Use defines to improve code readability

* Fix kernel indexing and review feedback
2023-11-02 17:21:53 -07:00
Jonathan R. Madsen 370a86830b Support Tool Intercept API Tables (#165)
* Update include/rocprofiler

- intercept_table.h header
- generic rocprofiler_runtime_library_t
- rocprofiler_internal_thread_library_t is not typedef for rocprofiler_runtime_library_t
- rocprofiler_at_runtime_api_registration

* Update lib/rocprofiler

- minor tweaks to context.cpp
  - check if none context early
  - disallow stop_context when finalizing
- add intercept_table.hpp and intercept_table.cpp
  - implement rocprofiler_at_runtime_api_registration
  - implement notify_runtime_api_registration
- update registration.cpp
  - invoke notify_runtime_api_registration
  - tweak to fini status when invoking client finalizer

* Update lib/rocprofiler/tests

- add tests for intercept table

* Add samples/intercept_table

- demonstrate how to install custom API function wrappers instead of relying on HSA callback tracing

* Update lib/rocprofiler/tests/intercept_table.cpp

- remove _SERVICE from ROCPROFILER_SERVICE_

* Update include/rocprofiler/intercept_table.h

- Update doxygen comments

* Update lib/rocprofiler/intercept_table.cpp

- return error config locked if already initialized

* Update lib/rocprofiler/intercept_table.cpp

- remove unnecessary alias

* Apply suggestions from code review

Co-authored-by: Tony Tye <Tony.Tye@amd.com>

* Update doxygen comments

- clarify when rocprofiler_at_runtime_api_registration can be invoked

* Use rocprofiler_runtime_library_t for intercept table and internal threading

- remove rocprofiler_intercept_library_t alias to rocprofiler_runtime_library_t
- remove rocprofiler_internal_thread_library_t alias to rocprofiler_runtime_library_t
- move around documentation with regard to rocprofiler_runtime_library_t enumeration
- added some extra doxygen documentation to internal threading functions

---------

Co-authored-by: Tony Tye <Tony.Tye@amd.com>

[ROCm/rocprofiler-sdk commit: 4f2dc896d3]
2023-11-02 19:10:10 -05:00
Jonathan R. Madsen 4f2dc896d3 Support Tool Intercept API Tables (#165)
* Update include/rocprofiler

- intercept_table.h header
- generic rocprofiler_runtime_library_t
- rocprofiler_internal_thread_library_t is not typedef for rocprofiler_runtime_library_t
- rocprofiler_at_runtime_api_registration

* Update lib/rocprofiler

- minor tweaks to context.cpp
  - check if none context early
  - disallow stop_context when finalizing
- add intercept_table.hpp and intercept_table.cpp
  - implement rocprofiler_at_runtime_api_registration
  - implement notify_runtime_api_registration
- update registration.cpp
  - invoke notify_runtime_api_registration
  - tweak to fini status when invoking client finalizer

* Update lib/rocprofiler/tests

- add tests for intercept table

* Add samples/intercept_table

- demonstrate how to install custom API function wrappers instead of relying on HSA callback tracing

* Update lib/rocprofiler/tests/intercept_table.cpp

- remove _SERVICE from ROCPROFILER_SERVICE_

* Update include/rocprofiler/intercept_table.h

- Update doxygen comments

* Update lib/rocprofiler/intercept_table.cpp

- return error config locked if already initialized

* Update lib/rocprofiler/intercept_table.cpp

- remove unnecessary alias

* Apply suggestions from code review

Co-authored-by: Tony Tye <Tony.Tye@amd.com>

* Update doxygen comments

- clarify when rocprofiler_at_runtime_api_registration can be invoked

* Use rocprofiler_runtime_library_t for intercept table and internal threading

- remove rocprofiler_intercept_library_t alias to rocprofiler_runtime_library_t
- remove rocprofiler_internal_thread_library_t alias to rocprofiler_runtime_library_t
- move around documentation with regard to rocprofiler_runtime_library_t enumeration
- added some extra doxygen documentation to internal threading functions

---------

Co-authored-by: Tony Tye <Tony.Tye@amd.com>
2023-11-02 19:10:10 -05:00
Galantsev, Dmitrii 3126d1461c CMake - Bump version
Change-Id: Ibe62c0059262bcb9937ae856b796392b1fe362a0
Signed-off-by: Galantsev, Dmitrii <dmitrii.galantsev@amd.com>


[ROCm/rocm_smi_lib commit: 7d629c5959]
2023-11-02 18:26:00 -05:00
Galantsev, Dmitrii 7d629c5959 CMake - Bump version
Change-Id: Ibe62c0059262bcb9937ae856b796392b1fe362a0
Signed-off-by: Galantsev, Dmitrii <dmitrii.galantsev@amd.com>
2023-11-02 18:26:00 -05:00
Galantsev, Dmitrii ff295e4648 CMake - Bump version
Change-Id: Ibe62c0059262bcb9937ae856b796392b1fe362a0
Signed-off-by: Galantsev, Dmitrii <dmitrii.galantsev@amd.com>


[ROCm/amdsmi commit: 7d629c5959]
2023-11-02 18:26:00 -05:00
Galantsev, Dmitrii 3ac6b36a60 Merge amd-staging into amd-master 20231102
Change-Id: I7d1901564af875f2f9aa8879f24bff098ea30600
Signed-off-by: Galantsev, Dmitrii <dmitrii.galantsev@amd.com>


[ROCm/rocm_smi_lib commit: 8aa036ae08]
2023-11-02 18:24:10 -05:00
Galantsev, Dmitrii 8aa036ae08 Merge amd-staging into amd-master 20231102
Change-Id: I7d1901564af875f2f9aa8879f24bff098ea30600
Signed-off-by: Galantsev, Dmitrii <dmitrii.galantsev@amd.com>
2023-11-02 18:24:10 -05:00
jeffqjiangNew 170cc43cfb Added all preparing steps in decode process before calling VA-API. (#32)
* rocDecode/HEVC parsing: Implemented correct logic to set active VPS, SPS and PPS: start from slice header and up. Added video image size change detection. Fixed slice_segment_address bits calculation in slice segment header parsing.

* rocDecode/HEVC: Changed variable naming to Google style.

* rocDecode/HEVC: Added VPS, SPS, PPS, and slice segment header content logging functions for debug purposes.

* rocDecode/HEVC: Compacted opening bracket lines to keep coding style consistency.

* * rocDecode/HEVC: Fixed an issue in profile-tier-level parsing where 44 bits are skipped in an incorrect way using ReadBits() which can only consume 32 bits max. Also formated SPS parsing code by using pointer instead of array element.

* * rocDecode/HEVC: Fixed the incorrect array size for sps_max_dec_pic_buffering_minus1, sps_max_num_reorder_pics and sps_max_num_reorder_pics in SPS structure define.

* * rocDecode/HEVC: Modified scaling list parsing to make sure we explicitly follow the spec.

* * rocDecode/HEVC: Added a few syntax elements to short team RPS structure, updated RPS parsing function and logging function.

* * rocDecode/HEVC: In PPS parsing function, use structure pointer instead of structure array element to improve coding clarity.

* * rocDecode/HEVC: Compacted the opening bracket lines. No functional changes.

* * rocDecode/HEVC: Added full parsing of slice segment header. Added PPS range extension parsing.

* * rocDecode/HEVC: Fixed a build error in debug mode due to merging from master branch: removing a redundant debug function.

* * rocDecode/HEVC: Changed the condition for sequence call back from picture size change to more general case where a new SPS is activated. Also moved the call from slice header parsing to upper level where frame data is processed.

* * rocDecode: Compacted opening bracket line. No functional changes.

* * rocDecode/HEVC: Moved POC calculation from slice header parsing to picture level, since we only need to do the calculation once per picture.

* * rocDecode/HEVC: Added RPS decode function.

* *rocDecode/HEVC: Added reference picture list construction.

* * rocDecode/HEVC: Added current picture marking in DPB.

* * rocDecode/HEVC: Removed VA surface id from DPB buffer info structure.

* * rocDecode/HEVC: Do not construct ref list for I pictures.

[ROCm/rocdecode commit: 7a537bbb88]
2023-11-02 18:08:24 -04:00
jeffqjiangNew 7a537bbb88 Added all preparing steps in decode process before calling VA-API. (#32)
* rocDecode/HEVC parsing: Implemented correct logic to set active VPS, SPS and PPS: start from slice header and up. Added video image size change detection. Fixed slice_segment_address bits calculation in slice segment header parsing.

* rocDecode/HEVC: Changed variable naming to Google style.

* rocDecode/HEVC: Added VPS, SPS, PPS, and slice segment header content logging functions for debug purposes.

* rocDecode/HEVC: Compacted opening bracket lines to keep coding style consistency.

* * rocDecode/HEVC: Fixed an issue in profile-tier-level parsing where 44 bits are skipped in an incorrect way using ReadBits() which can only consume 32 bits max. Also formated SPS parsing code by using pointer instead of array element.

* * rocDecode/HEVC: Fixed the incorrect array size for sps_max_dec_pic_buffering_minus1, sps_max_num_reorder_pics and sps_max_num_reorder_pics in SPS structure define.

* * rocDecode/HEVC: Modified scaling list parsing to make sure we explicitly follow the spec.

* * rocDecode/HEVC: Added a few syntax elements to short team RPS structure, updated RPS parsing function and logging function.

* * rocDecode/HEVC: In PPS parsing function, use structure pointer instead of structure array element to improve coding clarity.

* * rocDecode/HEVC: Compacted the opening bracket lines. No functional changes.

* * rocDecode/HEVC: Added full parsing of slice segment header. Added PPS range extension parsing.

* * rocDecode/HEVC: Fixed a build error in debug mode due to merging from master branch: removing a redundant debug function.

* * rocDecode/HEVC: Changed the condition for sequence call back from picture size change to more general case where a new SPS is activated. Also moved the call from slice header parsing to upper level where frame data is processed.

* * rocDecode: Compacted opening bracket line. No functional changes.

* * rocDecode/HEVC: Moved POC calculation from slice header parsing to picture level, since we only need to do the calculation once per picture.

* * rocDecode/HEVC: Added RPS decode function.

* *rocDecode/HEVC: Added reference picture list construction.

* * rocDecode/HEVC: Added current picture marking in DPB.

* * rocDecode/HEVC: Removed VA surface id from DPB buffer info structure.

* * rocDecode/HEVC: Do not construct ref list for I pictures.
2023-11-02 18:08:24 -04:00
Maisam Arif f061aa4be5 SWDEV-425457 - Updated Sphinx docs to include ESMI
Signed-off-by: Maisam Arif <maisarif@amd.com>
Change-Id: Ie7669c9f94703e5c5cdc65314cbf30e8b587d0f1
2023-11-02 17:39:56 -04:00
Maisam Arif 5b6d22b24e SWDEV-425457 - Updated Sphinx docs to include ESMI
Signed-off-by: Maisam Arif <maisarif@amd.com>
Change-Id: Ie7669c9f94703e5c5cdc65314cbf30e8b587d0f1


[ROCm/amdsmi commit: f061aa4be5]
2023-11-02 17:39:56 -04:00
Nusrat Islam 7c24d9970e Merge pull request #946 from nusislam/msccl-redop
msccl: remove dereference of reduce args

[ROCm/rccl commit: 61aed56ca7]
2023-11-02 16:22:24 -05:00
Nusrat Islam 61aed56ca7 Merge pull request #946 from nusislam/msccl-redop
msccl: remove dereference of reduce args
2023-11-02 16:22:24 -05:00