The three kfdtests have been fixed, so remove them from
filter list.
Signed-off-by: Eric Huang <jinhuieric.huang@amd.com>
Change-Id: I101a72476970a9d105e8c0b5c022847757fdd316
[ROCm/ROCR-Runtime commit: 3a378fcf0b]
Before gfx90a, coherent memory is uncached. So it was reasonable
when environment variable HSA_DISABLE_CACHE is set, memory is mapped
as coherent. On gfx90a, coherent memory can be cached, so mapping
memory as coherent can't guarantee memory is uncached. When
HSA_DISABLE_CACHE is set, we have to map memory as uncached.
Change-Id: Ia5ed4cf0ad6aef5644dc8c9e6632b52d606f06f4
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
Before gfx90a, coherent memory is uncached. So it was reasonable
when environment variable HSA_DISABLE_CACHE is set, memory is mapped
as coherent. On gfx90a, coherent memory can be cached, so mapping
memory as coherent can't guarantee memory is uncached. When
HSA_DISABLE_CACHE is set, we have to map memory as uncached.
Change-Id: Ia5ed4cf0ad6aef5644dc8c9e6632b52d606f06f4
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
[ROCm/ROCR-Runtime commit: f132fb2cd0]
Refer to commit "Mark buffers accessed by CP as UC"
A+A buffers are mapped as NC. CP (PM4Writes) need ReleaseMem function to
ensure the write go through to the memory
Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Change-Id: I4ee55a6e40fba078f5950d95c8fee7ee076260bf
Refer to commit "Mark buffers accessed by CP as UC"
A+A buffers are mapped as NC. CP (PM4Writes) need ReleaseMem function to
ensure the write go through to the memory
Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Change-Id: I4ee55a6e40fba078f5950d95c8fee7ee076260bf
[ROCm/ROCR-Runtime commit: 57f46b53ec]
Refer to commit: " Mark buffers accessed by CP as UC"
Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Change-Id: I1816e035dbb3178f28f5e34b050c20ecca282060
Refer to commit: " Mark buffers accessed by CP as UC"
Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Change-Id: I1816e035dbb3178f28f5e34b050c20ecca282060
[ROCm/ROCR-Runtime commit: 0e8500b886]
This change might be redundant if ROCr takes care of it
Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Change-Id: I7b67143a8ad21baa61b7eda7b8e5fe0ac1e33830
This change might be redundant if ROCr takes care of it
Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Change-Id: I7b67143a8ad21baa61b7eda7b8e5fe0ac1e33830
[ROCm/ROCR-Runtime commit: 10674916e4]
This change is for the A+A bring-up branch as it needs to made more
generic to handle all ASICs.
For A+A all the system buffers are mapped as NC (non coherent) unless
explicitly marked as UC (uncached). The coherency is then expected to be
handled by shader by explicitly using acquire/release instructions.
However, CP doesn't have same feature. The buffers used by CP thus have
to UC. For now queue buffer and Signal handler memory is marked as UC.
This change shouldn't affect other ASICs since Uncached flag is not used
in those. However, this change still need to be made more generic.
Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Change-Id: I56c37a809913f7f08c94d01b0572d0f4864939aa
This change is for the A+A bring-up branch as it needs to made more
generic to handle all ASICs.
For A+A all the system buffers are mapped as NC (non coherent) unless
explicitly marked as UC (uncached). The coherency is then expected to be
handled by shader by explicitly using acquire/release instructions.
However, CP doesn't have same feature. The buffers used by CP thus have
to UC. For now queue buffer and Signal handler memory is marked as UC.
This change shouldn't affect other ASICs since Uncached flag is not used
in those. However, this change still need to be made more generic.
Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Change-Id: I56c37a809913f7f08c94d01b0572d0f4864939aa
[ROCm/ROCR-Runtime commit: 7c05c5240f]
On gfx9, the maximum number of wavefronts per queue is the minimum of
40 waves per compute units, or 512 waves per shader engine. On gfx10,
there can only be 32 waves per compute units.
Signed-off-by: Laurent Morichetti <laurent.morichetti@amd.com>
Change-Id: I148d1a4fe6c07cdbfaa1f77939eb29311c81c008
On gfx9, the maximum number of wavefronts per queue is the minimum of
40 waves per compute units, or 512 waves per shader engine. On gfx10,
there can only be 32 waves per compute units.
Signed-off-by: Laurent Morichetti <laurent.morichetti@amd.com>
Change-Id: I148d1a4fe6c07cdbfaa1f77939eb29311c81c008
[ROCm/ROCR-Runtime commit: 4cf11c3a7e]
Reserve some space in the context save area for the debugger's
use. There should be 32 bytes per wave for a given queue.
Change-Id: I65ddb6123d0f6afd3149844617ad19023009101d
Reserve some space in the context save area for the debugger's
use. There should be 32 bytes per wave for a given queue.
Change-Id: I65ddb6123d0f6afd3149844617ad19023009101d
[ROCm/ROCR-Runtime commit: a83f9b67ce]
Temporarily blacklist some tests on gfx90a until they are solved.
Signed-off-by: Amber Lin <Amber.Lin@amd.com>
Change-Id: I87cc3a996ea7d55ed8f20f5b4eecfd8bb691effd
Temporarily blacklist some tests on gfx90a until they are solved.
Signed-off-by: Amber Lin <Amber.Lin@amd.com>
Change-Id: I87cc3a996ea7d55ed8f20f5b4eecfd8bb691effd
[ROCm/ROCR-Runtime commit: e342c9c890]
On every new asic with new stepping, we need to manually relax this
checking. This check is not very helpful. Delete it.
Change-Id: I11f813023ca2566d82f6d11121d4be38c296674b
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
On every new asic with new stepping, we need to manually relax this
checking. This check is not very helpful. Delete it.
Change-Id: I11f813023ca2566d82f6d11121d4be38c296674b
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
[ROCm/ROCR-Runtime commit: 1f05b54dc9]
Due to cache coherence change, the remote vram mapping is changed
to cached, the written value by remote shader will not be read by
local shader. So the test will fail.
Signed-off-by: Eric Huang <jinhuieric.huang@amd.com>
Change-Id: I2b64e8a30bed0066e159bad9bb7febae5ebe84aa
Due to cache coherence change, the remote vram mapping is changed
to cached, the written value by remote shader will not be read by
local shader. So the test will fail.
Signed-off-by: Eric Huang <jinhuieric.huang@amd.com>
Change-Id: I2b64e8a30bed0066e159bad9bb7febae5ebe84aa
[ROCm/ROCR-Runtime commit: ec7ba38b23]
XNACK API for GPUs that support this mode. This API
makes calls to amdgpu driver to configure xnack mode.
It supports set xnack mode and query the current mode used.
Change-Id: If865fd0e3f900f008243dc49504e1a0694e1791a
Signed-off-by: Alex Sierra <alex.sierra@amd.com>
XNACK API for GPUs that support this mode. This API
makes calls to amdgpu driver to configure xnack mode.
It supports set xnack mode and query the current mode used.
Change-Id: If865fd0e3f900f008243dc49504e1a0694e1791a
Signed-off-by: Alex Sierra <alex.sierra@amd.com>
[ROCm/ROCR-Runtime commit: 3f45f602d4]
Add function definitions to support SVM (shared virtual memory)
and xnack set.
Change-Id: Ia97ad9d0c449d8d500d799f702e1a58e87d65a56
Signed-off-by: Alex Sierra <alex.sierra@amd.com>
Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Add function definitions to support SVM (shared virtual memory)
and xnack set.
Change-Id: Ia97ad9d0c449d8d500d799f702e1a58e87d65a56
Signed-off-by: Alex Sierra <alex.sierra@amd.com>
Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
[ROCm/ROCR-Runtime commit: a352639df5]
Add svm (shared virtual memory) range and xnack mode
APIs.
Change-Id: Ibd8d7fe566dc200730da0c892caa71aad7589ebd
Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Signed-off-by: Alex Sierra <alex.sierra@amd.com>
Add svm (shared virtual memory) range and xnack mode
APIs.
Change-Id: Ibd8d7fe566dc200730da0c892caa71aad7589ebd
Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Signed-off-by: Alex Sierra <alex.sierra@amd.com>
[ROCm/ROCR-Runtime commit: 5ae49f2321]
strlen(src) should not be used as the length in strncpy. Use memcpy
since we know the length of the string, and ensure that we
NULL-terminate regardless of length
Signed-off-by: Kent Russell <kent.russell@amd.com>
Change-Id: I21cc6d106510c69464e7ac9d3fc7da3a1e6d1a68
strlen(src) should not be used as the length in strncpy. Use memcpy
since we know the length of the string, and ensure that we
NULL-terminate regardless of length
Signed-off-by: Kent Russell <kent.russell@amd.com>
Change-Id: I21cc6d106510c69464e7ac9d3fc7da3a1e6d1a68
[ROCm/ROCR-Runtime commit: 731a06c704]
The largebar check will exit exceptionally from test
when destination node is not set.
Signed-off-by: Eric Huang <jinhuieric.huang@amd.com>
Change-Id: I8bf0fed613250cc71468208e645fc562fb1a8757
The largebar check will exit exceptionally from test
when destination node is not set.
Signed-off-by: Eric Huang <jinhuieric.huang@amd.com>
Change-Id: I8bf0fed613250cc71468208e645fc562fb1a8757
[ROCm/ROCR-Runtime commit: 18ead8815c]
Update build script and CMakeLists_sp3.txt file as SP3 directory
structure has changed.
The SP3 source code with gfx90a suport is merged into a
new branch mukjoshi/sp3_gfx90a.
Please make sure to checkout this branch before using the
build script to generate the static library.
Change-Id: I2bf0ade8b2d254cd7648cc8a6d69a83ee51344cd
Update build script and CMakeLists_sp3.txt file as SP3 directory
structure has changed.
The SP3 source code with gfx90a suport is merged into a
new branch mukjoshi/sp3_gfx90a.
Please make sure to checkout this branch before using the
build script to generate the static library.
Change-Id: I2bf0ade8b2d254cd7648cc8a6d69a83ee51344cd
[ROCm/ROCR-Runtime commit: da3abfb0f8]
Add updated SP3 static library with support for gfx90a and
also add initial corresponding changes in kfdtest.
Change-Id: I71bc6404ace7f9bf0dd74e712287136aa2b8a03d
Eric Huang
Oak Zeng
Harish Kasiviswanathan
Laurent Morichetti
Amber Lin
Alex Sierra
Philip Yang
Kent Russell
Jonathan Kim
Mukul Joshi