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sumanthtg 00d46218b7 [dtest] Tests for atomicAdd/atomicAddnoRet 
Positive and negative test cases for atomicAdd and
AtomicAddnoRet device functions

SWDEV-238517 for enhancing hip unit tests

Change-Id: Id20ba2550d20f224004f105cdcd087002cb80e56
 2020-10-07 13:20:12 -04:00
sumanthtg b92a369a11 [dtest] Tests for atomicAdd/atomicAddnoRet 
Positive and negative test cases for atomicAdd and
AtomicAddnoRet device functions

SWDEV-238517 for enhancing hip unit tests

Change-Id: Id20ba2550d20f224004f105cdcd087002cb80e56


[ROCm/hip commit: 543dc8cea5]
 2020-10-07 13:20:12 -04:00
sumanthtg 543dc8cea5 [dtest] Tests for atomicAdd/atomicAddnoRet 
Positive and negative test cases for atomicAdd and
AtomicAddnoRet device functions

SWDEV-238517 for enhancing hip unit tests

Change-Id: Id20ba2550d20f224004f105cdcd087002cb80e56
 2020-10-07 13:20:12 -04:00
sumanthtg 754936e9e9 [dtest] Additional tests for hipOccupancyMax APIs 
Additional tests for following APIs
- hipOccupancyMaxActiveBlocksPerMultiprocessor
- hipOccupancyMaxPotentialBlockSize

SWDEV-238517 for enhancing hip unit tests

Change-Id: Ib9441c1366f46a082e10eb1a572bc7d8ebe1ee37


[ROCm/clr commit: 4eb65d58dd]
 2020-10-07 13:19:06 -04:00
sumanthtg 4eb65d58dd [dtest] Additional tests for hipOccupancyMax APIs 
Additional tests for following APIs
- hipOccupancyMaxActiveBlocksPerMultiprocessor
- hipOccupancyMaxPotentialBlockSize

SWDEV-238517 for enhancing hip unit tests

Change-Id: Ib9441c1366f46a082e10eb1a572bc7d8ebe1ee37
 2020-10-07 13:19:06 -04:00
sumanthtg 3a634bb965 [dtest] Additional tests for hipOccupancyMax APIs 
Additional tests for following APIs
- hipOccupancyMaxActiveBlocksPerMultiprocessor
- hipOccupancyMaxPotentialBlockSize

SWDEV-238517 for enhancing hip unit tests

Change-Id: Ib9441c1366f46a082e10eb1a572bc7d8ebe1ee37


[ROCm/hip commit: 2bee071530]
 2020-10-07 13:19:06 -04:00
sumanthtg 2bee071530 [dtest] Additional tests for hipOccupancyMax APIs 
Additional tests for following APIs
- hipOccupancyMaxActiveBlocksPerMultiprocessor
- hipOccupancyMaxPotentialBlockSize

SWDEV-238517 for enhancing hip unit tests

Change-Id: Ib9441c1366f46a082e10eb1a572bc7d8ebe1ee37
 2020-10-07 13:19:06 -04:00
Chauncey Hui f4da930e7e SWDEV-2 - Change OpenCL version number from 3209 to 3210 
[ROCm/clr commit: 099dbb7f13]
 2020-10-07 03:00:03 -04:00
Chauncey Hui 099dbb7f13 SWDEV-2 - Change OpenCL version number from 3209 to 3210 2020-10-07 03:00:03 -04:00
Evgeny 65928ee9d1 SWDEV-249924 : hip correlation id explicite propogation; tracer debug instrumentation; 
Change-Id: Ibbc411541f5610ce739f3fc1efa1ab7f605220f5

initial commmit

Change-Id: I34b360be62c2083819dc5c3acc8268bd69f2f58a


[ROCm/roctracer commit: ef61a39603]
 2020-10-06 13:25:51 -04:00
Evgeny ef61a39603 SWDEV-249924 : hip correlation id explicite propogation; tracer debug instrumentation; 
Change-Id: Ibbc411541f5610ce739f3fc1efa1ab7f605220f5

initial commmit

Change-Id: I34b360be62c2083819dc5c3acc8268bd69f2f58a
 2020-10-06 13:25:51 -04:00
Sourabh Betigeri 99d2c155ff SWDEV-247768: Added new perf test - SampleRate 
Change-Id: I3aee07dff3759a0ac56a1afb384168bb94394187


[ROCm/hip-tests commit: 71319d9d2c]
 2020-10-06 12:46:13 -04:00
Sourabh Betigeri 71319d9d2c SWDEV-247768: Added new perf test - SampleRate 
Change-Id: I3aee07dff3759a0ac56a1afb384168bb94394187
 2020-10-06 12:46:13 -04:00
Sourabh Betigeri c8d913a3d8 SWDEV-247768: Added new perf test - SampleRate 
Change-Id: I3aee07dff3759a0ac56a1afb384168bb94394187


[ROCm/clr commit: acdc435e77]
 2020-10-06 12:46:13 -04:00
Sourabh Betigeri acdc435e77 SWDEV-247768: Added new perf test - SampleRate 
Change-Id: I3aee07dff3759a0ac56a1afb384168bb94394187
 2020-10-06 12:46:13 -04:00
Sourabh Betigeri 6198eaf88e SWDEV-247768: Added new perf test - SampleRate 
Change-Id: I3aee07dff3759a0ac56a1afb384168bb94394187


[ROCm/hip commit: 979c5d4d6f]
 2020-10-06 12:46:13 -04:00
Sourabh Betigeri 979c5d4d6f SWDEV-247768: Added new perf test - SampleRate 
Change-Id: I3aee07dff3759a0ac56a1afb384168bb94394187
 2020-10-06 12:46:13 -04:00
Sarbojit Sarkar 1dee6f664b [perf]hipMalloc perf optimization 
Change-Id: I9cd1d29205cb0c9938d26bb8e336fc9fe8a262ed


[ROCm/clr commit: a3b44b5f75]
 2020-10-06 12:22:57 -04:00
Sarbojit Sarkar a3b44b5f75 [perf]hipMalloc perf optimization 
Change-Id: I9cd1d29205cb0c9938d26bb8e336fc9fe8a262ed
 2020-10-06 12:22:57 -04:00
Sarbojit Sarkar d58970c94e [perf]hipMalloc perf optimization 
Change-Id: I9cd1d29205cb0c9938d26bb8e336fc9fe8a262ed


[ROCm/hip commit: 718ac775f7]
 2020-10-06 12:22:57 -04:00
Sarbojit Sarkar 718ac775f7 [perf]hipMalloc perf optimization 
Change-Id: I9cd1d29205cb0c9938d26bb8e336fc9fe8a262ed
 2020-10-06 12:22:57 -04:00
Vladislav Sytchenko 4a6f033fd2 Change __HIP_ENABLE_PCH to be an option 
Currently all the logic checks if __HIP_ENABLE_PCH is set, so setting it
to OFF will still enable PCH.

Switching __HIP_ENABLE_PCH to be a CMake option will enable correct
build behaviour.

Change-Id: I77a663589ffb5f2595c6ad3d144eb9466adcf250


[ROCm/clr commit: 8034467ec3]
 2020-10-06 11:17:47 -04:00
Vladislav Sytchenko 8034467ec3 Change __HIP_ENABLE_PCH to be an option 
Currently all the logic checks if __HIP_ENABLE_PCH is set, so setting it
to OFF will still enable PCH.

Switching __HIP_ENABLE_PCH to be a CMake option will enable correct
build behaviour.

Change-Id: I77a663589ffb5f2595c6ad3d144eb9466adcf250
 2020-10-06 11:17:47 -04:00
Vladislav Sytchenko e428310a56 Change __HIP_ENABLE_PCH to be an option 
Currently all the logic checks if __HIP_ENABLE_PCH is set, so setting it
to OFF will still enable PCH.

Switching __HIP_ENABLE_PCH to be a CMake option will enable correct
build behaviour.

Change-Id: I77a663589ffb5f2595c6ad3d144eb9466adcf250


[ROCm/hip commit: 3949675ab0]
 2020-10-06 11:17:47 -04:00
Vladislav Sytchenko 3949675ab0 Change __HIP_ENABLE_PCH to be an option 
Currently all the logic checks if __HIP_ENABLE_PCH is set, so setting it
to OFF will still enable PCH.

Switching __HIP_ENABLE_PCH to be a CMake option will enable correct
build behaviour.

Change-Id: I77a663589ffb5f2595c6ad3d144eb9466adcf250
 2020-10-06 11:17:47 -04:00
Jason Tang 0e19d02735 SWDEV-255321 - Support target names from Target ID feature 
Change-Id: I45e5314dff2ee65dd402c38744279bf67501304d


[ROCm/clr commit: bad12583b0]
 2020-10-06 09:00:54 -04:00
Jason Tang bad12583b0 SWDEV-255321 - Support target names from Target ID feature 
Change-Id: I45e5314dff2ee65dd402c38744279bf67501304d
 2020-10-06 09:00:54 -04:00
kjayapra-amd 78fd06679b SWDEV-254363 - Checks to make sure kernel is launched on the same device as it was launched. 
Change-Id: I2f273a70b1a5fc0e9fc9c6144eabd32466ff4e59


[ROCm/clr commit: 40322a9f1c]
 2020-10-06 08:38:09 -04:00
kjayapra-amd 40322a9f1c SWDEV-254363 - Checks to make sure kernel is launched on the same device as it was launched. 
Change-Id: I2f273a70b1a5fc0e9fc9c6144eabd32466ff4e59
 2020-10-06 08:38:09 -04:00
kjayapra-amd 644e635e64 SWDEV-254363 - Checks to make sure kernel is launched on the same device as it was launched. 
Change-Id: I2f273a70b1a5fc0e9fc9c6144eabd32466ff4e59


[ROCm/hip commit: c4505bede3]
 2020-10-06 08:38:09 -04:00
kjayapra-amd c4505bede3 SWDEV-254363 - Checks to make sure kernel is launched on the same device as it was launched. 
Change-Id: I2f273a70b1a5fc0e9fc9c6144eabd32466ff4e59
 2020-10-06 08:38:09 -04:00
German Andryeyev 2c21a44b40 Add option to skip AQL barrier 
The change reuses HSA signals for dispatches as a wait signal.
Skipping the barrier requires to  disable L2 cache for sysmem
allocations and extra tracking for HDP access with the large bar.
ROC_BARRIER_SYNC=0 activates the new logic. Barrier sync is
still used by default.
ROC_ACTIVE_WAIT=1 enables unconditional active wait in ROCr.
The change also consolidated ROCr wait logic under single function.

Change-Id: I6bd1be30aa88258da1b1f9de319ef5a45852afd8


[ROCm/clr commit: d9397590de]
 2020-10-06 08:37:12 -04:00
German Andryeyev d9397590de Add option to skip AQL barrier 
The change reuses HSA signals for dispatches as a wait signal.
Skipping the barrier requires to  disable L2 cache for sysmem
allocations and extra tracking for HDP access with the large bar.
ROC_BARRIER_SYNC=0 activates the new logic. Barrier sync is
still used by default.
ROC_ACTIVE_WAIT=1 enables unconditional active wait in ROCr.
The change also consolidated ROCr wait logic under single function.

Change-Id: I6bd1be30aa88258da1b1f9de319ef5a45852afd8
 2020-10-06 08:37:12 -04:00
Rahul Garg 8e268b9170 Remove libhip_hcc references 
These were added in commit b2e0df3845.

Change-Id: I5815c90bb83ac74730f6bce114eb353f54b86670


[ROCm/clr commit: 2a5d39cd3b]
 2020-10-06 04:29:35 -04:00
Rahul Garg 2a5d39cd3b Remove libhip_hcc references 
These were added in commit 2cce9170c3.

Change-Id: I5815c90bb83ac74730f6bce114eb353f54b86670
 2020-10-06 04:29:35 -04:00
Rahul Garg a3a8ca1359 Remove libhip_hcc references 
These were added in commit 08ab76d58f.

Change-Id: I5815c90bb83ac74730f6bce114eb353f54b86670


[ROCm/hip commit: b673a56fcb]
 2020-10-06 04:29:35 -04:00
Rahul Garg b673a56fcb Remove libhip_hcc references 
These were added in commit bf443fef82.

Change-Id: I5815c90bb83ac74730f6bce114eb353f54b86670
 2020-10-06 04:29:35 -04:00
Sarbojit Sarkar 70d71642d2 [perf]hipMalloc performance optimization 
Change-Id: I6e8a918cc1c4cafad197b09e10755cd180e11ead


[ROCm/clr commit: 4a025e1a87]
 2020-10-06 03:19:41 -04:00
Sarbojit Sarkar 4a025e1a87 [perf]hipMalloc performance optimization 
Change-Id: I6e8a918cc1c4cafad197b09e10755cd180e11ead
 2020-10-06 03:19:41 -04:00
Sarbojit Sarkar ed1828ea72 SWDEV-253548 : clean up gfx-arch macros 
Change-Id: I8deb2ea44f556260bb78d24f68b04b0c730ed4d8


[ROCm/clr commit: 8ab8fac173]
 2020-10-06 03:17:09 -04:00
Sarbojit Sarkar 8ab8fac173 SWDEV-253548 : clean up gfx-arch macros 
Change-Id: I8deb2ea44f556260bb78d24f68b04b0c730ed4d8
 2020-10-06 03:17:09 -04:00
Chauncey Hui cf248c7b3b SWDEV-2 - Change OpenCL version number from 3208 to 3209 
[ROCm/clr commit: c7f03dae75]
 2020-10-06 03:00:02 -04:00
Chauncey Hui c7f03dae75 SWDEV-2 - Change OpenCL version number from 3208 to 3209 2020-10-06 03:00:02 -04:00
Sarbojit Sarkar 8587ec2976 SWDEV:253548 : remove gfx-arch macros 
Change-Id: I1ef0b4e080c15a9c6228f48ecd6a65b134d0a72d


[ROCm/clr commit: 3f0e33adb5]
 2020-10-06 01:15:58 -04:00
Sarbojit Sarkar 3f0e33adb5 SWDEV:253548 : remove gfx-arch macros 
Change-Id: I1ef0b4e080c15a9c6228f48ecd6a65b134d0a72d
 2020-10-06 01:15:58 -04:00
Sarbojit Sarkar 0eebd71062 SWDEV:253548 : remove gfx-arch macros 
Change-Id: I1ef0b4e080c15a9c6228f48ecd6a65b134d0a72d


[ROCm/hip commit: a2f9a2d469]
 2020-10-06 01:15:58 -04:00
Sarbojit Sarkar a2f9a2d469 SWDEV:253548 : remove gfx-arch macros 
Change-Id: I1ef0b4e080c15a9c6228f48ecd6a65b134d0a72d
 2020-10-06 01:15:58 -04:00
Chris Freehill 624f906f07 Fail gracefully if drm directory is not found 
Change-Id: I0f3ab2721108355752caf0280124469b98af4967


[ROCm/rocm_smi_lib commit: c6f02b4d62]
 2020-10-05 21:12:11 -04:00
Chris Freehill c6f02b4d62 Fail gracefully if drm directory is not found 
Change-Id: I0f3ab2721108355752caf0280124469b98af4967
 2020-10-05 21:12:11 -04:00
Chris Freehill 17f6a43fa1 Fail gracefully if drm directory is not found 
Change-Id: I0f3ab2721108355752caf0280124469b98af4967


[ROCm/amdsmi commit: c6f02b4d62]
 2020-10-05 21:12:11 -04:00