Gráfico de Commits

1240 Commits

Autor SHA1 Mensagem Data
Ioannis Assiouras a1c30318fb SWDEV-546223 - Get image support info from ISA meta (#773) 2025-09-02 15:05:18 +01:00
Ioannis Assiouras 5f525ee934 SWDEV-550882 - Expect HSA_EXT_POINTER_TYPE_RESERVED_ADDR pointer type from hsa_amd_pointer_info for hmm (#733) 2025-08-27 19:42:13 +01:00
Karthik Jayaprakash 89070536c0 SWDEV-552141 - Fix handle/fd type passed from app to align with spec. (#759)
* SWDEV-552141 - Fix handle/fd type passed from app to align with spec.

* SWDEV-552141 - Fix handle/fd type passed from app to align with spec.
2025-08-27 14:28:53 -04:00
SaleelK ddba20579d SWDEV-551080 - Fix hipMemcpyDeviceToDeviceNoCU path (#683)
* hipMemcpyDeviceToDeviceNoCU should always take SDMA path as per the
  flag usage
2025-08-25 15:13:02 -07:00
Danylo Lytovchenko 2ff2316227 Adjust clang format to the new versions, revert broken macro layout (#714) 2025-08-22 17:23:22 +02:00
systems-assistant[bot] 621da5410a SWDEV-465041 - Avoid wait in device enqueue (#443)
If we have PCIE atomics then we can avoid workaround in the scheduler, which requires an explicit wait on CPU
2025-08-20 12:46:47 -04:00
Danylo Lytovchenko f7338717ae SWDEV-470698 - fix formatting, add format check workflow (#657) 2025-08-20 19:58:06 +05:30
Andryeyev, German 72b9408fed SWDEV-547108 - Fix compilation errors under Windows (#867)
Interop and numa are not enabled.

[ROCm/clr commit: 0ac913e64c]
2025-08-17 02:33:31 -04:00
Betigeri, Sourabh 35e48d1eaf SWDEV-546293 - hipMemPrefetchAsync_v2 and hipMemAdvise_v2 implementation (#869)
SWDEV-546293 - hipMemPrefetchAsync hipMemAdvise_v2

Please enter the commit message for your changes. Lines starting

[ROCm/clr commit: cbee74a80e]
2025-08-15 22:40:04 -07:00
Manocha, Rahul b3ccf487da SWDEV-545952 - API definitions for hipStreamSet/GetAttribute (#831)
Co-authored-by: Rahul Manocha <rmanocha@amd.com>

[ROCm/clr commit: 0f49c4a97f]
2025-08-15 12:51:35 -07:00
Arandjelovic, Marko c33359ec62 SWDEV-532479 - Add tracking of hostcall memory allocations (#416)
* SWDEV-532479 - Add tracking of hostcall memory allocations

* SWDEV-532479 - Remove hostcall allocations if request is received

* SWDEV-532479 - Cleanup

* SWDEV-532479 - Naming fix

* SWDEV-532479 - Add new separator after each new function

[ROCm/clr commit: b58faa2f37]
2025-08-15 00:17:24 +02:00
Xie, Pengda 0a7064606c SWDEV-520384 - Improve postLoad latency during program load (#758)
Change-Id: I3c5a9e148efbd845c8fa3e4b51d9653664e9c499

[ROCm/clr commit: 191f068193]
2025-08-13 19:36:06 -07:00
Xie, Pengda 446f5740d8 SWDEV-547880 - Remove incorrect constMemSize calculation (#813)
[ROCm/clr commit: a028359ead]
2025-08-13 13:13:27 -07:00
Andryeyev, German 6df9a49437 SWDEV-465041 - Add support for user events with DD (#321)
* SWDEV-465041 - Add support for user events with DD

User events can be replaced with HSA signals. Add the interface
to allocate HSA signal for user events and update the status on
CL_COMPLETE.
Force pinned path with DD to avoid blocking calls. Pinned memory
can be released only when the command is complete.
Simplify device enqueue path to use generic kernel arg buffer and
signals

* Fix notifyCmdQueue() logic for OCL

* Avoid blocking calls in OCL with DD

* Add event  destruciton in a case of the failure.

[ROCm/clr commit: 2305f8ae56]
2025-08-12 19:04:36 -04:00
Chaudhary, Jatin Jaikishan 8f5eb715dc SWDEV-508540 - adjust for compile time wavefront 64 (#747)
[ROCm/clr commit: 926eedc230]
2025-08-11 10:17:27 +05:30
GunaShekar, Ajay bfcf0ef4e8 SWDEV-543366 - Bump PAL_CLIENT_INTERFACE_MAJOR_VERSION 916 --> 932 (#725)
Co-authored-by: Lin, Qun <Quentin.Lin@amd.com>
Co-authored-by: Lin,Qun <qlin@amd.com>

[ROCm/clr commit: ed903e8889]
2025-08-08 08:45:42 -07:00
Kudchadker, Saleel 3a849c6962 SWDEV-538195 - Introduce threshold for handler submission (#723)
- When doing device/stream sync, we can submit a handler which may
  introduce some host side delays. Use DEBUG_CLR_BATCH_CPU_SYNC_SIZE to
  batch commands for host wait. Default for HIP is 8 commands.
- Investigation is underway in ROCr but need to address this for now in
  HIP runtime.

[ROCm/clr commit: 9b045922a8]
2025-08-06 20:34:42 -07:00
Xie, Pengda 9cbbee4d6e SWDEV-520384 - Improve Fat Binary loading latency (#390)
Init and fini kernel needs to be launched when we load and unload code object. Avoid looping through all kernels within a code object just to run the init and fini kernels. Compiler currently only generates 1 init and fini kernel.

[ROCm/clr commit: cd46294b31]
2025-08-05 14:02:05 -07:00
Xie, Pengda b7d8cb56d1 SWDEV-505833 - Remove DEBUG_CLR_SKIP_RELEASE_SCOPE flag (#735)
Cleanup debug flag DEBUG_CLR_SKIP_RELEASE_SCOPE

[ROCm/clr commit: 4121a860bf]
2025-08-05 08:31:55 -07:00
Kudchadker, Saleel a1d3da6bd3 SWDEV-547614 - Demangle graph kernel names (#809)
[ROCm/clr commit: 1492328894]
2025-08-01 14:35:30 -07:00
Manocha, Rahul 4a93a614e5 SWDEV-539710 - Defer allocation of managed variable (#652)
Co-authored-by: Rahul Manocha <rmanocha@amd.com>

[ROCm/clr commit: 3f6f9d6081]
2025-07-31 08:30:23 -07:00
Betigeri, Sourabh 680c7fbf64 SWDEV-483895 - Use ROCr to reserve memory for HMM (#590)
[ROCm/clr commit: a1f056bd11]
2025-07-15 21:40:13 +05:30
Xie, Jiabao(Jimbo) e5226f2b7e SWDEV-460151 - add gfx1201 to amd-staging clr (#183)
* SWDEV-460151 - add gfx1201 to amd-staging clr

* SWDEV-460151 - removed pal macro

---------

Co-authored-by: Jimbo Xie <jiabaxie@amd.com>

[ROCm/clr commit: a5d932f160]
2025-07-11 08:51:47 -07:00
Sang, Tao a777d6eca0 SWDEV-539145 - Simplify host memory pool management (#668)
* SWDEV-539145 - Simplify host memory pool management

Remove unnecessary variables and functions.
Make code simpler and clear.

* Change cpu_agent_info_ into pointer.

* Restore getPreferredNumaNode()

[ROCm/clr commit: 1351cd7fa8]
2025-07-11 10:38:40 -04:00
Sang, Tao 7fd322af90 SWDEV-508776 - support VGPRs validation (#274)
Clarify some VGPRs terms description.
Fix some wrong query logics of availableVGPRs_ and
availableRegistersPerCU_ in device info.
Add hipDeviceAttributeMaxAvailableVgprsPerThread
attribute query.
Remove hardcoding of following
 info_.vgprAllocGranularity_
 info_.vgprsPerSimd_

[ROCm/clr commit: 397f303d97]
2025-07-09 10:46:52 -04:00
Kudchadker, Saleel 433c25eab0 SWDEV-539378 - Use agent of IPC memory owner (#570)
- Currently runtime just uses the local agent as it did not check for
  IPCShared()
- With this fix we query hsa_amd_pointer_info and get the right agent
  for the memory to pass it to the HSA copy api

[ROCm/clr commit: 46d766e4e2]
2025-07-08 12:02:01 -07:00
Xie, Pengda 8e5921174f SWDEV-540576 - Abort if user request a core dump (#653)
* SWDEV-539414 - Return error status from runtime handler when HIP_SKIP_ABORT_ON_GPU_ERROR is false

* SWDEV-539414 - default handler when GPU core file is generated

* SWDEV-540576 - Abort if user request a core dump

Change-Id: I9e2c640acf559880bd13641de9103e660ef822a3

---------

Co-authored-by: Assiouras, Ioannis <Ioannis.Assiouras@amd.com>
Co-authored-by: agunashe <ajay.gunashekar@amd.com>

[ROCm/clr commit: 9c1bff0ae7]
2025-07-03 00:29:14 +05:30
Sang, Tao 287ec83f5c SWDEV-539145 - Support extended fine grained system memory pool (#603)
* Add hipHostMalloc() new flag hipHostMallocUncached which will force to allocate pinned
host memory on extended fine grained system memory pool.
* Add hipHostAlloc() new flag hipHostAllocUncached which will force to allocate pinned
host memory on extended fine grained system memory pool.
* Add hipHostRegister() new flag hipHostRegisterUncached which will force to map
host memory onto extended fine grained system momory pool.

[ROCm/clr commit: a7d7687b8f]
2025-07-01 10:10:10 +05:30
Lin, Qun ced47b3588 SWDEV-508869 - Replace asicRevision with gfxip triple in paldevice (#601)
asicRevision is not unique in pal path now, use gfxip triple to match isa is more straight forward in pal path.

[ROCm/clr commit: b584fc8cd1]
2025-06-27 10:09:21 +08:00
Lin, Qun 3b44884a57 SWDEV-508869 - Fix Linux build error for HIP on PAL (#176)
[ROCm/clr commit: 9699cc3864]
2025-06-27 07:51:22 +08:00
Sang, Tao da7c6f57ef SWDEV-539399 - Support ROCCLR_MEM_HSA_CONTIGUOUS (#610)
Fix missing support of ROCCLR_MEM_HSA_CONTIGUOUS in
hipExtMallocWithFlags().

[ROCm/clr commit: f4d78d427c]
2025-06-26 14:05:23 -04:00
Kudchadker, Saleel 3c9f80b4e4 SWDEV-535490 - Improve logging (#441)
- Include HIP version/githash in the logs
- Add a new method to print library path

[ROCm/clr commit: 5d53c83806]
2025-06-24 13:00:00 -07:00
Brzak, Branislav 4eba877aef SWDEV-531996 - Add legacy fallback Mesa loading via dlsym (#512)
[ROCm/clr commit: 494c0e3201]
2025-06-11 08:02:51 +05:30
Brzak, Branislav c95ca33e7b SWDEV-531996 SWDEV-530154 - Use *getprocaddress to obtain Mesa functions (#504)
[ROCm/clr commit: 5fabfedbd1]
2025-06-10 13:31:32 +05:30
Jayaprakash, Karthik 4691ca2f39 SWDEV-531711 - Fixing compilation error by moving static var to public. (#438)
[ROCm/clr commit: b72812d324]
2025-05-30 11:42:50 +05:30
Andryeyev, German fc2f5aaf22 SWDEV-533074 - Expose hipDeviceAttributeNumberOfXccs attribute (#336)
[ROCm/clr commit: 5cc172c99c]
2025-05-21 22:35:42 +05:30
Jayaprakash, Karthik a17e22a78c SWDEV-529929 - hipMemGetHandleForAddressRange implementation. (#245)
[ROCm/clr commit: 12131de4a9]
2025-05-20 15:56:04 -04:00
Jayaprakash, Karthik b59859c52e SWDEV-457749 - Use size of handle for range instead of actual size for physmem. (#342)
[ROCm/clr commit: bed454caa1]
2025-05-20 15:24:49 -04:00
Kudchadker, Saleel ee7c5554db SWDEV-523279 - Use preferred engine mask for SDMA (#317)
- ROCr now reports preferred engine for copy status. We can leverage
this for max bandwidth for inter-GPU copies
- Cleanup logging

[ROCm/clr commit: 1b0ea080e4]
2025-05-19 16:04:51 -07:00
Kudchadker, Saleel 5fd5e846e2 SWDEV-531518 - Fix offset accumulation (#333)
srcAddress/dstAddress accumulation was cumulative, which shouldnt be
done if we increment offset.

[ROCm/clr commit: 5712944c7c]
2025-05-19 18:03:06 +05:30
Jayaprakash, Karthik f4c9056cdc Revert "SWDEV-522707 - Set phys_mem_handle type to sizeof(size_t) to avoid blocking address range. (#105)" (#348)
This reverts commit 0071d33754.

[ROCm/clr commit: bb7750a946]
2025-05-19 15:19:16 +05:30
Jayaprakash, Karthik 4ea2d9a5ee SWDEV-531711 - Report correct error code based on device failure. (#286)
[ROCm/clr commit: f5b8db33f1]
2025-05-17 06:33:13 -04:00
Assiouras, Ioannis 71f19d7017 SWDEV-529449 - Bug fix when retrieving a memobj from the IPC mem handle
[ROCm/clr commit: f7482ef0a6]
2025-05-13 19:18:22 +01:00
Jayaprakash, Karthik a128beeeb5 SWDEV-506467 - Fixing compilation issue seen on clang compilation for ASAN. (#253)
[ROCm/clr commit: 876de49b11]
2025-05-12 17:16:56 -04:00
Andryeyev, German b9669ea266 SWDEV-531678 - Remove split path from the dispatch (#283)
The split path for blit kernels are no longer necessary, since the new blit kernels
don't use the copy size as the global workload

[ROCm/clr commit: da198ac5b2]
2025-05-12 12:50:32 -04:00
Arandjelovic, Marko 558a26cf98 SWDEV-511204 - Mapped virtual memory should use device instead of host context (#213)
Since the sub-buffer(virtual memory that is mapped to device memory) is associated with device memory, it should utilize the device context instead of the host context. The original implementation caused hipMemcpyPeer to not take the P2P path, as the memory object was treated as host memory.

[ROCm/clr commit: a7492c516d]
2025-05-12 16:55:25 +02:00
Patel, Jaydeepkumar 5bd5f3aa6e SWDEV-521135 - Make common way to set/parse UUID bytes from PAL props. (#63)
[ROCm/clr commit: 6858b0fca1]
2025-05-12 17:00:30 +05:30
Six, Lancelot fe14cc349b SWDEV-517078: Fix gfx11 trap handler (#212)
Fix incorrect edits done when porting the 2nd level trap handler from
the hsa-runtime.

Change-Id: I7bc5160be47b8f669efe05c4d194bc3c47fc0661

[ROCm/clr commit: c35e9643ec]
2025-05-11 01:12:28 +01:00
Xie, AlexBin 142e347aac SWDEV-528860 - reserve some memory in visible frame buffer (#251)
[ROCm/clr commit: faac50c77a]
2025-05-09 20:08:23 -04:00
Xie, Jiabao(Jimbo) e1d2194b75 SWDEV-528913 - support gfx950 in rocsetting (#217)
* SWDEV-528913 - support gfx950 in rocsetting

---------

Co-authored-by: Jimbo Xie <jiabaxie@amd.com>

[ROCm/clr commit: a320a3f214]
2025-05-07 15:44:49 -04:00