Add initial implementation of virtual memory heap with
dynamic virtual memory mapping support for memory pools.
DEBUG_HIP_MEM_POOL_VMHEAP controls the new method.
Change-Id: I8dc5be2e0f34ab472f1800f43bb6243639a5e500
[ROCm/clr commit: 296dce5570]
Support hipExternalMemoryGetMappedMipmappedArray().
Add ImageExternalBuffer to differiate ImageBuffer.
Currently we only support tiling_optimal mode as
vulkan driver doesn't provide tiling information.
Change-Id: I7e3524cdde53e4df9f728894bcebf4bd3f58d4d9
[ROCm/clr commit: 6398f604b0]
Add a view bit to avoid original resource destruction when parent
dependency doesn't exist with the image view cache
Change-Id: I8277afd575af8f29951c5d1a9f7d94d784251657
[ROCm/clr commit: b49e8e78e1]
Make sure parent_ field is cleared for the internal image views.
The internal image views don't require dependencies tracking.
The issue appeard only when Navi10 pitch workaround was enabled.
Change-Id: I376d212750085a9391f8c32fc2979dcb5d93c89c
[ROCm/clr commit: 6b89980fb2]
Add missing mipmap Apis’ implementation.
Fix some bugs of mimpmap apis.
Use hipmipmappedArray to differentiate cuda
and driver apis on Nvidia.
Change-Id: I6079d9f3b2ddf4e42b9a6f7f3902322cfca02cfd
[ROCm/clr commit: f03c11491b]
- Make IPC interfaces generic between devices and rely on the IPC buffer
for attach/detach logic
Change-Id: Id3c18d122030329b7ee532bbb6317de9dd6a0bbe
[ROCm/clr commit: 9aa6f25f1c]
For large bar platform, it's not necessary to mmap
memory allocated on VRAM to cpu again
Change-Id: I0701680476829d4058b3e7b643e8df657d0c6168
Signed-off-by: Ruili Ji <ruiliji2@amd.com>
[ROCm/clr commit: 25fe45bb2a]
Adding virtual memory management APIs to rocclr.
The HIP layer will handle virtual allocs on devices.
Change-Id: Ia978f105c2c3fed3959c77580ba228e845105754
[ROCm/clr commit: b5f555f9ec]
Adding opaque data handle to memory. This is used to look back the HIP object associated with it.
Change-Id: I1bbb14a915bed79c6c3593a29a627778c7aaf13a
[ROCm/clr commit: 867346520f]
Add ROCR memory detection and enable arena mem object for possible
access in HIP
Change-Id: Icf86ac789176bfee4ea8d36b0970a817d4c6a2f7
[ROCm/clr commit: 28597ec5b5]
Pass active queue for transfers in the cache coherency layer.
That will allow to use device transfer queue only for
cases when active queue isn't available, because using device
transfer queue from another active queue may cause a deadlock
Change-Id: Ifbe7e0303b77dbf6eeda3939ffbc25a3df7472de
[ROCm/clr commit: 95d55fdfa8]
- Device Reset should not purge the allocations that were not by the user
- Addresses QMCPack Test abort due to the removal of all the mem objects during reset
Change-Id: I7b7a123e72bcc985d7e51d17c2382bc618d3e041
[ROCm/clr commit: 924695fb5e]
If deferred allocation is disabled, then make sure the image view
is created without a delay. Also reset the allocation state, since
create() method isn't called for a view creation.
Change-Id: I7aa22a62bff18289ade83e56b5d3305ba68c715b
[ROCm/clr commit: 089a5cc4ad]
Replace amd::Atomic with std::atomic. Remove make_atomic uses by
converting the variable to std::atomic and making sure the memory
order is relaxed when synchronizes-with is not needed.
Delete utils/atomic.hpp.
Change-Id: I0b36db8d604a8510ac6e36b32885fd16a1b8ccfa
[ROCm/clr commit: 5d4b6f74d3]
When HIP_ENABLE_DEFERRED_LOADING=0, many global variables will be
referenced but they are not initialized in that early time. The patch
will use constexpr to initialze global constant varables in compile
time.
Change-Id: I9d538b7abc6a0ce700ec3332b97fc144db5fc1ef
[ROCm/clr commit: fdef6f722f]
German Andryeyev
kjayapra-amd
Ioannis Assiouras
Jaydeep Patel
taosang2
Todd tiantuo Li
Ruili Ji
Saleel Kudchadker
Sarbojit Sarkar
Rakesh Roy
Christophe Paquot
Satyanvesh Dittakavi
agunashe
Jason Tang
Ravi C Akkenapally
Laurent Morichetti