コミットグラフ

2445 コミット

作成者 SHA1 メッセージ 日付
Andreas Schneider 8ccfa4c75c cmake: Do not strip targets in the release build
Distributions want to generate debuginfo packages, do not strip them! If
you want to do it during installation use 'make install/strip'!

Change-Id: I3983af24ce4f4ddb189ede0ed0820dfee83b6280
2019-04-19 07:06:28 -04:00
Sean Keely 1251842900 Don't create blits when copy profiling is enabled.
Change-Id: I879827133957ee610c3381ea30c536ec7d10ffab
2019-04-18 20:00:02 -05:00
Jay Cornwall 56f280c8a7 Detect memory event through Flags field insetad of Failure
KFD no longer reports MemoryAccessFault.Failure with retry fault
implementation. ROCr ignores the memory event when Failure = 0.

Use the Flags field instead, which will be non-zero when the
event is triggered.

Change-Id: Ie90799a303b0b2f1b476b20ffafdde79ae137182
2019-04-15 19:16:07 -05:00
Ramesh Errabolu ba029ebe21 Remove instantiation of MemoryRegion for heap type SVM surfaced by ROCt
Change-Id: Ib4ff7e7cabe9aacb811888aeb74f652dcb57f9e0
2019-04-10 18:33:07 -05:00
Andreas Schneider b8a1331763 cmake: Create cmake config file
Another cmake project like hsa-runtime could just use:

find_package(hsakmt REQUIRED 1.9.0)

Change-Id: Ia1c9a80ef287facdd607382d69649b0718d687b4
2019-04-03 08:36:09 -04:00
Konstantin Zhuravlyov 7001134757 Process symbols with 0 address
Change-Id: I9ed943a8ccd3b103edd6aba8264c009d8cda29fa
2019-03-30 02:14:43 -04:00
Sean Keely a535e18cc1 Add hsa_amd_memory_lock_to_pool.
Makes malloc memory accessible to GPUs so that the memory has the
capabilities of the pool it is locked to.
This admits fine grained locked memory and reserves API space for any future
special CPU pools.

Change-Id: If8c3dd8582a43f19d3d36b3763c1a688cc419ef0
2019-03-29 01:09:21 -05:00
Sean Keely 9f7df6d6fe Remove legacy memory fault event name.
Change-Id: I3ad240482523409e1152548009aecf127e63bbfa
2019-03-28 15:25:25 -05:00
Sean Keely e5de33dd9a Fix void* arithmetic.
GCC allows arithmetic on void* treating void as char.  Clang and
the language spec does not.

Change-Id: I939f2432f276979bb81881406e10528597ac6001
2019-03-28 12:49:19 -05:00
Sean Keely 7ea0cd688f Disable sram-ecc reporting via ISA until HCC is fixed.
Change-Id: I0382825884b727173385f04da9f2088650c3ba1d
2019-03-21 17:46:56 -04:00
Chris Freehill 68c202de1f Re-enable RSMI call using updated API prototype
Change-Id: Ifc8fa35708fea05cbc8a9bea727a6d4c9d2ecea7
2019-03-18 23:18:42 -05:00
Chris Freehill 7b3537cf44 Temporary disable of rsmi call due to api change
Change-Id: If73f31c5fbe4bcd34f8e52a5109a6fbfff70b5e1
2019-03-16 21:05:47 -05:00
Sean Keely fd9fb77e28 Do not strip release builds.
Customer request.

Change-Id: Id77dcdc0b6908c7a5e460edfd7d9468a1691e351
2019-03-07 14:04:14 -06:00
Tom Stellard 006c2c248d Separate build version from library version
This patch separates the build version (i.e. ROCm version) from the
library version used to set the SONAME of the shared objects.  This
prevents the SONAME from getting bumped each time there is a new ROCm
release without any change to the libhsakmt ABI.

1.0.6 was choosen as the library version since this was the
last library version used prior to switching to the ROCm version
numbers.

Change-Id: I7c29ae84d8a362a831e804569d8147ca65155cad
2019-02-28 21:32:45 -08:00
Eric Huang e5b215570b kfdtest: fix and change in RAS test
1. RAS error injection debugfs interface has been changed which
is using ras_ctrl instead of *_err_inject.

2. Remove ASSERT_SUCCESS for fwrite, because fwrite returns
the size of written item but not the error number.

3. Using throw exception instead of return to avoid a segment fault.

Change-Id: I6c4d9c2f7e66719faec99abd1552105a08c238a4
Signed-off-by: Eric Huang <JinhuiEric.Huang@amd.com>
2019-03-29 11:00:01 -04:00
Eric Huang d6cde5bf08 libhsakmt: update kfd_ioctl.h regarding RAS interface
It is aligned with RAS changes in KFD.

Change-Id: I52816da01a4001158a40a1207d1fbe6ec3271343
Signed-off-by: Eric Huang <JinhuiEric.Huang@amd.com>
2019-03-28 21:38:44 -04:00
Sean Keely c7f1277013 Add hsaKmtRegisterMemoryWithFlags.
API follows hsaKmtRegisterMemory but allows passing HsaMemFlags.

Change-Id: I66a230a87c8b085f27c769bdf2cb4d0d96a5d6dd
2019-03-28 17:17:40 -04:00
Kent Russell 1304a92e17 libhsakmt: Add Vega M support
While this may not be supported in the runtime, the kernel/firmware
support it

Change-Id: I7fe4536a6b3055f39e25f453060e899938645d91
Signed-off-by: Kent Russell <kent.russell@amd.com>
2019-03-21 08:05:47 -04:00
Kent Russell c7439a0039 libhsakmt: Add another gfx902 GPU ID
Change-Id: I967f16bf548171df73d2e721f16c1aac52e99852
Signed-off-by: Kent Russell <kent.russell@amd.com>
2019-03-21 08:05:47 -04:00
Philip Yang 0bd9f35563 Revert "kfdtest.exclude: Temporarily blacklist IPC on gfx900"
This reverts commit d00ec779ce.

Fixes for HMM change corner cases are merged in from drm-next.
Tests are passed on gfx900 with the latest amd-kfd-staging.

Change-Id: I6c00d1eacf6b3f1ce715e085ae622b4e9ff1b7ff
Signed-off-by: Philip Yang <Philip.Yang@amd.com>
2019-03-18 10:10:00 -04:00
Amber Lin cfa47ac1f9 libhsakmt: Fix missing apicid in topology
While adding x2APIC support, apicid for non-x2apic was missing out by
mistake.



Change-Id: I25eed362c035c0e9fb9ea948899c49f70311f269
Signed-off-by: Amber Lin <Amber.Lin@amd.com>
2019-03-11 13:05:37 -04:00
Oak Zeng 1046a1fd72 Introduce XGMI SDMA queue type
Change-Id: I8c6ff04f92c2bbea0bab94ddb8cc4cceb5d74d02
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
2019-03-07 19:42:20 -05:00
Oak Zeng 414a3508d6 Thunk interface to get SDMA engine info
Add SDMA engine info fields to node properties and
modify get node properties API to read SDMA engine
info from sysfs

Change-Id: Iea877b5bc008cc9df9405daf564a359535f1bc9f
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
2019-03-07 14:09:43 -05:00
Oak Zeng e4109de26d Use latest kfd_ioctl.h
A new SDMA queue type for XGMI was added

Change-Id: Iad065c1a7c053a58e0d86becfb374215e316a611
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
2019-03-07 13:25:33 -05:00
Amber Lin f8028a40fd libhsakmt: Support x2APIC in topology
Current processor/cache topology code implements xAPIC architecture, which
is 8 bits addressability. This is not enough for a system having more than
255 processors. x2APIC is the extension of xAPIC architecture to support
32 bit addressability of processors. This patch detects the x2APIC
enablement and uses the extension leaf to get apicid when detected.

Change-Id: I0826585d02f696a46cd5efb9a6630c60af01e2d8
Signed-off-by: Amber Lin <Amber.Lin@amd.com>
2019-03-01 16:42:30 -05:00
Kent Russell d00ec779ce kfdtest.exclude: Temporarily blacklist IPC on gfx900
Due to the recent HMM changes, the KFDIPCTest can intermittently fail,
combined with CrossMemoryAttach consistently failing. Remove it for now
while Philip Yang investigates

Change-Id: Icf272100bb7882eff4202ad6f4ced63b569f4e7d
2019-02-28 07:29:47 -05:00
Sean Keely 67376e06ab Report SRAM ECC errors through the system event handler.
Modify the system event handler to support multiple users.
Name memory fault reason codes.

Change-Id: I1b5979b36ab15637eb2be59a61e2d57e76d0a70e
2019-02-27 18:08:07 -05:00
Kent Russell a0b8dd8462 Temporarily remove CMATest from gfx900
Per Philip Yang:
For forked child process, userptr allocated on heap (through malloc)
will have two vmas if child process malloc smaller size buf, free it,
this is on vma cloned from parent process. Then malloc larger size buf,
kernel will put some pages on previous freed space from vma cloned,
create new vma for the rest of pages. This is what IPCTest does.

Change-Id: I054771e20880f975d7cc774225f19aad5363843f
2019-02-27 07:05:42 -05:00
Sean Keely 3c3db0243e Loader support for SRAM ECC.
Change-Id: I0c6791c356d9186cc8dabae9fd698b1d4de19b09
2019-02-25 18:30:05 -05:00
Yong Zhao 1d478f3cf2 kfdtest: Add a result check in CreateCpQueue test
With the orginal code, CreateCpQueue will report failure if
WaitOnValue return false. Add EXPECT_TRUE() so that in that case
the failure is reported.

Change-Id: I043d013958b452d7ccb9538dc296d99d024abf01
Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
2019-02-21 17:42:45 -05:00
Sean Keely c56d86100b Add fine grain vram pool.
Part 1 of 2.
Enables fine grain vram over PCIe based on env flag.
Part 2 will extend to XGMI.

Change-Id: I8ad506e004b398d56d462b0200274eae2293a461
2019-02-21 13:08:11 -05:00
Sean Keely 344d964f9f Suppress exception reporting for well defined invalid signal handles.
hsa_exceptions with empty what() strings will not report in debug builds.

Change-Id: I0d424d3b1d3044808ece1720a460a57d68bf878e
2019-02-15 19:35:57 -05:00
Eric Huang 7349276860 kfdtest: add RAS tests
They are disabled for now.

Change-Id: I9c936130cbaf8c773f4b8e94bccf4af1f45eda65
Signed-off-by: Eric Huang <JinhuiEric.Huang@amd.com>
2019-02-15 15:03:32 -05:00
Philip Cox 90a3697e1d kfdtest: Blacklist BasicDebuggerSuspendResume
We need to black list this testcase temporarily because
it is failing intermittently.  The failure tends to only happen
when the certain build machine is used to build it.

This issue is being tracked by Jira ticket:
    ROCMOPS-389

Change-Id: Ic4682c9da389ed731cbc034dff57e6646bba0e9d
Signed-off-by: Philip Cox <Philip.Cox@amd.com>
2019-02-13 10:45:20 -05:00
Philip Cox ac6f089f26 kfdtest: Initial basic dbg suspend/resume testcase
A basic sanity test that tests the codepath for
the debugger suspend and resume code path.

Change-Id: If4c64f7bd6a1ef45068a33965b829725a78ce492
Signed-off-by: Philip Cox <Philip.Cox@amd.com>
2019-02-08 11:28:33 -05:00
Sean Keely 400304aa10 Remove stop using ROCm release tags for library version numbers.
Version is now a fixed string that matches previous internal builds.
This also matches released DEB/RPM builds (but not github versions).

Change-Id: Id4819b9de8c855250aadf1a1cebb187b5c031721
2019-02-06 19:22:53 -05:00
Ramesh Errabolu 3fbf03af76 Allows users, via env ROCR_VISIBLE_DEVICES, to surface a subset of Gpu devices
Change-Id: I5662639d5d70f054831969669f9d30dec356dd5a

Update per review comments

Change-Id: I18c7d7cb00b261493b61c2cf5454d486166f40d8
2019-02-06 02:02:29 -06:00
Chris Freehill 014945310a Fix boolean semantic error
Change-Id: Ic927370d5874af3f33105fca6ee0b581ebc6fa08
2019-01-31 14:03:48 -06:00
Yong Zhao 776077fe65 libhsakmt: Use a better name doorbell_mmap_offset
The previous name doorbell_offset is used too extensively throughout
the code and did not reflect the true usage.

Change-Id: I50d33f5c00e82c46cdf4264a78b8f925705bed6a
Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
2019-01-31 14:50:04 -05:00
Yong Zhao 7cd7830182 kfdtest: Use SDMA queue info from class KFDBaseComponentTest
Change-Id: Iacdb75006ef5f9ce6c4fbb0525d2c3a8535fdd23
Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
2019-01-31 14:00:57 -05:00
Yong Zhao 6857602cbc kfdtest: Include SDMA queue info in class KFDBaseComponentTest
This will facilitate us to avoid using family ID to differentiate the
SDMA engines and SDMA queues.

Change-Id: I8d6203cc5d330e9130a1b2624997c86ba53e8ae4
Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
2019-01-31 14:00:57 -05:00
Chris Freehill 626f13a88b Fix async memory test; temporarily disable NUMA memory test
Change-Id: I1c0618f5dba513c1cf8fafb5fc64e5c811df8454
2019-01-31 09:14:54 -05:00
Yong Zhao 51ee5c324a libhsakmt: Introduce HSA_ZFB environment variable
This variable is 0 by default. When set to 1, it means there is no frame
buffer, so all memory allocation is routed to system memory. This mode
is mainly used during emulation.

Use CoarseGrain for VRAM under ZFB mode

Change-Id: I29e8e98be56935e3ceb94782d70771cc45700749
Signed-off-by: Yong Zhao <Yong.Zhao@amd.com>
2019-01-29 19:46:26 -05:00
xinhui pan 41bf449e99 thunk: fix size overflow
Some test case alloc >4gb memory.
Use HSAuint64 in bytes and HSAuint32 in pages.

Change-Id: I0d5e6c299903b5898cfea024178a7a26b9ba3c90
Signed-off-by: xinhui pan <xinhui.pan@amd.com>
2019-01-28 10:49:45 -05:00
Sean Keely 65d39cc476 Unify APU and dGPU initial queue scratch allocation.
Both support dynamic scratch allocation so there is no reason
to preemptively allocate on APUs.

Change-Id: I22eaec01a83a091ee9dc1f594a1a9106e8dd81fc
2019-01-25 02:11:39 -05:00
Jay Cornwall b764991982 Set EOP buffer TC policy to non-coherent
Restores regression in dispatch latency.

Change-Id: I17869d3d515d8c1fa055a57afec2531903b88b16
Signed-off-by: Jay Cornwall <Jay.Cornwall@amd.com>
2019-01-23 12:21:01 -05:00
Jay Cornwall 079eadd71b Remove legacy microcode version check in GpuAgent::InvalidateCodeCaches
Fixes instruction cache invalidation when using microcode branches.

Change-Id: I932676e683983145f5c807204e592fb5e530c8af
2019-01-22 16:39:52 -06:00
Oak Zeng faba8950d4 Delete a few SDMA queue types
The design changed. Those are not needed any more

Change-Id: Ibb1230d1c34d6ac5153275f9334af45c73805f37
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
2019-01-22 14:49:05 -06:00
Oak Zeng dd6c6e7bc6 Revert "Add more SDMA queue type"
This reverts commit 5173e71810.

Change-Id: I0a52a44a5d141b398d0898bea52e4dcf41dc950f
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
2019-01-21 10:37:56 -06:00
Oak Zeng 124f77775c Revert "Create SDMA queue on specific engine"
This reverts commit 58b95e0a9d.

Change-Id: Idc0decd86364ed3441e9037b83be8be9953f0b3e
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
2019-01-21 10:37:46 -06:00