Loader support for SRAM ECC.
Change-Id: I0c6791c356d9186cc8dabae9fd698b1d4de19b09
Bu işleme şunda yer alıyor:
@@ -110,6 +110,10 @@ class Isa final: public amd::hsa::common::Signed<0xB13594F2BD8F212D> {
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const bool &xnackEnabled() const {
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return xnackEnabled_;
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}
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/// @returns True if this Isa has sram ecc enabled, false otherwise.
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const bool &sramEccEnabled() const {
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return sramEcc_;
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}
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/// @returns This Isa's supported wavefront.
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const Wavefront &wavefront() const {
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return wavefront_;
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@@ -181,13 +185,13 @@ class Isa final: public amd::hsa::common::Signed<0xB13594F2BD8F212D> {
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private:
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/// @brief Default constructor.
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Isa(): version_(Version(-1, -1, -1)), xnackEnabled_(false) {}
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Isa(): version_(Version(-1, -1, -1)), xnackEnabled_(false), sramEcc_(false) {}
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/// @brief Construct from @p version.
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Isa(const Version &version): version_(version), xnackEnabled_(false) {}
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Isa(const Version &version): version_(version), xnackEnabled_(false), sramEcc_(false) {}
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/// @brief Construct from @p version.
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Isa(const Version &version, const bool xnack): version_(version), xnackEnabled_(xnack) {}
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Isa(const Version &version, const bool xnack, const bool ecc): version_(version), xnackEnabled_(xnack), sramEcc_(ecc) {}
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/// @brief Isa's version.
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Version version_;
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@@ -195,6 +199,9 @@ class Isa final: public amd::hsa::common::Signed<0xB13594F2BD8F212D> {
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/// @brief Isa's supported xnack flag.
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bool xnackEnabled_;
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/// @brief Isa's sram ecc flag.
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bool sramEcc_;
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/// @brief Isa's supported wavefront.
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Wavefront wavefront_;
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@@ -209,7 +216,7 @@ class IsaRegistry final {
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/// @returns Isa for requested @p full_name, null pointer if not supported.
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static const Isa *GetIsa(const std::string &full_name);
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/// @returns Isa for requested @p version, null pointer if not supported.
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static const Isa *GetIsa(const Isa::Version &version, bool xnack);
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static const Isa *GetIsa(const Isa::Version &version, bool xnack, bool ecc);
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private:
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/// @brief IsaRegistry's map type.
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@@ -97,9 +97,10 @@ GpuAgent::GpuAgent(HSAuint32 node, const HsaNodeProperties& node_props)
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assert(err == HSAKMT_STATUS_SUCCESS && "hsaGetClockCounters error");
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// Set instruction set architecture via node property, only on GPU device.
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isa_ = (core::Isa*)core::IsaRegistry::GetIsa(core::Isa::Version(
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node_props.EngineId.ui32.Major, node_props.EngineId.ui32.Minor,
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node_props.EngineId.ui32.Stepping), profile_ == HSA_PROFILE_FULL);
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isa_ = (core::Isa*)core::IsaRegistry::GetIsa(
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core::Isa::Version(node_props.EngineId.ui32.Major, node_props.EngineId.ui32.Minor,
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node_props.EngineId.ui32.Stepping),
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profile_ == HSA_PROFILE_FULL, node_props.Capability.ui32.SRAM_EDCSupport == 1);
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// Check if the device is Kaveri, only on GPU device.
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if (isa_->GetMajorVersion() == 7 && isa_->GetMinorVersion() == 0 &&
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@@ -378,11 +378,17 @@ hsa_status_t IsIsaEquivalent(hsa_isa_t isa, void *data) {
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assert(data_pair->first.handle != 0);
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assert(data_pair->second != true);
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const core::Isa *isa1 = core::Isa::Object(isa);
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assert(isa1);
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const core::Isa *isa2 = core::Isa::Object(data_pair->first);
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assert(isa2);
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if (isa1->version() == isa2->version()) {
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const core::Isa *agent_isa = core::Isa::Object(isa);
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assert(agent_isa);
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const core::Isa *code_object_isa = core::Isa::Object(data_pair->first);
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assert(code_object_isa);
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// SRAM ECC enabled code may run on a system without ECC
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// but a system which has ECC enabled requires ECC enabled code.
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if (agent_isa->sramEccEnabled() && !code_object_isa->sramEccEnabled())
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return HSA_STATUS_SUCCESS;
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if (agent_isa->version() == code_object_isa->version()) {
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data_pair->second = true;
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return HSA_STATUS_INFO_BREAK;
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}
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@@ -68,7 +68,7 @@ static const uint kKfdVersionMinor = 99;
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#ifndef NDEBUG
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static bool PrintUsrGpuMap(std::map<uint32_t, int32_t>& gpu_usr_map) {
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(void)PrintUsrGpuMap; //Suppress unused symbol warning.
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(void)PrintUsrGpuMap; // Suppress unused symbol warning.
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std::map<uint32_t, int32_t>::iterator it;
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for (it = gpu_usr_map.begin(); it != gpu_usr_map.end(); it++) {
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int32_t usrIdx = it->second;
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@@ -44,6 +44,7 @@
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#include <cstring>
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#include <sstream>
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#include <utility>
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namespace core {
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@@ -74,6 +75,9 @@ std::string Isa::GetFullName() const {
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if (xnackEnabled_)
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full_name << "+xnack";
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if (sramEcc_)
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full_name << "+sram-ecc";
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return full_name.str();
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}
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@@ -180,8 +184,8 @@ const Isa *IsaRegistry::GetIsa(const std::string &full_name) {
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return isareg_iter == supported_isas_.end() ? nullptr : &isareg_iter->second;
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}
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const Isa *IsaRegistry::GetIsa(const Isa::Version &version, bool xnack) {
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auto isareg_iter = supported_isas_.find(Isa(version, xnack).GetFullName());
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const Isa *IsaRegistry::GetIsa(const Isa::Version &version, bool xnack, bool ecc) {
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auto isareg_iter = supported_isas_.find(Isa(version, xnack, ecc).GetFullName());
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return isareg_iter == supported_isas_.end() ? nullptr : &isareg_iter->second;
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}
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@@ -189,27 +193,29 @@ const IsaRegistry::IsaMap IsaRegistry::supported_isas_ =
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IsaRegistry::GetSupportedIsas();
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const IsaRegistry::IsaMap IsaRegistry::GetSupportedIsas() {
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#define ISAREG_ENTRY_GEN(maj, min, stp, xnack) \
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Isa amd_amdgpu_##maj##min##stp##xnack; \
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amd_amdgpu_##maj##min##stp##xnack.version_ = Isa::Version(maj, min, stp); \
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amd_amdgpu_##maj##min##stp##xnack.xnackEnabled_ = xnack; \
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supported_isas.insert(std::make_pair( \
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amd_amdgpu_##maj##min##stp##xnack.GetFullName(), \
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amd_amdgpu_##maj##min##stp##xnack)); \
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#define ISAREG_ENTRY_GEN(maj, min, stp, xnack, ecc) \
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Isa amd_amdgpu_##maj##min##stp##xnack##ecc; \
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amd_amdgpu_##maj##min##stp##xnack##ecc.version_ = Isa::Version(maj, min, stp); \
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amd_amdgpu_##maj##min##stp##xnack##ecc.xnackEnabled_ = xnack; \
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amd_amdgpu_##maj##min##stp##xnack##ecc.sramEcc_ = ecc; \
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supported_isas.insert(std::make_pair( \
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amd_amdgpu_##maj##min##stp##xnack##ecc.GetFullName(), \
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amd_amdgpu_##maj##min##stp##xnack##ecc)); \
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IsaMap supported_isas;
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ISAREG_ENTRY_GEN(7, 0, 0, false)
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ISAREG_ENTRY_GEN(7, 0, 1, false)
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ISAREG_ENTRY_GEN(7, 0, 2, false)
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ISAREG_ENTRY_GEN(8, 0, 1, true)
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ISAREG_ENTRY_GEN(8, 0, 2, false)
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ISAREG_ENTRY_GEN(8, 0, 3, false)
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ISAREG_ENTRY_GEN(8, 1, 0, true)
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ISAREG_ENTRY_GEN(9, 0, 0, false)
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ISAREG_ENTRY_GEN(9, 0, 2, true)
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ISAREG_ENTRY_GEN(9, 0, 4, false)
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ISAREG_ENTRY_GEN(9, 0, 6, false)
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ISAREG_ENTRY_GEN(7, 0, 0, false, false)
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ISAREG_ENTRY_GEN(7, 0, 1, false, false)
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ISAREG_ENTRY_GEN(7, 0, 2, false, false)
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ISAREG_ENTRY_GEN(8, 0, 1, true, false)
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ISAREG_ENTRY_GEN(8, 0, 2, false, false)
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ISAREG_ENTRY_GEN(8, 0, 3, false, false)
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ISAREG_ENTRY_GEN(8, 1, 0, true, false)
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ISAREG_ENTRY_GEN(9, 0, 0, false, false)
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ISAREG_ENTRY_GEN(9, 0, 2, true, false)
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ISAREG_ENTRY_GEN(9, 0, 4, false, false)
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ISAREG_ENTRY_GEN(9, 0, 6, false, false)
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ISAREG_ENTRY_GEN(9, 0, 6, false, true )
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return supported_isas;
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}
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@@ -68,6 +68,7 @@
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#define EF_AMDGPU_MACH_AMDGCN_GFX906_LC 0x02f
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#define EF_AMDGPU_MACH_AMDGCN_GFX909_LC 0x031
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#define EF_AMDGPU_XNACK_LC 0x100
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#define EF_AMDGPU_SRAM_ECC_LC 0x200
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// ELF Section Header Flag Enumeration Values.
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#define SHF_AMDGPU_HSA_GLOBAL (0x00100000 & SHF_MASKOS)
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@@ -583,7 +583,7 @@ namespace code {
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if (IsFinalizer && (EFlags & EF_AMDGPU_XNACK)) {
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NewName = NewName + "+xnack";
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} else {
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if (EFlags != 0 && (EFlags & EF_AMDGPU_XNACK_LC)) {
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if (EFlags & EF_AMDGPU_XNACK_LC) {
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NewName = NewName + "+xnack";
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} else {
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if (OldName == "AMD:AMDGPU:8:0:1")
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@@ -599,6 +599,9 @@ namespace code {
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}
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}
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if (EFlags & EF_AMDGPU_SRAM_ECC_LC)
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NewName += "+sram-ecc";
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return NewName;
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}
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@@ -631,6 +634,9 @@ namespace code {
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if (img->EFlags() & EF_AMDGPU_XNACK_LC)
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isaName += "+xnack";
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if (img->EFlags() & EF_AMDGPU_SRAM_ECC_LC)
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isaName += "+sram-ecc";
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return true;
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} else {
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std::string vendor_name, architecture_name;
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@@ -108,7 +108,7 @@ bool IsAccessibleMemoryAddress(uint64_t address)
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int32_t random_fd = 0;
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ssize_t bytes_written = 0;
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if (-1 == (random_fd = open("/dev/random", O_WRONLY))) {
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return false;
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return true; // Skip check if /dev/random is not available.
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}
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bytes_written = write(random_fd, (void*)address, 1);
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if (-1 == close(random_fd)) {
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