コミットグラフ

2445 コミット

作成者 SHA1 メッセージ 日付
Jay Cornwall 4fbffcdd9c Always allocate space for control stack at beginning of save area
Hardware block testing is done with the workgroup state offset
initialized to the control stack size on all ASICs. MEC microcode
assumes this space is available when the workgroup state offset is
reset after a context restore event.

Fixes context save area overrun when the full save area is used.

Change-Id: I8eeb62f97140c6fe409fe78b4497d833584feea8
Signed-off-by: Jay Cornwall <Jay.Cornwall@amd.com>
2017-07-04 10:12:02 -04:00
Harish Kasiviswanathan dc6ece67fd Fix fd leak if application forks
If the application forks, close the fd inherited from the parent.

Change-Id: I48e4157d5f0d6f04d07ecb23b719a23934687cdb
Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
2017-06-30 15:59:41 -04:00
Harish Kasiviswanathan 4d0697bf65 Honor ReadOnly bit in HsaMemFlags
Change-Id: I456cde81384bf0f4bf055711d94b731179706d28
Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
2017-06-28 15:02:21 -04:00
Amber Lin 897c4e2fff Replace printf/fprintf with pr_xxx
Libraries normally don't print messages. We use pr_err, pr_warn,
pr_info, and pr_debug to print messages to stderr when prints are
enabled for debugging.

Change-Id: I9caf719343aa618c88e7b500f9737a46702e424a
Signed-off-by: Amber Lin <Amber.Lin@amd.com>
2017-06-28 10:47:35 -04:00
Amber Lin ccfe739929 Introduce debug level to Thunk
Existing Thunk has printf/fprintf in the code while normally libraries
don't print any message. This patch introduces a print machenism similar to
how the Linux kernel prints to console based on the log level. The default
is not to print any message, but setting HSAKMT_DEBUG_LEVEL will enable the
prints.

Change-Id: Ic071e122d35a82260218e9914cde4815e69df742
Signed-off-by: Amber Lin <Amber.Lin@amd.com>
2017-06-26 16:33:17 -04:00
Evgeny c533229bc1 Block list extending
Change-Id: Id17efde25fce287296e80f2b37c77b15aa59b561
2017-06-23 16:37:02 -04:00
Amber Lin 13aadde56e Use environment variable to force gfx version
For experimental purpose, we need an option to change compute capability
by forcing the GfxIp version. This patch allows to use environment
variable HSA_OVERRIDE_GFX_VERSION=major.minor.stepping to replace the
default version. For example:
export HSA_OVERRIDE_GFX_VERSION=9.0.1

Change-Id: I90cfbd43619d9d3aebf53321d4e058f01bcd7088
Signed-off-by: Amber Lin <Amber.Lin@amd.com>
2017-06-22 18:15:17 -04:00
Evgeny 8618bf7e2c minor fixes, debug output, comments, using env vars, dead code
Change-Id: I08ad73b561709c1818d78a9191c96d6ad141a609
2017-06-22 18:04:26 -04:00
Evan Quan 5b3c9f0b31 Revert "Change gfx900 compute capability to 9.0.1"
This reverts commit 5114a9368b.


Change-Id: Id9c4f43462820bf09f25674fa30e6eb04098808e
Signed-off-by: Evan Quan <evan.quan@amd.com>
2017-06-20 15:36:09 +08:00
Amber Lin 6e113e2634 Free control stack correctly
ctl_stack_copy is allocated from malloc. It should be freed by free.

Change-Id: Ib924da20200d91f52f106fe173464d47862759a8
Signed-off-by: Amber Lin <Amber.Lin@amd.com>
2017-06-19 09:01:35 -04:00
Ramesh Errabolu 08e0bca567 Support Perf Cntrs (PMC) and Thread Trace (SQTT) over AQL queues
Change-Id: I716b722895d90b46914c31377e791ad602acecc1
2017-06-15 12:58:31 -04:00
Kenny Ho 5b4df54b10 Revert "Implement memory fault analysis through context save area"
This reverts commit 75c9506f9d.

Change-Id: Ibf11b764b383b9be291f3009a30550e1a1e2d115
2017-06-14 14:21:53 -04:00
Evgeny 35b376e2ee GFX8 API
Change-Id: I9d0c430e4199f043226c8897f3320a7973cbdeda
2017-06-14 12:24:28 -04:00
Jay Cornwall 75c9506f9d Implement memory fault analysis through context save area
When a fatal memory fault occurs the scheduler context-saves all queues
in the process and notifies the runtime through the memory event. The
saved state contains all GPR/LDS data at the moment of the fault.

Retrieve this state and present it to the user if HSA_DEBUG_FAULT is set
to "analyze" and the wavefront caused the fault. If amdgcn-capable objdump
is in the PATH invoke this to disassemble code around the PC.

Queue lifetime is now managed by the runtime to allow querying the
context save state for all active queues.

Change-Id: I6fee662fad1c4f9aa125bf5c53d7d0ea1ab32f95
2017-06-13 23:12:28 -04:00
Amber Lin 5114a9368b Change gfx900 compute capability to 9.0.1
9.0.1 is XNACK enabled gfx900 compile target. Compiler must generate ISA
that's XNACK enabled.



Change-Id: Ic4987132ef9f8d06d9e2bcdb8f7eeb875cdd2b44
Signed-off-by: Amber Lin <Amber.Lin@amd.com>
2017-06-13 17:04:42 -04:00
Evgeny 25035b8d09 Adding HSA extension AMD AQL profile library, see Readme.txt
Change-Id: Icbc1e0fb0185642eabbab411a2138ea030d22be8
2017-06-13 16:18:06 -04:00
Evgeny da831502ab Adding GFXIP and kernel code object
Change-Id: Ieb2dfea8d9e909efac583f541730d77b7d0c9679
2017-06-13 14:58:29 -05:00
Harish Kasiviswanathan 5e26827d05 Support deb package build for other architectures
Use build machine architecture to build debian package. Useful for
building on Power8 and ARM64 machines.

Change-Id: I97fc80a6723b139e753019a355f11ced0bba0dd4
Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
2017-06-13 12:12:37 -04:00
Konstantin Zhuravlyov d98e99949a Update hsa_isa_t entries
- Add 7.0.2 (consumer hawaii)
  - Add 9.0.1 (gfx900 with xnack)
  - Add 9.0.2
  - Add 9.0.3

Change-Id: I6a07797027c4eaf47038837c5ae51e05b2aba0e4
2017-06-12 14:34:11 -04:00
hthangir a0957bc679 The fallback path covers not just ARM64, need this for Power as well.
Change-Id: I7bbf76f77bd3ac47a0a0987c1e880e23834588e2
2017-06-07 14:45:29 -05:00
Qingchuan Shi cd35fb280a Patch target name in code object for future-proof
Change-Id: I6f12b5e5791bd1745ec3ab76d382fad50282e733
2017-06-05 19:08:27 -04:00
Chris Freehill 801bf4398c Added async. mem. copy sample.
Change-Id: I4fbb009181056c5f293d17720214b70588d44bdf
2017-06-05 17:20:51 -04:00
Amber Lin ceaaa1a57c A missing block in PMC
DB block was missing in the UUID look-up.

Change-Id: Ife5c25859bab6ec7fd99d0cd4d098ab044a08142
Signed-off-by: Amber Lin <Amber.Lin@amd.com>
2017-06-05 12:21:56 -04:00
Jay Cornwall 5db53ceda1 Enable SDMA on gfx9, disable on gfx8
gfx9 has passed qualification. gfx8 stability is under investigation.

Change-Id: Ia72211d47756399ecdfceafeb67c2ab34ebda834
2017-06-02 15:14:14 -05:00
Felix Kuehling 374bd89d8c Remove deprecated implementation of hsaKmtMapGraphicHandle
The KFD implementation has been removed and will not be upstreamed.
This API has been superseded by hsaKmtRegisterGraphicsHandleToNodes.

Change-Id: I5f2d8da3260974618cdb6ea3fdcd77d37b82c9cb
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Amber Lin <Amber.Lin@amd.com>
2017-06-02 13:52:19 -04:00
Amber Lin 683fc96325 Implement hsaKmtGetQueueInfo interface
For items in HsaQueueInfo, control stack information comes from KFD, CU
mask information is maintained in Thunk, and others (queue detail error
and queue type extended) are ignored (value = 0) at this point.

Change-Id: Ib21370b0f52b2bb4ebe6a9b4b6ec6139cccb25ca
Signed-off-by: Amber Lin <Amber.Lin@amd.com>
2017-06-01 14:15:54 -04:00
Kent Russell b78e0e152a Clean up thunk code
Use checkpatch.pl to fix the majority of errors. Some that remain and
will be excluded:
Use of typedefs/externs/volatile/sscanf
Lines over 80 characters

Remaining errors are due to misunderstanding the * symbol with typedefs

Also use this opportunity to spell manageable properly

Change-Id: I0b335e9cb3e1eea38bee27eaa1f582b2c9b09b38
2017-05-31 14:38:59 -04:00
Chris Freehill 1170244ae2 Added IPC sample
Change-Id: I980c430d6e091eb1abbc0df89ca74c96348bcd37
2017-05-31 09:47:16 -04:00
Chris Freehill adf201d6a5 Added rocrinfo sample
Corrected a few formatting issues with binary_search.cpp

Change-Id: I9dcc0a231c6b8c424b44f4ab17032ff51b81a1ba
2017-05-31 09:46:06 -04:00
Sean Keely c3e2a88ade Add preferred agent info to pointer info struct.
Lookup blit agent via pointer info in memory_fill.

Change-Id: I02feaf68bb9726858e8cb0ede6bc5f2b3707f5af
2017-05-31 05:16:05 -04:00
Sean Keely 59cc20d3cb Check mmap return address for allocation, not requested address.
Change-Id: Ifeb7b17976fc791e3256c70d57cb4d1324a8b960
2017-05-30 21:26:55 -05:00
Qingchuan Shi 77e5b30c41 remove finalizer usage from image ext
Change-Id: I282f02cedce790bf42f07c588fd50e346b9ba665
2017-05-29 20:44:52 -04:00
Sean Keely e38ff18990 Unmap GPUs when allow_access removes them from system pools.
Change-Id: Ib9eb88622fded43ebd9eddbf78ad6771a5b91e77
2017-05-17 20:58:05 -04:00
Felix Kuehling 8aeb933426 Add some additional gfx900 PCI IDs
Change-Id: I5f00f3b30a27285d75c606c1308abfe032ce1d02
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
2017-05-11 16:39:19 -04:00
Chris Freehill 8161ebb915 Refactored performance test code
Commented and flattened binary search sample.

Change-Id: Ib783292207c956d16003195924a3bcfbbde5039f
2017-05-11 14:45:45 -04:00
Felix Kuehling ea58703ece Fix uninitialized memory bug in hsaKmtWaitOnMultipleEvents
Use calloc to allocate event data. Otherwise random data may be filled
in for events that haven't actually signalled. This could trigger the
VM fault handler in the Runtime when no VM fault actually happened and
lead to intermittent HSA conformance test failures.

Change-Id: Icf702970e73a485b50633703c1b164f87fbb8606
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
2017-05-10 18:16:31 -04:00
Felix Kuehling 15764e2897 Fix KFD ioctl ABI
This change breaks the ABI, and aligns it with the upstream ABI.
It also fixes some ioctl structures that are not 64-bit safe and
consolidates ioctl numbers.

Change-Id: Ib79944721534bd55a5299c5baf7bb5b3246cccd2
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
2017-05-09 14:59:13 -04:00
Konstantin Zhuravlyov a777413400 Purge warning in amd_hsa_code.cpp
Change-Id: Iaa5d7af183af5e8c069365a1f0410365b46d53d5
2017-05-08 19:39:49 -04:00
James Edwards 001d43ce56 Change rpm preinstall script to post install
Change-Id: Iccc04902699bf0ba8b5269e1129b72cf69ef7f00
2017-05-07 14:02:54 -05:00
Felix Kuehling 5eb31b2ebe Switch to cleaned up memory management ioctls
Change-Id: Ib8971ef91138f2a051272b9b57f0ebd480e8e738
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
2017-05-04 16:29:37 -04:00
Harish Kasiviswanathan 3b2f064cbc Get PAGE_SIZE from system configuration
Change-Id: I87f383c443b873e13d36e80bfa034665bf493520
Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
2017-05-02 16:54:32 -04:00
Amber Lin ca06b0966b Add more non-priv PMC blocks to GFX9
This patch adds more non-privileged PMC blocks to GFX9/gfx900 to cover
blocks added in HSA Thunk Spec.

Change-Id: Ia3d953213a32536b2275231149f11ba060791442
Signed-off-by: Amber Lin <Amber.Lin@amd.com>
2017-05-01 09:14:03 -04:00
Amber Lin ed4a22e0d3 Add more non-priv PMC blocks to GFX8
This patch adds more non-privileged PMC blocks to GFX8 products: gfx801,
gfx803, and gfx803. Most of them have the same counter IDs on the same
block. For certain blocks when the product doesn't have the same counter
IDs, gfx8_xx_ is used to represent the product.

Change-Id: I059913c974bf2eb875fd1cf6f8b0d8c9c9bd7c14
Signed-off-by: Amber Lin <Amber.Lin@amd.com>
2017-04-27 11:22:12 -04:00
Amber Lin 9f19acbdb7 Add more non-priv PMC blocks to gfx70x/GFX7
HSA Thunk Spec was updated to include more non-privileged blocks for
profiling. This patch adds those newly added non-privileged blocks for
gfx70x.

Signed-off-by: Amber Lin <Amber.Lin@amd.com>

Change-Id: Id745ac236c871e8e61a128a2460784f9c9c354b6
2017-04-25 13:08:10 -04:00
hthangir 8aa19388a9 On GFX9+ amd_queue_t.scratch_backing_memory_location must store the queue's scratch backing store VA, not the offset.
Also fix permission in couple files.

Change-Id: I4203f8e5a36406b20562d8943ea5c341847f039a
2017-04-18 22:37:56 -05:00
Felix Kuehling 3f7e7933e3 Add debug option to control the number of guard pages
Change-Id: I18b10bcbb4d74a92f17330e44b2dbb4cea61da00
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
2017-04-10 11:40:39 -04:00
Felix Kuehling 34ddde0c50 Add debug option to check userptrs on registration
export HSA_CHECK_USERPTR=1 to check user pointers on registration. If
the pointer doesn't point to a valid mapping, there will be a segfault.

Change-Id: I459c0902cbc90338517fbf79678871ebfbe5183b
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
2017-04-10 11:40:39 -04:00
Amber Lin c119653add Create indirect IO links
KFD added all direct IO links to sysfs, so this patch removes all direct
links related code and modify the indirect links function to reflect the
change.

Change-Id: Iaec7b5f6c59f9034f8f960ca1fe1145d51dab367
Signed-off-by: Amber Lin <Amber.Lin@amd.com>
2017-04-07 07:18:13 -04:00
Christophe Paquot 617b6fa987 Separate gfx700 and AI architectures
Registers are different and it's cleaner to do as such

Change-Id: I36eee4c9c74deb43ca4666baa87894765a5f27b8
2017-04-07 00:14:22 -04:00
Jay Cornwall f0a1c7c4c6 Fix gfx9 trap handler to retrieve correct return address
The trap protocol changed between gfx8 and gfx9. The return address
is in trap temporaries [0,1] on gfx9 rather than [4,5] on gfx8.
Unfortunately SP3 changes the meaning of the ttmp register aliases
in gfx9, further confusing the issue.

Clean up later when LLVM assembly build is introduced to the runtime.

Change-Id: I84ea9bf3736f060dd95d0361f9d5a0f9a3576178
2017-04-05 17:33:49 -05:00