Commit-Graf

496 Incheckningar

Upphovsman SHA1 Meddelande Datum
Aaron Liu 1b7bb8646c libhsakmt: reorder the list of GPUs in enum asic_family_type
Put CHIP_gfx90a next to CHIP_gfx908 to keep all the GFXv9
chips together.

Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Change-Id: I32b4b7f7746ae4bdaff7e178f13307c1bcfa93e1


[ROCm/ROCR-Runtime commit: 80e4cb6261]
2021-07-30 10:23:56 -04:00
chen gong 820e03bd4c libhsakmt: add cyan skillfish support
Signed-off-by: chen gong <curry.gong@amd.com>
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
Change-Id: Ie26c2e156c9c4e68a6b36fe699adccf3f808b5e7


[ROCm/ROCR-Runtime commit: 860931557c]
2021-07-29 16:44:16 -04:00
Philip Yang c26f323d51 libhsakmt: Qyery pointer info flags for registered memory
hsaKmtQueryPointerInfo return vm_obj flags for all below registered
memory types other than hsaKmtAllocMemory, and set the CoarseGrain flag
correctly for:

Graphics: always coarse grain.

Shared: hsaKmtShareMemory pass mflags with export handle to KFD to store
in KFD objs, hsaKmtRegisterSharedHandle get mflags from KFD with import
handle.

Userptr: it is already coarse-grain by default, or based on mflags
provided in hsaKmtRegisterMemoryWithFlags call.



Change-Id: Idc23e8b0cf599b02580737639da2f9ef4ccd0c0d
Signed-off-by: Philip Yang <Philip.Yang@amd.com>


[ROCm/ROCR-Runtime commit: fa7b4a6268]
2021-07-22 21:14:46 -04:00
Philip Yang 178c985a8b libhsakmt: Query pointer info returns HsaMemFlags
Query pointer info returns KFD_IOC_ALLOC_MEM_FLAGS_* flags, it should
return HsaMemFlags, fix it by renaming vm_obj->flags to mflags and
always saving HsaMemFlags.

Use consistent function parameter and variable name to avoid confusion:
mflags for HsaMemFlags and ioc_flags for KFD_IOC_ALLOC_MEM_FLAGS_*
flags.

AMDKFD_IOC_GET_DMABUF_INFO return ioc_flags, translate it to mflags
using new helper fmm_translate_ioc_to_hsa_flags.



Change-Id: If9e117c507139c0166abb1ab0df8c233ef7e48a1
Signed-off-by: Philip Yang <Philip.Yang@amd.com>


[ROCm/ROCR-Runtime commit: 2c796e62be]
2021-07-22 21:14:46 -04:00
Aaron Liu e709fed186 libhsakmt: add yellow carp DID
Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Change-Id: If798dc733bc8d65c67922fb5d2e32aa1dada8381


[ROCm/ROCR-Runtime commit: 3d12437f1b]
2021-07-22 21:18:42 +08:00
Kent Russell 8d90ef172c libhsakmt: Add gfx1032 DID
0x73E3 DID was missing, add it.

Signed-off-by: Kent Russell <kent.russell@amd.com>
Change-Id: Id1ae2f268e0e8b5cfec5ae2065153fe73854b93a


[ROCm/ROCR-Runtime commit: ed62c7aa1c]
2021-07-22 07:37:19 -04:00
Jonathan Kim 6c4717ae7a libhsakmt: add runtime enable and disable calls
Add hsaKmtRuntimeEnable and disable.

Signed-off-by: Jonathan Kim <jonathan.kim@amd.com>
Reviewed-by: Felix Kuehling <felix.kuehling@amd.com>
Change-Id: I083f9293948e975546a1b3c1334cb41499b9ab1f


[ROCm/ROCR-Runtime commit: 1ce548829b]
2021-07-16 18:37:41 -04:00
Jonathan Kim 1001f27cb5 libhsakmt: update thunk api for exception handling
The debugger and debug agent no longer use the Thunk API.
Remove all deprecated functions and keep commented
references for future KFD tests.

Update and the keep the version checks for future use
and hsaKmtRuntimeEnable/Disable.

Signed-off-by: Jonathan Kim <jonathan.kim@amd.com>
Signed-off-by: Laurent Morichetti <laurent.morichetti@amd.com>
Reviewed-by: Felix Kuehling <felix.kuehling@amd.com>
Change-Id: Ia2f10d82f5ac36d0bd1bda233810f26e8a154d55


[ROCm/ROCR-Runtime commit: 31ac82617c]
2021-07-16 18:36:18 -04:00
Jonathan Kim fe03b35c8e libhsakmt: update create queue for exception handling
Update hsaKmtCreateQueue to initialize the new save area header with the
exception payload and event ID.

Signed-by-off: Jonathan Kim <jonathan.kim@amd.com>
Reviewed-by: Felix Kuehling <felix.kuehling@amd.com>
Reviewed-by: Sean Keely <sean.keely@amd.com>
Change-Id: Icd38062dc982cb29b30644699014eeb0b3e26d00


[ROCm/ROCR-Runtime commit: 96c7a5c9dc]
2021-07-16 18:34:35 -04:00
Felix Kuehling 14d821391e libhsakmt: Fix deadlocks in __fmm_release
__fmm_release is sometimes called with the aperture lock, and sometimes
without. Consistently call it with the aperture lock held and remove the
lock/unlock calls from this function.

Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Change-Id: I80dddc64cc0703e5eed8e9f1eb65b75a2c7ae2eb


[ROCm/ROCR-Runtime commit: 5fac7dcc3b]
2021-07-12 18:27:55 -04:00
Felix Kuehling 559bb50c6a libhsakmt: Fix deadlock in map_mmio
Unlock mutex if MMIO mapping fails. This happens on all GFXv8 GPUs.

Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Change-Id: I1dee1cbddefd9185c24ea79377f49f8ae2c5ff57


[ROCm/ROCR-Runtime commit: 19536080a8]
2021-07-09 17:07:42 -04:00
Aaron Liu 09d3f9749c libhsakmt: add yellow carp support
This patch is to add yellow carp support on thunk.

Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Change-Id: Icfecc3fd1f472c9924f934c6a5352448356d83df


[ROCm/ROCR-Runtime commit: a55551309c]
2021-07-06 21:46:28 -04:00
Sean Keely 4c960d7b3d Add error message to assertion.
Warn that HSA_FORCE_ASIC_TYPE may be needed if the engine major id
assertion fails.

Change-Id: I67e01e99c3d1bdc84630ccfae489dce5e77961b5


[ROCm/ROCR-Runtime commit: 408fca0278]
2021-06-28 23:18:43 -04:00
Philip Yang f94be2078c libhsakmt: fix multiple threads register userptr race
Aperture locking is too fine-grained, it has race between find userptr
and allocate userptr object.

Change _fmm_allocate_device and fmm_allocate_memory_object to not take
the aperture lock, the callers take it, this implements an atomic find
userptr or allocate a new one.



Change-Id: I6773404e22c1f4382a211c5a9817df23c5534a2a
Signed-off-by: Philip Yang <Philip.Yang@amd.com>


[ROCm/ROCR-Runtime commit: c4d5ee28f0]
2021-06-25 14:16:20 -04:00
Alex Sierra dd5e49d846 libhsakmt: change memory allocation alignment
it is to optimize memory allocation latency, which
changes alignment from 2MB to 1GB.

Signed-off-by: Alex Sierra <alex.sierra@amd.com>
Signed-off-by: Eric Huang <jinhuieric.huang@amd.com>
Change-Id: I7818e9f13b17e2c0992e75b17f978dc03a018a57


[ROCm/ROCR-Runtime commit: 973b35bc06]
2021-06-01 11:33:16 -04:00
Harish Kasiviswanathan 9a51b04c8e libhsakmt: Handle unaccessible p2p_links
Device cgroup can limit accessible devices. Handle the cases where
p2p_links are not accessible



Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Change-Id: I513dc75ad14e4f2d426cf2fbd301bcba12b4ee54


[ROCm/ROCR-Runtime commit: e28b3fe8b3]
2021-05-25 12:01:44 -04:00
Chengming Gui dc9f7ce1ff libhsakmt: Prepare Beige_goby support
PCI IDs have yet to be added later.

Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Change-Id: Ia0cbda17469b13fca807ce4eb74deae6f0d1eeac


[ROCm/ROCR-Runtime commit: ce995fe48d]
2021-05-18 02:04:06 -04:00
Mike Li a8ceb5c406 Add Size of VGPR and SGPR to HsaNodeProperties
Signed-off-by: Mike Li <Tianxinmike.Li@amd.com>
Change-Id: I7e6c0c5b9fd90c0bb5f3b7d35362a073afdcf9b8


[ROCm/ROCR-Runtime commit: 47ccc6604d]
2021-05-03 15:16:15 -04:00
Felix Kuehling ec289d055f libhsakmt: Add a new device ID for gfx90a
It is gfx90a VF device ID, for virtualization support.

Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Change-Id: I9e51d6b58c702d185e6758a9c511e9b8bc72c2f5


[ROCm/ROCR-Runtime commit: d8d8e3ddd6]
2021-04-30 13:42:27 -04:00
Harish Kasiviswanathan e4b86db92f libhsakmt: Add DIDs for gfx1032
Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Change-Id: I61e938db3763bc2cdb4e0ea74f9aaae810b5d27b


[ROCm/ROCR-Runtime commit: 9b95185a61]
2021-04-27 09:43:32 -04:00
Felix Kuehling 11e3516d74 libhsakmt: add XNACK API set/get mode
XNACK API for GPUs that support this mode. This API
makes calls to amdgpu driver to configure xnack mode.
It supports set xnack mode and query the current mode used.

Change-Id: If865fd0e3f900f008243dc49504e1a0694e1791a
Signed-off-by: Alex Sierra <alex.sierra@amd.com>


[ROCm/ROCR-Runtime commit: bb441d0bdd]
2021-04-16 00:10:41 -04:00
Felix Kuehling 024781d8e8 libhsakmt: add SVM thunk implementation
Implement SVM (Shared Virtual Memory) in the thunk.

Change-Id: I0380150d1d3da48070f9389a06f416d6059d6948
Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Signed-off-by: Sean Keely <Sean.Keely@amd.com>
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Sierra <alex.sierra@amd.com>


[ROCm/ROCR-Runtime commit: dd72f236c1]
2021-04-16 00:10:25 -04:00
Felix Kuehling f267a5251c libhsakmt: Query KFD version once after opening /dev/kfd
Query the KFD interface version once and store it in a global variable.
This makes it more efficient for KFD APIs to query the API version
later.

Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Change-Id: I267f3465f754e78fb21a7c42c5877cd68eaa9d05


[ROCm/ROCR-Runtime commit: 43ce63b68b]
2021-04-16 00:08:54 -04:00
Felix Kuehling 9216fb99b8 Revert "libhsakmt: add SVM thunk implementation"
This reverts commit a247255a6a.
SVM is not ready yet. This was merged by accident.

Change-Id: I372f7d293fd38429ec570bc0e0add7e612871594
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>


[ROCm/ROCR-Runtime commit: 4ebda913cd]
2021-03-10 22:33:34 -05:00
Felix Kuehling 0a400cac45 Revert "libhsakmt: add XNACK API set/get mode"
This reverts commit 2c1c2cfdf8.
SVM is not ready yet. This was merged by accident.

Change-Id: I7c0d835a0d3a448f2ac1094f818601e5d6363045
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>


[ROCm/ROCR-Runtime commit: a8f4c43fef]
2021-03-10 20:34:43 -05:00
Kent Russell 3a90583c47 Merge gfx90a into amd-staging
Conflicts:
	CMakeLists.txt
	include/hsakmt.h
	src/libhsakmt.h
	src/libhsakmt.ver
	src/queues.c
	src/topology.c
	tests/kfdtest/src/KFDMemoryTest.cpp
	tests/kfdtest/src/KFDTestUtil.hpp

Signed-off-by: Kent Russell <kent.russell@amd.com>
Change-Id: Ic2732e7c0b5e42c1a3a91223f65a65064b602181


[ROCm/ROCR-Runtime commit: 83d80074f7]
2021-03-02 07:48:22 -05:00
Oak Zeng 41a9f7d480 Allocate coherent uncached memory when HSA_DISABLE_CACHE is set
Set the KFD_IOC_ALLOC_MEM_FLAGS_COHERENT flag  and
KFD_IOC_ALLOC_MEM_FLAGS_UNCACHED flag to allocate
uncached coherent memory when HSA_DISABLE_CACHE
environment variable is set. At KFD driver,
Single KFD_IOC_ALLOC_MEM_FLAGS_UNCACHED flag is
not sufficient to allocate uncached memory. We
have to use both two flags to allocate uncached
memory.

Change-Id: Ie490f37b2e696314e60048f5b1b57442431696e9
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>


[ROCm/ROCR-Runtime commit: ae0e74095e]
2021-02-26 13:00:01 -05:00
Chengming Gui e54c5d29d3 libhsakmt: add DID for gfx1031
Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Change-Id: I1b890dda0ef9ee53c3950c17c106197167f210b9


[ROCm/ROCR-Runtime commit: c21466d735]
2021-02-26 17:40:13 +08:00
Oak Zeng c189479766 Make GPU mapping of memory as uncached if HSA_DISABLE_CACHE is set
Before gfx90a, coherent memory is uncached. So it was reasonable
when environment variable HSA_DISABLE_CACHE is set, memory is mapped
as coherent. On gfx90a, coherent memory can be cached, so mapping
memory as coherent can't guarantee memory is uncached. When
HSA_DISABLE_CACHE is set, we have to map memory as uncached.

Change-Id: Ia5ed4cf0ad6aef5644dc8c9e6632b52d606f06f4
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>


[ROCm/ROCR-Runtime commit: f132fb2cd0]
2021-02-23 12:20:29 -05:00
Harish Kasiviswanathan 4935d0f012 libhsakmt: Explicitly mark AQL buffers as UC
This change might be redundant if ROCr takes care of it

Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Change-Id: I7b67143a8ad21baa61b7eda7b8e5fe0ac1e33830


[ROCm/ROCR-Runtime commit: 10674916e4]
2021-02-23 12:20:29 -05:00
Harish Kasiviswanathan a3ef11ce1d libhsakmt: A+A: Mark buffers accessed by CP as UC
This change is for the A+A bring-up branch as it needs to made more
generic to handle all ASICs.

For A+A all the system buffers are mapped as NC (non coherent) unless
explicitly marked as UC (uncached). The coherency is then expected to be
handled by shader by explicitly using acquire/release instructions.

However, CP doesn't have same feature. The buffers used by CP thus have
to UC. For now queue buffer and Signal handler memory is marked as UC.

This change shouldn't affect other ASICs since Uncached flag is not used
in those. However, this change still need to be made more generic.

Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Change-Id: I56c37a809913f7f08c94d01b0572d0f4864939aa


[ROCm/ROCR-Runtime commit: 7c05c5240f]
2021-02-23 12:20:29 -05:00
Laurent Morichetti 289e4dc1db libhsakmt: Fix the ctrl stack size calculation
On gfx9, the maximum number of wavefronts per queue is the minimum of
40 waves per compute units, or 512 waves per shader engine.  On gfx10,
there can only be 32 waves per compute units.

Signed-off-by: Laurent Morichetti <laurent.morichetti@amd.com>
Change-Id: I148d1a4fe6c07cdbfaa1f77939eb29311c81c008


[ROCm/ROCR-Runtime commit: 4cf11c3a7e]
2021-02-23 12:20:29 -05:00
Laurent Morichetti c3940a1d44 Update the context save area size
Reserve some space in the context save area for the debugger's
use. There should be 32 bytes per wave for a given queue.

Change-Id: I65ddb6123d0f6afd3149844617ad19023009101d


[ROCm/ROCR-Runtime commit: a83f9b67ce]
2021-02-23 12:20:29 -05:00
Oak Zeng 992d1aef5b Support gfx90a real asic device id
Change-Id: Ib223b4e890899c3c4e468993a88f849bccc5d182
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>


[ROCm/ROCR-Runtime commit: 50debca7e9]
2021-02-23 12:20:29 -05:00
Alex Sierra 2c1c2cfdf8 libhsakmt: add XNACK API set/get mode
XNACK API for GPUs that support this mode. This API
makes calls to amdgpu driver to configure xnack mode.
It supports set xnack mode and query the current mode used.

Change-Id: If865fd0e3f900f008243dc49504e1a0694e1791a
Signed-off-by: Alex Sierra <alex.sierra@amd.com>


[ROCm/ROCR-Runtime commit: 3f45f602d4]
2021-02-23 12:20:29 -05:00
Alex Sierra a247255a6a libhsakmt: add SVM thunk implementation
Implement SVM (Shared Virtual Memory) in the thunk.

Change-Id: I0380150d1d3da48070f9389a06f416d6059d6948
Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Signed-off-by: Sean Keely <Sean.Keely@amd.com>
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Sierra <alex.sierra@amd.com>


[ROCm/ROCR-Runtime commit: 75e8fe383f]
2021-02-23 12:20:29 -05:00
Kent Russell 23f6c95324 Fix GCC warning regarding strncpy in CPU info
strlen(src) should not be used as the length in strncpy. Use memcpy
since we know the length of the string, and ensure that we
NULL-terminate regardless of length

Signed-off-by: Kent Russell <kent.russell@amd.com>
Change-Id: I21cc6d106510c69464e7ac9d3fc7da3a1e6d1a68


[ROCm/ROCR-Runtime commit: 731a06c704]
2021-02-23 12:20:29 -05:00
Eric Huang cceccd6d64 libhsakmt: add device id(0x46) for gfx90a mGPU model in topology
Signed-off-by: Eric Huang <jinhuieric.huang@amd.com>
Change-Id: I43f7c12906c408576e1eb55871d51e7a30569ede


[ROCm/ROCR-Runtime commit: 4b3b941bb3]
2021-02-23 12:20:29 -05:00
Jonathan Kim 480618489e libhsakmt: add host trap send
Adding host trap send command.

Signed-off-by: Jonathan Kim <Jonathan.Kim@amd.com>
Change-Id: I291c13f5905e00bc6685a980284a6abd0c98da78


[ROCm/ROCR-Runtime commit: f398d6d204]
2021-02-23 12:20:29 -05:00
Oak Zeng b1a9306ece Add gfx90a Gopher LSE DID (0x54)
Change-Id: Ic0a1e3d01373e0d6ba58e42188dced394423de82
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>


[ROCm/ROCR-Runtime commit: 97ae33f9de]
2021-02-23 12:20:29 -05:00
Amber Lin 8d96c2c71f libhsakmt: Add device ID used in Simnow
Simnow simulator uses 0x7400 as gfx90a's device ID

Signed-off-by: Amber Lin <Amber.Lin@amd.com>
Change-Id: I0022509ef643760bc906e537b4fc64f1523fd8bf


[ROCm/ROCR-Runtime commit: 8c6dd3cbae]
2021-02-23 12:20:29 -05:00
Eric Huang 9f7ae5b9e2 libhsakmt: add new flag for memory mapped as uncached
It is to provide an option to map specific memory as
uncached on A+A HW platform.

Signed-off-by: Eric Huang <JinhuiEric.Huang@amd.com>
Change-Id: Ib665cb306a0e78aba3ea5ee2f0e46cb62ae139f8


[ROCm/ROCR-Runtime commit: 2464bfc714]
2021-02-23 12:20:29 -05:00
Jay Cornwall 4d4b0d8d6b libhsakmt: Limit control stack size on gfx1032
Add to workaround list.

Change-Id: I01855d3404203760507879db5af23455407ac450
Signed-off-by: Jay Cornwall <jay.cornwall@amd.com>


[ROCm/ROCR-Runtime commit: 0fc623e873]
2021-02-08 13:09:13 -05:00
Ori Messinger 57cbb4a5f2 libhsakmt: Add Missing gfx1030 DID
The purpose of this patch is to add a missing device ID for gfx1030.
The missing ID "0x73A1" is now added to the "topology.c" file.

Signed-off-by: Ori Messinger <Ori.Messinger@amd.com>
Change-Id: I05a8a55e2c46f941a039fa72a6a5e76bf2a52736


[ROCm/ROCR-Runtime commit: 46c94662b7]
2021-01-29 07:18:49 -05:00
Gang Ba deb1bd7a90 libhsakmt: Correct number of io_links
Inside Docker, when limit GPU number to one, it may cause node
numIOLinks bigger than total node number.

Signed-off-by: Gang Ba <gaba@amd.com>
Change-Id: Ib84f2f05f8e0c70e48b9043b79aec02b5a214bbe


[ROCm/ROCR-Runtime commit: 7652932c38]
2021-01-19 19:46:25 -05:00
Prike.Liang a991dda23b libhsakmt: add more gfx90c family device support
This patch is to add Cezanne/Lucienne support on thunk.

Change-Id: Icd9b9913fa87bbfe6c71b36a2892d6ddb73e3ddd
Signed-off-by: Prike.Liang <Prike.Liang@amd.com>


[ROCm/ROCR-Runtime commit: 7e184ebb3a]
2021-01-15 09:48:41 +08:00
Chen Gong fc87256172 libhsakmt: enhancing support to gfx1033
This patch make get_block_properties() function work on gfx1033 platform

Change-Id: Ie5be7dfb38575eec8b39b91f3ee5b3a31abe8bd1
Signed-off-by: Chen Gong <curry.gong@amd.com>


[ROCm/ROCR-Runtime commit: 4cf50fdeaa]
2020-12-22 14:15:23 +08:00
Huang Rui d72d4943b4 libhsakmt: add gfx1033 support
This patch is to add Van Gogh support on thunk.

Change-Id: I75819329b865e4c38c097e83e3a0cb4e4f566fa2
Signed-off-by: Huang Rui <ray.huang@amd.com>


[ROCm/ROCR-Runtime commit: 9600760ff7]
2020-12-08 23:54:46 -05:00
Gang Ba 98bb73932d libhsakmt: Create P2P links
1. Create P2P links
2. Determine FRAMEBUFFER_PUBLIC/PRIVATE only based
   host-accessibility, not peer-accesssibility

Signed-off-by: Gang Ba <gaba@amd.com>
Change-Id: I15fccdc60386b453e2a47849a16df15157324b21


[ROCm/ROCR-Runtime commit: bedecc5957]
2020-11-17 15:43:12 -05:00
Gang Ba 0ddd455ead libhsakmt: add Streaming Performance Monitors APIs
Signed-off-by: Gang Ba <gaba@amd.com>
Change-Id: Iab9a98fa2079b7cae7158c524479dfc3fa672407


[ROCm/ROCR-Runtime commit: e8c0426c54]
2020-11-16 16:36:21 -05:00