Gráfico de Commits

2930 Commits

Autor SHA1 Mensagem Data
Evgeny 2cbff7ec5b Adding HSA extension AMD AQL profile library, see Readme.txt
Change-Id: Icbc1e0fb0185642eabbab411a2138ea030d22be8


[ROCm/ROCR-Runtime commit: 25035b8d09]
2017-06-13 16:18:06 -04:00
Evgeny f17287cec4 Adding GFXIP and kernel code object
Change-Id: Ieb2dfea8d9e909efac583f541730d77b7d0c9679


[ROCm/ROCR-Runtime commit: da831502ab]
2017-06-13 14:58:29 -05:00
Harish Kasiviswanathan 669b85f6df Support deb package build for other architectures
Use build machine architecture to build debian package. Useful for
building on Power8 and ARM64 machines.

Change-Id: I97fc80a6723b139e753019a355f11ced0bba0dd4
Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>


[ROCm/ROCR-Runtime commit: 5e26827d05]
2017-06-13 12:12:37 -04:00
Konstantin Zhuravlyov 79a238eb78 Update hsa_isa_t entries
- Add 7.0.2 (consumer hawaii)
  - Add 9.0.1 (gfx900 with xnack)
  - Add 9.0.2
  - Add 9.0.3

Change-Id: I6a07797027c4eaf47038837c5ae51e05b2aba0e4


[ROCm/ROCR-Runtime commit: d98e99949a]
2017-06-12 14:34:11 -04:00
hthangir f5c06c5911 The fallback path covers not just ARM64, need this for Power as well.
Change-Id: I7bbf76f77bd3ac47a0a0987c1e880e23834588e2


[ROCm/ROCR-Runtime commit: a0957bc679]
2017-06-07 14:45:29 -05:00
Qingchuan Shi 410520a18a Patch target name in code object for future-proof
Change-Id: I6f12b5e5791bd1745ec3ab76d382fad50282e733


[ROCm/ROCR-Runtime commit: cd35fb280a]
2017-06-05 19:08:27 -04:00
Chris Freehill af5b8f343f Added async. mem. copy sample.
Change-Id: I4fbb009181056c5f293d17720214b70588d44bdf


[ROCm/ROCR-Runtime commit: 801bf4398c]
2017-06-05 17:20:51 -04:00
Amber Lin b354927222 A missing block in PMC
DB block was missing in the UUID look-up.

Change-Id: Ife5c25859bab6ec7fd99d0cd4d098ab044a08142
Signed-off-by: Amber Lin <Amber.Lin@amd.com>


[ROCm/ROCR-Runtime commit: ceaaa1a57c]
2017-06-05 12:21:56 -04:00
Jay Cornwall dfbad5fa07 Enable SDMA on gfx9, disable on gfx8
gfx9 has passed qualification. gfx8 stability is under investigation.

Change-Id: Ia72211d47756399ecdfceafeb67c2ab34ebda834


[ROCm/ROCR-Runtime commit: 5db53ceda1]
2017-06-02 15:14:14 -05:00
Felix Kuehling fce3048015 Remove deprecated implementation of hsaKmtMapGraphicHandle
The KFD implementation has been removed and will not be upstreamed.
This API has been superseded by hsaKmtRegisterGraphicsHandleToNodes.

Change-Id: I5f2d8da3260974618cdb6ea3fdcd77d37b82c9cb
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Amber Lin <Amber.Lin@amd.com>


[ROCm/ROCR-Runtime commit: 374bd89d8c]
2017-06-02 13:52:19 -04:00
Amber Lin dd782c86c0 Implement hsaKmtGetQueueInfo interface
For items in HsaQueueInfo, control stack information comes from KFD, CU
mask information is maintained in Thunk, and others (queue detail error
and queue type extended) are ignored (value = 0) at this point.

Change-Id: Ib21370b0f52b2bb4ebe6a9b4b6ec6139cccb25ca
Signed-off-by: Amber Lin <Amber.Lin@amd.com>


[ROCm/ROCR-Runtime commit: 683fc96325]
2017-06-01 14:15:54 -04:00
Kent Russell c53049ce46 Clean up thunk code
Use checkpatch.pl to fix the majority of errors. Some that remain and
will be excluded:
Use of typedefs/externs/volatile/sscanf
Lines over 80 characters

Remaining errors are due to misunderstanding the * symbol with typedefs

Also use this opportunity to spell manageable properly

Change-Id: I0b335e9cb3e1eea38bee27eaa1f582b2c9b09b38


[ROCm/ROCR-Runtime commit: b78e0e152a]
2017-05-31 14:38:59 -04:00
Chris Freehill 2eb017d044 Added IPC sample
Change-Id: I980c430d6e091eb1abbc0df89ca74c96348bcd37


[ROCm/ROCR-Runtime commit: 1170244ae2]
2017-05-31 09:47:16 -04:00
Chris Freehill ac7d871853 Added rocrinfo sample
Corrected a few formatting issues with binary_search.cpp

Change-Id: I9dcc0a231c6b8c424b44f4ab17032ff51b81a1ba


[ROCm/ROCR-Runtime commit: adf201d6a5]
2017-05-31 09:46:06 -04:00
Sean Keely 42bb22d0cc Add preferred agent info to pointer info struct.
Lookup blit agent via pointer info in memory_fill.

Change-Id: I02feaf68bb9726858e8cb0ede6bc5f2b3707f5af


[ROCm/ROCR-Runtime commit: c3e2a88ade]
2017-05-31 05:16:05 -04:00
Sean Keely c0e1079b78 Check mmap return address for allocation, not requested address.
Change-Id: Ifeb7b17976fc791e3256c70d57cb4d1324a8b960


[ROCm/ROCR-Runtime commit: 59cc20d3cb]
2017-05-30 21:26:55 -05:00
Qingchuan Shi 1dfe4959e5 remove finalizer usage from image ext
Change-Id: I282f02cedce790bf42f07c588fd50e346b9ba665


[ROCm/ROCR-Runtime commit: 77e5b30c41]
2017-05-29 20:44:52 -04:00
Sean Keely 754935ee65 Unmap GPUs when allow_access removes them from system pools.
Change-Id: Ib9eb88622fded43ebd9eddbf78ad6771a5b91e77


[ROCm/ROCR-Runtime commit: e38ff18990]
2017-05-17 20:58:05 -04:00
Felix Kuehling 8b490f27f4 Add some additional gfx900 PCI IDs
Change-Id: I5f00f3b30a27285d75c606c1308abfe032ce1d02
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>


[ROCm/ROCR-Runtime commit: 8aeb933426]
2017-05-11 16:39:19 -04:00
Chris Freehill 9f1065771a Refactored performance test code
Commented and flattened binary search sample.

Change-Id: Ib783292207c956d16003195924a3bcfbbde5039f


[ROCm/ROCR-Runtime commit: 8161ebb915]
2017-05-11 14:45:45 -04:00
Felix Kuehling 2fe4ad9d9b Fix uninitialized memory bug in hsaKmtWaitOnMultipleEvents
Use calloc to allocate event data. Otherwise random data may be filled
in for events that haven't actually signalled. This could trigger the
VM fault handler in the Runtime when no VM fault actually happened and
lead to intermittent HSA conformance test failures.

Change-Id: Icf702970e73a485b50633703c1b164f87fbb8606
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>


[ROCm/ROCR-Runtime commit: ea58703ece]
2017-05-10 18:16:31 -04:00
Felix Kuehling e5b910be20 Fix KFD ioctl ABI
This change breaks the ABI, and aligns it with the upstream ABI.
It also fixes some ioctl structures that are not 64-bit safe and
consolidates ioctl numbers.

Change-Id: Ib79944721534bd55a5299c5baf7bb5b3246cccd2
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>


[ROCm/ROCR-Runtime commit: 15764e2897]
2017-05-09 14:59:13 -04:00
Konstantin Zhuravlyov 768644ba7a Purge warning in amd_hsa_code.cpp
Change-Id: Iaa5d7af183af5e8c069365a1f0410365b46d53d5


[ROCm/ROCR-Runtime commit: a777413400]
2017-05-08 19:39:49 -04:00
James Edwards b39fea499a Change rpm preinstall script to post install
Change-Id: Iccc04902699bf0ba8b5269e1129b72cf69ef7f00


[ROCm/ROCR-Runtime commit: 001d43ce56]
2017-05-07 14:02:54 -05:00
Felix Kuehling 2cc06c88ff Switch to cleaned up memory management ioctls
Change-Id: Ib8971ef91138f2a051272b9b57f0ebd480e8e738
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>


[ROCm/ROCR-Runtime commit: 5eb31b2ebe]
2017-05-04 16:29:37 -04:00
Harish Kasiviswanathan 49805f82b1 Get PAGE_SIZE from system configuration
Change-Id: I87f383c443b873e13d36e80bfa034665bf493520
Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>


[ROCm/ROCR-Runtime commit: 3b2f064cbc]
2017-05-02 16:54:32 -04:00
Amber Lin 0d55f4a1f7 Add more non-priv PMC blocks to GFX9
This patch adds more non-privileged PMC blocks to GFX9/gfx900 to cover
blocks added in HSA Thunk Spec.

Change-Id: Ia3d953213a32536b2275231149f11ba060791442
Signed-off-by: Amber Lin <Amber.Lin@amd.com>


[ROCm/ROCR-Runtime commit: ca06b0966b]
2017-05-01 09:14:03 -04:00
Amber Lin d4a47bae3e Add more non-priv PMC blocks to GFX8
This patch adds more non-privileged PMC blocks to GFX8 products: gfx801,
gfx803, and gfx803. Most of them have the same counter IDs on the same
block. For certain blocks when the product doesn't have the same counter
IDs, gfx8_xx_ is used to represent the product.

Change-Id: I059913c974bf2eb875fd1cf6f8b0d8c9c9bd7c14
Signed-off-by: Amber Lin <Amber.Lin@amd.com>


[ROCm/ROCR-Runtime commit: ed4a22e0d3]
2017-04-27 11:22:12 -04:00
Amber Lin edd6771ef1 Add more non-priv PMC blocks to gfx70x/GFX7
HSA Thunk Spec was updated to include more non-privileged blocks for
profiling. This patch adds those newly added non-privileged blocks for
gfx70x.

Signed-off-by: Amber Lin <Amber.Lin@amd.com>

Change-Id: Id745ac236c871e8e61a128a2460784f9c9c354b6


[ROCm/ROCR-Runtime commit: 9f19acbdb7]
2017-04-25 13:08:10 -04:00
hthangir ef38e563ba On GFX9+ amd_queue_t.scratch_backing_memory_location must store the queue's scratch backing store VA, not the offset.
Also fix permission in couple files.

Change-Id: I4203f8e5a36406b20562d8943ea5c341847f039a


[ROCm/ROCR-Runtime commit: 8aa19388a9]
2017-04-18 22:37:56 -05:00
Felix Kuehling 188902e6c0 Add debug option to control the number of guard pages
Change-Id: I18b10bcbb4d74a92f17330e44b2dbb4cea61da00
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>


[ROCm/ROCR-Runtime commit: 3f7e7933e3]
2017-04-10 11:40:39 -04:00
Felix Kuehling 0f42207171 Add debug option to check userptrs on registration
export HSA_CHECK_USERPTR=1 to check user pointers on registration. If
the pointer doesn't point to a valid mapping, there will be a segfault.

Change-Id: I459c0902cbc90338517fbf79678871ebfbe5183b
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>


[ROCm/ROCR-Runtime commit: 34ddde0c50]
2017-04-10 11:40:39 -04:00
Amber Lin 426aad482c Create indirect IO links
KFD added all direct IO links to sysfs, so this patch removes all direct
links related code and modify the indirect links function to reflect the
change.

Change-Id: Iaec7b5f6c59f9034f8f960ca1fe1145d51dab367
Signed-off-by: Amber Lin <Amber.Lin@amd.com>


[ROCm/ROCR-Runtime commit: c119653add]
2017-04-07 07:18:13 -04:00
Christophe Paquot 65f6986835 Separate gfx700 and AI architectures
Registers are different and it's cleaner to do as such

Change-Id: I36eee4c9c74deb43ca4666baa87894765a5f27b8


[ROCm/ROCR-Runtime commit: 617b6fa987]
2017-04-07 00:14:22 -04:00
Jay Cornwall 2c71b68fdb Fix gfx9 trap handler to retrieve correct return address
The trap protocol changed between gfx8 and gfx9. The return address
is in trap temporaries [0,1] on gfx9 rather than [4,5] on gfx8.
Unfortunately SP3 changes the meaning of the ttmp register aliases
in gfx9, further confusing the issue.

Clean up later when LLVM assembly build is introduced to the runtime.

Change-Id: I84ea9bf3736f060dd95d0361f9d5a0f9a3576178


[ROCm/ROCR-Runtime commit: f0a1c7c4c6]
2017-04-05 17:33:49 -05:00
Felix Kuehling d2064da64b Add guard page after each address space reservation
Guard pages help catch out-of-bounds memory accesses by applications
by generating VM faults (GPU) and segfaults (CPU).

Remove address space reservation from scratch aperture. That address
space is managed by the Thunk client. Guard pages would cause Thunk's
address space management to get out of sync with the client's.

Change-Id: I2e5aee2923a90186358cc7b0e131baf547996df6
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>


[ROCm/ROCR-Runtime commit: 11862b9f61]
2017-03-30 11:31:48 -04:00
Sean Keely 9734bc078a Remove comments, no functional change.
Change-Id: I923c037803a847352c2c50d9d47460cb0f01f22c


[ROCm/ROCR-Runtime commit: 8a5ff78be6]
2017-03-28 18:22:49 -05:00
Sean Keely 941c065513 Support async. queue errors and dynamic scratch without KFD events.
Change-Id: I4e9e7a37aa7b9c96b28ce79f562760283e02b1e0


[ROCm/ROCR-Runtime commit: 7dfeee5074]
2017-03-28 19:18:18 -04:00
Felix Kuehling 071c31f516 Add missing gfx900 device IDs
Change-Id: Ica5deb000279a508106125461af64a3851294b0a
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>


[ROCm/ROCR-Runtime commit: 53838c9818]
2017-03-24 16:03:46 -04:00
Sean Keely 5288e46340 Refactor signal_wait timing code and respect small timeouts.
Optimized for Gromacs and SHOC.

Change-Id: Ib674710268b41003259711a0e42d3e770a82018d


[ROCm/ROCR-Runtime commit: c4544906b9]
2017-03-23 23:55:48 -05:00
hthangir 4d121c2b97 We should be using the "used" gcc attribute.
Change-Id: I1589273740ae66e8d7d8186a88e2c411a2e0425c
See: https://gcc.gnu.org/onlinedocs/gcc/Common-Variable-Attributes.html#Common-Variable-Attributes


[ROCm/ROCR-Runtime commit: ba3f1cb476]
2017-03-20 11:57:39 -04:00
hthangir d4a8e87a35 Fix the comment to specify the right type of allocation required.
Change-Id: I8bda8d64010d466d6ca5e779d2042cca3f494ecf


[ROCm/ROCR-Runtime commit: 6c750f479d]
2017-03-20 11:56:54 -04:00
hthangir d775242246 Disable SDMA only on gfx900 until it is validated.
Change-Id: Ib960be3ca6d3fc4b664ba047243964b8c7a33f24


[ROCm/ROCR-Runtime commit: 7c6cde1871]
2017-03-20 11:55:22 -04:00
Amber Lin 65f40a36cf Add TCA block to PMC support
Add TCA to PMC tables.

Change-Id: Ia4164ab4581ea3f539706f534f672e5c24f5362f


[ROCm/ROCR-Runtime commit: 73eff30d7d]
2017-03-20 10:22:21 -04:00
Konstantin Zhuravlyov d0a8e27a35 [Loader] Fix memory allocations for code objects that
are larger than swap space available

Change-Id: I321487f96fe0a18998301a9058430c19427e5a94


[ROCm/ROCR-Runtime commit: a08d760c70]
2017-03-11 00:57:25 -05:00
Sean Keely b7256bae4e Support async error code 256, invalid vendor specific packet.
Change-Id: I491f34def4c3d54403864fa42670f7847a6141cc


[ROCm/ROCR-Runtime commit: 5f50e97d18]
2017-03-10 16:20:27 -05:00
Sean Keely 3ca460d72f Relax signal assertion.
Informs, in debug mode only, that a signal wait violated the HSA
spec with regard to the consuming agents list.  This list is used
for optimized signal type selection.

Change-Id: I5879f8f822d01af504ab913482b2532feb00be98


[ROCm/ROCR-Runtime commit: 2824786b3b]
2017-03-10 16:05:34 -05:00
Christophe Paquot d759209584 Add inc/ to some include
Change-Id: Id027b015c8785a132835a422d97a23b0bbce208a


[ROCm/ROCR-Runtime commit: 05d587ef79]
2017-03-09 19:45:01 -08:00
Sean Keely c02e8c67df Adjust signal sleep to reflect null kernel latency. Performance tested on Gromacs.
Change-Id: I3851148ee8544b15d840f2c26ca73a83f8d0df2e


[ROCm/ROCR-Runtime commit: 426d41e27c]
2017-03-09 15:20:53 -05:00
Amber Lin cddc3c032f Re-formatting IO link code
- Typo fix: *_link_tye to *_link_type and a missing word in comments
- Replace printf with fprintf(stderr
- Shorten lines to fit in 80 characters

Change-Id: Ibeb0b98d5c59d617ae06d9854a9dde16251ded52
Signed-off-by: Amber Lin <Amber.Lin@amd.com>


[ROCm/ROCR-Runtime commit: 3738a1b5f2]
2017-03-09 11:08:22 -05:00