Use ROC_ENABLE_LARGE_BAR (0/1) to toggle. The support is
enabled by default.
Change-Id: I6cb93a46594cb6f5e90bf6057738330225efb553
[ROCm/clr commit: d10d691e76]
This workaround is to avoid performance penalty of SDMA engine
taking a while to clock up from a lower DPM state. Add env var
GPU_FORCE_BLIT_COPY_SIZE (1024 by default for HIP in KB). Forcing
Src and Dst agent to be amdgpu makes ROCr take blit copy path for
what otherwise should have been SDMA copy
Change-Id: I222f687155f86000d17d66d25182e490b6710463
[ROCm/clr commit: 5f64e6e7ad]
[hipclang-vdi-rocm][perf]~45% to 50% of Performance drop on
rocBLAS_int8 test
- Enable AMD_OPT_FLUSH optimization by default to match HCC
- Disable CPU writes to GPU memory on boards with large bar,
because it requires HDP flush tracking.
- Enable L2 cache on kernel arguments, because L2 will be
invalidated on memory reuse .
Change-Id: I124cf250bdd4d19c523ce542c163813828f8fbdc
[ROCm/clr commit: 374f612b7c]
German Andryeyev
Aakash Sudhanwa
Jason Tang
Payam
Saleel Kudchadker
Laurent Morichetti