Commit Graph

628 Commits

Author SHA1 Message Date
Philip Yang a580869abd libhsakmt: Support contiguous VRAM allocation flag
Add HsaMemFlags Contiguous bit for hsaKmtAllocMemory to allocate
contiguous VRAM, to support RDMA device with limited scatter-gather
ability.

Check KFD ioctl minor version >= 17.

Change-Id: I0db00dad125b2b7be523f343082641f59b850423
Signed-off-by: Philip Yang <Philip.Yang@amd.com>


[ROCm/ROCR-Runtime commit: 97497c7efc]
2024-04-23 14:27:12 -04:00
Your Name f4ff320797 libhsakmt: Remove HsaMemFlag reserved bit init
HsaMemFlag new flags added and the number of the reserved bits is
reduced, and generate value overflow compilanation error.

The reserved bits is not used, remove the init.

Change-Id: I603596977dfd558ce31ead03711d7c5ce5ee5b71
Signed-off-by: Philip Yang <Philip.Yang@amd.com>


[ROCm/ROCR-Runtime commit: e2d742ac6f]
2024-04-23 14:27:12 -04:00
Stella Laurenzo 2fea138040 Properly nest build time headers to match arrangement at install time.
The build tree was missing a level of nesting, causing diversions based
on in-tree/out-of-tree use.
KR: Also fixed kfdtest paths

Change-Id: I8638b6d6227daabddd8eaa2aa387ba578b8dfab8
Signed-off-by: Stella Laurenzo <stellaraccident@gmail.com>
Signed-off-by: Kent Russell <kent.russell@amd.com>


[ROCm/ROCR-Runtime commit: a180fea5ad]
2024-04-01 17:10:40 -04:00
David Yat Sin 78ad630632 Set NUMA region to 0 when using GTTAccess flag
When allocating memory for MES AQL queue structure, the PreferredNode
is set to the device index of GPU to hint the location where the BO
needs to be created. But we need to ignore the device index when calling
bind_mem_to_numa.

Change-Id: Iae69fe02bfd48c5a3bd495319f6f2706d6e8aea2


[ROCm/ROCR-Runtime commit: 541d0dbbae]
2024-03-29 17:17:56 +00:00
Mihai Preda 69c283ef3d Free the malloc'ed event on page alloc failure
Change-Id: I009a9a6e2f67545c51470e86eac1adb78d6181b4
Signed-off-by: Mihai Preda <preda@users.noreply.github.com>
Signed-off-by: Kent Russell <kent.russell@amd.com>


[ROCm/ROCR-Runtime commit: fa0c182325]
2024-03-26 09:57:26 -04:00
David Yat Sin 19c7b5b4f6 libhsakmt: add PC sampling support
Add pc sampling support.

Change-Id: I08199024ba5a8eb2845c048d499fc8fcd260d2e8
Signed-off-by: David Yat Sin <David.YatSin@amd.com>
Signed-off-by: James Zhu <James.Zhu@amd.com>


[ROCm/ROCR-Runtime commit: f94e2530fb]
2024-03-25 15:53:38 +00:00
Philip Yang 96206ef888 libhsakmt: Add memory alloc flag GTTAccess
To allocate GTT memory for MES AQL queue structure, KFD will create GART
mapping for the memory to be accessed by MES.

Change-Id: Iae7b33d1e70861109f1551d3a71dc60dfde9de61
Signed-off-by: Philip Yang <Philip.Yang@amd.com>


[ROCm/ROCR-Runtime commit: 9fbe853fea]
2024-03-20 10:41:51 -04:00
Xinmudotmoe 3b6146e7db Update doorbell->size to support large default PAGE_SIZE kernels
Change-Id: I6fbe10ae3309f2f935d6782366cedb56dc1438c3
Signed-off-by: Xinmudotmoe <xinmu@xinmu.moe>
Signed-off-by: Kent Russell <kent.russell@amd.com>


[ROCm/ROCR-Runtime commit: 0c06bec272]
2024-03-13 09:18:42 -04:00
Sv. Lockal 760647dd19 Fix compilation on musl-based systems
This allows to build ROCT-Thunk-Interface for Alpine Linux, Gentoo with musl profile and so on.

List of changes:
* Fix redefinition of PAGE_SIZE from limits.h
* Use NAME_MAX from limits.h

Closes #65

Change-Id: Ibdb0ef5668a07b7b403fcc4a44cd2658e00a584a
Signed-off-by: Sv. Lockal <lockalsash@gmail.com>
Signed-off-by: Kent Russell <kent.russell@amd.com>


[ROCm/ROCR-Runtime commit: 9a89997b5f]
2024-03-11 10:46:55 -04:00
Harish Kasiviswanathan 2f05682f29 libhsakmt: Associate correct GPU with queue memory
Pass the correct gpu_id to KFD for system memory that is allocated for
the queue and eop buffer

Change-Id: I43bb6333560a7d9d38293c191303161ab1443b5d
Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>


[ROCm/ROCR-Runtime commit: 341ecaf1d9]
2024-02-26 14:20:16 -05:00
Harish Kasiviswanathan de1c7daba7 libhsakmt: Move global zfb_support to globals.c
zfb_support needs to accessed from multiple places, so move to globals.c
file

Change-Id: I40b487c26a13e7cc6fc01b671d6166e7114e02d2
Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>


[ROCm/ROCR-Runtime commit: 191caf46ac]
2024-02-26 09:08:11 -05:00
Harish Kasiviswanathan aeddcb8156 libhsakmt: Use correct gpu_id for GPU system memory
For GTT memory allocation if GPU is provided honour it.

Change-Id: Iea9a26bc44cd3daa2337845f53dc430787b0643b
Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>


[ROCm/ROCR-Runtime commit: 858dfd364f]
2024-02-25 10:45:36 -05:00
David Yat Sin 68522c65a9 HSA_USE_SVM to override SVMAPISupported node prop
When HSA_USE_SVM is 0, thunk uses non-SVM path, but upper layers still
use SVM path. That is not as expected.

Suggested-by: Lang Yu <Lang.Yu@amd.com>
Change-Id: I1ae0b4faa2f8af5ec69a81cfeb7661bd47d739d4


[ROCm/ROCR-Runtime commit: 0accd17b6e]
2024-01-16 22:44:38 -05:00
Jeremy Newton b2b4d5e7b5 Fix missing global symbol
If using hsakmt as a shared library

Change-Id: I66a1849a46bd7009813d49824d0d059e8a511038
Signed-off-by: Jeremy Newton <Jeremy.Newton@amd.com>


[ROCm/ROCR-Runtime commit: 42581d4172]
2024-01-04 11:14:39 -05:00
gaba dcf8b5fd6c libhsakmt: Fix CPU cache issue
For "Intel Meteor lake Mobile", the cache info is not in sysfs,
    That means /sys/devices/system/node/node%d/%s/cache is not exist,
    but system working fine.

Change-Id: Ie7c04426791a84c2288ff21df093226828a5f629
Signed-off-by: Gang Ba <Gang.Ba@amd.com>


[ROCm/ROCR-Runtime commit: 4bf73f521b]
2023-12-08 15:29:19 -05:00
David Yat Sin 8151aad0c2 libhsakmt: Handle HW_EXCEPTION events
Add new structures for HW Exception events and copy data from KFD to
expose to upper layers.

Change-Id: Icd5eb98997c47620e3b86277ab6d3abb7ed7d56f


[ROCm/ROCR-Runtime commit: 01ff2f7934]
2023-11-17 04:43:51 +00:00
Rajneesh Bhardwaj bb813a14d4 libhsakmt: Use MADV_HUGEPAGE for large allocations
For large memory allocations (>2MB) the thunk should use the
MADV_HUGEPAGE flag for madvise call to optimize allocation performance
on certain operating systems that rely on madvise hint when Traspatent
Huge Pages is not set to always.

Suggested-by: Joseph Greathouse <joseph.greathouse@amd.com>
Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@amd.com>
Change-Id: Ic0c753f89a177b0f715942d6e2a7108b08a85f20


[ROCm/ROCR-Runtime commit: 5047eb161f]
2023-10-12 17:01:34 -04:00
Torsten Keßler 7d30e82f41 Mark new symbols in ROCm 5.7.0 as global
Change-Id: Ia0391cac7f432f019dea94f98a145dbf8120817d


[ROCm/ROCR-Runtime commit: b44cca813d]
2023-10-11 15:50:27 -04:00
Philip Yang cf6745a36c libhsakmt: Set CWSR range granularity
Set CWSR svm range granularity to 0xff, then KFD will migrate the entire
CWSR range from VRAM back to system memory when recovering the CPU page
fault if rocgdb access CWSR area, this avoid the partial CWSR range
migration and stall CWSR GPU mapping issue.

This is a temporary workaround, it should be reverted once the KFD is
fixed.

Change-Id: I80a7248244574edba25b13858b7ebcf1c77b8930
Signed-off-by: Philip Yang <Philip.Yang@amd.com>


[ROCm/ROCR-Runtime commit: 85a47fa66b]
2023-10-06 10:46:40 -04:00
David Yat Sin 254e8219b3 libhsakmt: Fix incorrect flags for ext coherence
Change-Id: I89c838b9fbdb85589691f29806ae15884b25592f


[ROCm/ROCR-Runtime commit: 73efd3a14e]
2023-10-04 15:00:58 +00:00
James Zhu 0379e077b4 libhsakmt: remove share resource in performance counter
This share resource is for IOMMUv2 which is removed from
AMDGPU/KFD.

Change-Id: Ia6e9311f1adc56fac2c9e8fa05b24c5ec8c272a5
Signed-off-by: James Zhu <James.Zhu@amd.com>


[ROCm/ROCR-Runtime commit: d195deeec4]
2023-09-30 08:54:10 -04:00
James Zhu 6d52c1f332 libhsakmt: remove iommu_block which supports IOMMUv2 performance
IOMMUv2 is removed from AMDGPU/KFD.

Change-Id: I9fcf20ae9288cb40bb4b696284fc70534fb6484b
Signed-off-by: James Zhu <James.Zhu@amd.com>


[ROCm/ROCR-Runtime commit: 277d5e27ff]
2023-09-30 08:54:10 -04:00
James Zhu 9533c318bb libhsakmt: remove IOMMUv2 performance monitor support
IOMMUv2 is removed from AMDGPU/KFD.

Change-Id: Ib87f501c07d9de90e6b83b98f98daacd5913e98a
Signed-off-by: James Zhu <James.Zhu@amd.com>


[ROCm/ROCR-Runtime commit: 274b5b51ca]
2023-09-30 08:54:10 -04:00
David Yat Sin 351cbe9dc7 Add extended coherence memory flag
Add support for new flag for memory allocation that will provide
system-scope coherent atomics

Change-Id: I426d66223e8d2b570f69b4c0e61145ce9b2290d2


[ROCm/ROCR-Runtime commit: 8e06dce573]
2023-09-22 11:03:00 -04:00
Jonathan Kim c279ff343f kfdtest: add suspend and resume queues operation
Add base debug operations to suspend and resume queues.
Routine will return the number of queues successfully
suspended or resumed.

Signed-off-by: Jonathan Kim <jonathan.kim@amd.com>
Change-Id: I8f18317f70464b04231c5cf822e11d545ebfa02a


[ROCm/ROCR-Runtime commit: 5a675921ea]
2023-08-09 09:26:09 -04:00
Jonathan Kim 1435bb4887 kfdtest: add base debug class and debug attach/detach operation
Add base debug class and attach/detach operations.

Signed-off-by: Jonathan Kim <jonathan.kim@amd.com>
Change-Id: I60f3c166646f05838fec208ac2f59bba998c63f8


[ROCm/ROCR-Runtime commit: dd56b38c2f]
2023-08-08 15:59:35 -04:00
David Yat Sin b5f6c688b6 Keep libdrm device_handle on older libdrm
Even if the version of libdrm older and does not support the
amdgpu_device_get_fd function, the device_handle stored in
amdgpu_handle[] is still valid and can be returned via
hsaKmtGetAMDGPUDeviceHandle.

Change-Id: I024a3e82e6cfebac5577aefe359b067746c4023e


[ROCm/ROCR-Runtime commit: 66b66e42cd]
2023-08-01 10:52:26 -04:00
Jonathan Kim 72bd0f3a8d libhsakmt: add debug trap thunk call for testing
Add generic thunk call for debug testing that assumes
caller populations trap arguments correctly.

Signed-off-by: Jonathan Kim <jonathan.kim@amd.com>
Change-Id: I33a0bc66ca77e29f5b663d4bfe73f8684df8bfb6


[ROCm/ROCR-Runtime commit: aaab019960]
2023-07-26 10:29:27 -04:00
Alex Sierra 6fb53cdb1b src: add debug API to support GPU core dump
Functions to API added to extract the following information from KFD
Runtime information, device info and queues snapshot.

Signed-off-by: Alex Sierra <Alex.Sierra@amd.com>
Change-Id: If995ecc54497ab61189bb0f209c64af0bbb0f56f


[ROCm/ROCR-Runtime commit: 0cbf26c148]
2023-06-26 18:58:15 +00:00
Alex Sierra b5ba77994a add hsaKmtGetRuntimeCapabilities API
Queries for runtime capabilities after its being enabled

Signed-off-by: Alex Sierra <alex.sierra@amd.com>
Change-Id: I098c0e9862c0c1d5e304b111cdc281c0ccd09691


[ROCm/ROCR-Runtime commit: 5e0a32d7b3]
2023-06-26 18:58:15 +00:00
James Zhu 498b718e83 libhsakmt: add event age tracking
Keeping last signaled event age to avoid race conditions
for HSA_EVENTTYPE_SIGNAL when event age init value is non-zero.

Change-Id: Ifb9a11a6868e5762a9f92f579e45a0a2c8fa1017
Signed-off-by: James Zhu <James.Zhu@amd.com>


[ROCm/ROCR-Runtime commit: a0cbf90b90]
2023-06-10 11:41:50 -04:00
Alex Sierra 6998fcee45 libhsakmt: include changes for upstream debugger API
Signed-off-by: Alex Sierra <alex.sierra@amd.com>
Change-Id: Id296e13dff431c7a151c5aae0b93412b1e116467


[ROCm/ROCR-Runtime commit: 728162c2c8]
2023-06-02 15:56:19 -04:00
Kent Russell c11b1022f1 fmm.c: Fix possibly initialized variable usage
If we end up in the first if clause, aperture_base is not set, unlike
the other 2 clauses. Initialize it to NULL at declaration time, and only
change its value in the final else clause, where we set it to
aperture->base

Change-Id: I2bf44dc93cae8a03e66f41cedd85d57be2115bba
Signed-off-by: Kent Russell <kent.russell@amd.com>


[ROCm/ROCR-Runtime commit: 718d95de77]
2023-05-30 15:46:14 -04:00
Xiaogang Chen 682173c851 libhsakmt: allow gpu nodeid arrary is null and number of gpu is zero.
Allow hsaKmtRegisterGraphicsHandleToNodes parameters NodeArray be null
and NumberOfNodes be zero at same time. It is the case we want the imported
buffer not be registered by kfd. Set gpu_id_array = NULL explicitly to avoid
free uninitialized gpuid array.

Report: Yat Sin, David<David.YatSin@amd.com>
Signed-off-by: Xiaogang Chen<Xiaogang.Chen@amd.com>
Change-Id: I3babc1160c9573e38dd11d81965c8de2b70cae2e


[ROCm/ROCR-Runtime commit: f6183f937e]
2023-05-29 00:15:14 -04:00
Xiaogang Chen ebce4177ad libhsakmt: have hsaKmtMapMemoryToGPU return same value as fmm_map_to_gpu.
Have hsaKmtMapMemoryToGPU return same value as fmm_map_to_gpu to keep consistency.

Signed-off-by: Xiaogang Chen<Xiaogang.Chen@amd.com>
Change-Id: Ifabb72301e1d5a6c1310973bb1321714e12a1fa6


[ROCm/ROCR-Runtime commit: 7e4e57ae5f]
2023-05-29 00:15:14 -04:00
Xiaogang Chen dd8954e83e libhsakmt: query/use render node fds that libdrm uses.
Query render node fds that libdrm uses for current process and
use them at Thunk if available.

v2: avoid naming conflict with amdgpu_device_get_fd from amdgpu.h

Signed-off-by: Xiaogang Chen<Xiaogang.Chen@amd.com>
Change-Id: Id7288c03730f4a4c9c3644e37ca4725fec71a471


[ROCm/ROCR-Runtime commit: ac1db60fc2]
2023-05-29 00:15:14 -04:00
Xiaogang Chen 6800fbec43 libhsakmt: add NodeId at HsaGraphicsResourceInfo.
Return GPU NodeId that exported the DMA buffer from amdgpu graphic driver
at fmm_register_graphics_handle.

Signed-off-by: Xiaogang Chen<Xiaogang.Chen@amd.com>
Change-Id: Iaeccce6e6d0b7e27f10b15ed89d1b5310d03d44b


[ROCm/ROCR-Runtime commit: 9bebb276be]
2023-05-29 00:15:14 -04:00
Xiaogang Chen eeec387ca2 libhsakmt: add DMABuf import without address allocation.
When gpu map info is not provided import DMABuf without VA assigned.

Signed-off-by: Xiaogang Chen<Xiaogang.Chen@amd.com>
Change-Id: I996ab4eb46977af5064126529c28a8bf20a67292


[ROCm/ROCR-Runtime commit: 989c6c617c]
2023-05-29 00:15:14 -04:00
Xiaogang Chen 4d6b75d857 libhsakmt: support allocating a fixed address at mmap_aperture.
When HsaMemFlags.ui32.FixedAddress=1 allocate fixed address at mmap_aperture.

Signed-off-by: Xiaogang Chen<Xiaogang.Chen@amd.com>
Change-Id: I1f3b532ec3c1a4fb0962126a0bd56441abaf6a9c


[ROCm/ROCR-Runtime commit: d2a37894bb]
2023-05-29 00:15:14 -04:00
Xiaogang Chen 038916c727 libhsakmt: update HsaPointerInfo for address-only allocated VRAM.
Signed-off-by: Xiaogang Chen<Xiaogang.Chen@amd.com>
Change-Id: Ib88b34dff772997d2b2e5f3c7e333cef3092ef56


[ROCm/ROCR-Runtime commit: 11ac57d293]
2023-05-29 00:15:14 -04:00
Xiaogang Chen b4b03aca20 libhsakmt: support vram-only and VA-only alloc/free.
Signed-off-by: Xiaogang.Chen <Xiaogang.Chen@amd.com>
Change-Id: I47cf53642d2ea197c08b20e84d7cae04b2d431e0


[ROCm/ROCR-Runtime commit: 0138487aa4]
2023-05-29 00:15:14 -04:00
Xiaogang Chen ee0c668706 libhsakmt: add/init a new manageable_aperture_t from NON_CANONICAL space.
This new manageable_aperture_t is used for VRAM allocation-only and
VA allocation-only.

Signed-off-by: Xiaogang Chen<Xiaogang.Chen@amd.com>
Change-Id: I3866ef9d35386d6aef7b6934ac8d4a89ef843b50


[ROCm/ROCR-Runtime commit: 0a2989083b]
2023-05-29 00:15:14 -04:00
Xiaogang Chen 51392afedb libhsakmt: Revert "libhsakmt: Update FD creation logic"
This reverts commit 89ce41694f.
Current amdgpu exposes one render node for one gpu node/partition,
revert to previous way to open render node at Thunk.

Signed-off-by: Xiaogang Chen<Xiaogang.Chen@amd.com>
Change-Id: I436be74f8e872a7ab5c4a1420b4ea884f5a00e57


[ROCm/ROCR-Runtime commit: cc4fb2d1a9]
2023-05-29 00:15:14 -04:00
Bing Ma a868d0972b libhsakmt: Add support functions for ASAN
Add support functions to remap the first page of device memory (GPU/GTT)
to share host ASAN logic.

Signed-off-by: David Yat Sin <David.YatSin@amd.com>
Change-Id: I4c27d5417ba80a172dccb0a079a597c5dc1c8f85


[ROCm/ROCR-Runtime commit: 1e6d728730]
2023-05-17 13:38:19 -04:00
xinhui pan a945a9824e thunk: Fix and optimise for pointer range search
Previous code might fail to get the correct ln node. And trigger extra
walk through of the tree. Fix it.

While walking through the tree, better to search from right to left as
the node->start likely close to *address*.

Change-Id: If86ddf73e59a1eb88225d1ea90797818e8165488
Signed-off-by: xinhui pan <xinhui.pan@amd.com>


[ROCm/ROCR-Runtime commit: 77761836ae]
2023-04-20 19:36:29 -04:00
Jesse Zhang 76c0c340f9 libhsakmt: Add compute core check for APU
We should check compute core instead of cpu core,
in order to exclude the case of APU.

Signed-off-by: Jesse zhang <jesse.zhang@amd.com>
Change-Id: I2ec2a6807f51f49f80e0e500f5d9af81c2efae37


[ROCm/ROCR-Runtime commit: 4d54d6e706]
2023-04-17 09:34:37 +08:00
Graham Sider d8960d6b57 libhsakmt: Mask stepping version for GC 9.4.3 checks
GC 9.4.3 to set gfx target version to 9.4.x dependent on revision and
capabilities. Due to this, where applicable, mask off the gfx target
stepping version and only check major/minor version (9.4). There are no
collisions due to this change since GC 9.4.3 is the only ASIC that uses
gfx target version 9.4.x.

Signed-off-by: Graham Sider <Graham.Sider@amd.com>
Change-Id: I72803e594c421f054d18ccfa7e92c507128fa5be


[ROCm/ROCR-Runtime commit: 831d1ad352]
2023-04-14 12:03:23 -04:00
Graham Sider 543fe60c96 libhsakmt: Fix queue destroy SVM path free size
Use q->total_mem_alloc_size for munmap in SVM codepath of free_queue.

Signed-off-by: Graham Sider <Graham.Sider@amd.com>
Change-Id: I2fecaa1ddb337b1fe71f9cbba45a0c9467eff0c0


[ROCm/ROCR-Runtime commit: ae659e5427]
2023-04-14 10:03:38 -04:00
Mukul Joshi dc0d800908 libhsakmt: Fix memory leak on queue destroy for GFX9.4.3
Currently, on queue destroy, context save restore memory is freed
only for a single XCC. Instead, we need to free the entire context
save restore memory, which was allocated for all XCCs.

Signed-off-by: Mukul Joshi <mukul.joshi@amd.com>
Change-Id: I51ebb12fa8d5ebed41979d68e74f7c5392dca062


[ROCm/ROCR-Runtime commit: a713fb766e]
2023-04-14 10:03:38 -04:00
David Belanger 7f91f54b27 libhsakmt: EOP Removal
Do not allocate the EOP buffer when not required.

Signed-off-by: David Belanger <david.belanger@amd.com>
Change-Id: I1664a3f0a882219a72278174006cdb8d46fd4f5e


[ROCm/ROCR-Runtime commit: 252a2cf959]
2023-04-14 10:03:38 -04:00