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22 Commits

Author SHA1 Message Date
Saleel Kudchadker b2b8545eb6 SWDEV-260345 - Manage constant buffer for blit 
- Leverage managed buffer that would use chunks for fill pattern. Use a
different chunk for the next fill to avoid wait

Change-Id: I254483c867e112f66564ffd8f55e0a605d8896c9


[ROCm/clr commit: 175ad024d3]
 2022-07-12 12:41:02 -04:00
Ajay 9fcc7a7219 SWDEV-332522 - streamOpsWrite & streamOpsWait to accept memory offset 
Change-Id: I4b6ecb4d80c093d038d86616a637c4bb465ae24e


[ROCm/clr commit: d2f837d25f]
 2022-04-25 14:59:36 -04:00
kjayapra-amd 31c0525344 SWDEV-305527 - Changes to handle memset blit kernel that takes width, height and depth. This also fixes SWDEV-317261. 
Change-Id: Ic85f63a95d9d8f48884fc8c7fd95cbb496dfbbca


[ROCm/clr commit: 7fb80a027a]
 2022-03-31 09:02:33 -04:00
German Andryeyev a7be0eb56a SWDEV-316824 - Fix P2P compute copy path 
Use device memory object for the GPU VA address look-up.

Change-Id: I76bf58b29205f7b3ba1bf68e9fcca69421267203


[ROCm/clr commit: 3fd4a67670]
 2022-02-15 13:20:13 -05:00
kjayapra-amd cfb15c6c5d SWDEV-294420 - Ignore Image blit kernels if image instructions are not supported. 
Change-Id: I145172672b0b032aa722649b0c4ca9267e3e5c85


[ROCm/clr commit: 7413b7f79b]
 2021-10-05 18:12:44 -04:00
Sourabh 936e0836a8 SWDEV-292525 - [vdi] Path to streamOps shaders 
Implementation to use a blit kernel to perform
a hipStreamWait/write instead of an AQL packet.

Change-Id: I462671ed5cec37144dfe97ff66439249196117c1


[ROCm/clr commit: cbb8d82bdb]
 2021-09-27 13:59:35 -04:00
Saleel Kudchadker 36ec8c8871 SWDEV-297448 - Add 64bit and 16bit write support 
For the fillBuffer shader, if there are two 32bit writes to a MMIO
register, it can get dropped. It has to be a single 64bit write.
Add optimization to fillBuffer to write 64bit and 16bit writes.

Change-Id: I3aa78e027898f8ae01e9c8f09004615673720c2b


[ROCm/clr commit: 21ba34d0fe]
 2021-09-08 12:30:04 -04:00
agunashe 49f0546637 SWDEV-293742 - Update copyright end year VDI repo 
Change-Id: I69d2fea4a7a43adf96ccea794270e4af991c5261


[ROCm/clr commit: d96481fb36]
 2021-08-22 23:56:07 -07:00
Ravi C Akkenapally 6629930067 SWDEV-179105 - Stream Operations: Add support for Wait and Write 
Change-Id: Ibffa1d6d573826b64763da280074a77271d66808


[ROCm/clr commit: 0a5f9a3b10]
 2021-02-15 17:02:38 -08:00
German Andryeyev f96e973378 SWDEV-257787 - Add engine tracking per signal 
- The logic will trace compute, sdma read/write operations and
apply signals when necessary
- ROC_CPU_WAIT_FOR_SIGNAL, ROC_SYSTEM_SCOPE_SIGNAL
and ROC_SKIP_COPY_SYNC were added to control the tracking

Change-Id: I9e8e6174c63bf7784f7ab00964e2918c8667d364


[ROCm/clr commit: dbc7abaecf]
 2021-01-25 12:34:45 -05:00
German Andryeyev 30cf81fc93 Add HSA signal global tracking logic. 
Implement the global class for signals tracking per device queue.
Switch to the new tracking mechanism.

Change-Id: I3c4dda04b34e6d18d6a95510d84102909633b415


[ROCm/clr commit: 8698aeef0d]
 2021-01-08 12:57:33 -05:00
Jason Tang 6778b6e4e2 SWDEV-263539 - More Target ID fix in GSL path 
On behalf of Tony Tye. The bootleg passes CQE Baffin/Ellesmere test.

Change-Id: I4c21d21b3aaba360682ef15b8a4dda239f8af276


[ROCm/clr commit: d4316141b7]
 2020-12-14 16:48:55 -05:00
Anusha Godavarthy Surya de10e7e1e6 SWDEV-244600 - HIP BLIT code object needs to have reserved symbol name 
Change-Id: I8401fea5eab71c0f7414eec0666066d9553a6622


[ROCm/clr commit: 093f7fa3ca]
 2020-08-06 01:14:06 -04:00
Tao Sang 44eb207f8d Apply constexpr on global constant varaibles 
When HIP_ENABLE_DEFERRED_LOADING=0, many global variables will be
referenced but they are not initialized in that early time. The patch
will use constexpr to initialze global constant varables in compile
time.

Change-Id: I9d538b7abc6a0ce700ec3332b97fc144db5fc1ef


[ROCm/clr commit: fdef6f722f]
 2020-07-22 22:14:13 -04:00
German Andryeyev e20f40119c Fix async mem clear 
Optimization for the fence release removed a sync for mem fill.
Add simple const buffer management forr the filled pattern to avoid
pattern overwriting with the async fills.

Change-Id: I63773ac09ceec31d5396d24570e4647ff096326b


[ROCm/clr commit: 2ce6bbebc4]
 2020-05-20 11:13:41 -04:00
Michael LIAO b785d25506 Clear executable permission. 
Change-Id: Ia0d363b1ba89d7947e5b5a55cb67edba86f0515e


[ROCm/clr commit: 503ef06555]
 2020-05-07 10:38:58 -04:00
Alex Xie a97194485a SWDEV-232894 Port hipMemcpy optimizations from HCC to VDI 
Apply the optimization to change for OpenCL too.
Clean up some unnecessary checks.

Change-Id: I840261fe35baeeadeba7388e86779d482f509aad


[ROCm/clr commit: 6c5a42b33c]
 2020-04-30 11:06:28 -04:00
German Andryeyev 715425d074 SWDEV-232807 
[ROCm][TCT][HIP] cooperative stream test case is failing.

Make sure lockXfer() in the blit manager returns a valid value.
Port the latest PAL backend logic into the ROCr backend.
This change doesn't fix the issue, reported in the ticket.

Change-Id: I54101a824f49a2dcfbbf5414cb5b3af41745306d


[ROCm/clr commit: 89133a7301]
 2020-04-23 15:01:02 -04:00
kjayapra-amd 236705c62f SWDEV-229840 - Improve error messages on ROCCLR Layer. 
Change-Id: Iab7d9156cdc206db86385aa05023a0095ed40f92


[ROCm/clr commit: 7458bf9964]
 2020-04-19 20:01:49 -04:00
jujiang 375649abc5 SWDEV-196333-hipCopyhammer_H2D&hipCopyHammer_D2H tests fix return false case 
Change-Id: I919e098f8b1b8c41b200bd32dcf108977c472b43


[ROCm/clr commit: 518a75ca66]
 2020-02-24 15:08:21 -05:00
Laurent Morichetti e284923583 Update copyright info 
Change-Id: Ia4f9ff0f5f873b4223a8cca154188bb0d2f1abba


[ROCm/clr commit: b4c6143a2f]
 2020-02-04 09:26:14 -08:00
Laurent Morichetti 011f3e945b Merge branch 'origin/pghafari/vdi-prototype' into lmoriche/amd-master 
Change-Id: Id3b833d405596735becb3346f3b08c6da57033fe


[ROCm/clr commit: 20c7173849]
 2020-01-30 20:12:13 -08:00