Commit graph

192 Commits

Autor SHA1 Nachricht Datum
Jatin Chaudhary 2a16ef5d04 Adding and populating available registers per cu value
Change-Id: Ide012038a9d74b20166ce1e69a9f2c0cbdce0d73


[ROCm/clr commit: d0f009a0ee]
2020-09-28 05:30:23 -04:00
kjayapra-amd a3212c53b7 SWDEV-241896 - Remove extern support in ROCclr/HIP since compiler added Texture Reference support.
Change-Id: I2cf27e13a53860fe11e9245c9cbdcb8bd88a7872


[ROCm/clr commit: 4071cf1a16]
2020-09-25 10:20:16 -04:00
Jason Tang 4c0e5d238d Avoid using sdma engine if there's none
Change-Id: Id8d373683f3e1667ab461b4c5b8b490377b64cc0


[ROCm/clr commit: 40b432f992]
2020-09-25 09:48:10 -04:00
Aryan Salmanpour b01d49542c Fix a crash when printf used in a kernel launched on a stream with custom CU mask
SWDEV-249719 - root cause: queues with custom CU mask are not inserted
into queuePool_ (i.e., queue of reusable HSA queues) of ROC device class
causing a crash when creating hostcall buffers for printf

Change-Id: Ieee7005d9a5a30b3113394ce23ee65927126d0d6


[ROCm/clr commit: 2e199bd492]
2020-09-25 09:25:19 -04:00
kjayapra-amd 267f3797f5 SWDEV-253063 - Code changes to make Image Buffer Workaround only for targets gfx 10.1
Change-Id: I17044a1c0775f427b9ba712eb3fd5ab21ed88b0e


[ROCm/clr commit: 18352d189b]
2020-09-23 11:07:15 -04:00
kjayapra-amd b3e8c5cdb0 SWDEV-252542 - Fixing Win Compilation on SWDEV-241902.
Change-Id: If76f79002b265dccf6da4acef1ff9372d8b0a2ff


[ROCm/clr commit: 7462e39954]
2020-09-18 12:11:56 -04:00
Satyanvesh Dittakavi c667dc6fa0 set free mem to zero avoding underflow
Change-Id: I964b41695fb41712624146c5959a35b37eacf52d


[ROCm/clr commit: 90c694988b]
2020-09-18 11:56:57 -04:00
kjayapra-amd 3e6cf63a83 SWDEV-241902 - Changes to pass file descriptor and offset to load code object.
Change-Id: I0243cccdeaa533b2a56fde42f12d5424c3b63a3b


[ROCm/clr commit: a66c56d641]
2020-09-15 07:54:24 -04:00
kjayapra-amd 095c775e83 SWDEV-251941 - Adding gfx1030,gfx1031 support to mainline
Change-Id: I752dff86651a55f4fbf719e84ee7d3ec49f5f207


[ROCm/clr commit: 11b723a605]
2020-09-14 09:07:44 -04:00
Vladislav Sytchenko 60b435a7c3 Fix typo
Change-Id: I571e84cab9258dfd5e94b70865505f452ed89016


[ROCm/clr commit: be0d98b433]
2020-09-12 20:16:27 -04:00
Jason Tang 61c85339c3 SWDEV-252095 - Fix progvar_prog_scope_misc test Aborted (core dumped)
The progvar_prog_scope_misc test expects CL_DEVICE_MAX_MEM_ALLOC_SIZE to be multiple of integer.

Change-Id: Ic0690f5ab06ffa3feafb718beabbcf83ab53978c


[ROCm/clr commit: 740f1ba0aa]
2020-09-11 12:36:39 -04:00
Sarbojit Sarkar f111d53228 Fix for memory leak detected in hipModule*load [SWDEV:250740]
Change-Id: I8c4930b64764620a896079b14b27f6f87fbad292


[ROCm/clr commit: 677208f2de]
2020-09-10 10:50:46 -04:00
Laurent Morichetti c863b2074b Use std::atomic
Replace amd::Atomic with std::atomic. Remove make_atomic uses by
converting the variable to std::atomic and making sure the memory
order is relaxed when synchronizes-with is not needed.

Delete utils/atomic.hpp.

Change-Id: I0b36db8d604a8510ac6e36b32885fd16a1b8ccfa


[ROCm/clr commit: 5d4b6f74d3]
2020-09-09 14:55:29 -04:00
German Andryeyev 6e0c211730 Reduce the default size of the signal pool
Implement dynamic signal pool grow per allocated queue

Change-Id: Ie8b17937d72c29cc49e59639c4b2023ea984b14c


[ROCm/clr commit: e68d671a51]
2020-09-09 09:53:52 -04:00
Tao Sang c6a000f618 Fix compiling issue exposed by opencl TC build
1.Some files are not built in rocclr so the issues are
not found in rocclr build. But the issues are exposed
in TC build.
2.Clear unused codes in test cmake file.

Change-Id: I1ad4decdf4df5237b93e1ea2547eb39a19f7dc4a


[ROCm/clr commit: 65075e72f1]
2020-09-08 12:40:22 -04:00
Jason Tang eaf65e59ae Remove gfxipVersion_ from device level
Change-Id: I11485beffdb9371a20d7abcaa1d1774c102db574


[ROCm/clr commit: 5ecce5c287]
2020-09-07 11:33:49 -04:00
Alex Xie f8dd901fc2 SWDEV-250136 - [LNX][Navi21][OCL over ROCr] OpenCL-GL sharing failed
Change-Id: Id61f649f035964d14f6399dbea03137c11f8eaea


[ROCm/clr commit: 2c2665665d]
2020-09-06 10:40:56 -04:00
kjayapra-amd bfaa8f8ab5 SWDEV-240800 - P2P device attributes support
Change-Id: I2b060a66715f676dfb7136940e69e21288f509d8


[ROCm/clr commit: 0163d8acc0]
2020-09-03 14:41:53 -04:00
Vladislav Sytchenko 618619e903 Navi21 support
Change-Id: I7263556fdb85dc0152a2a72cc0ec4d7cd5e978a6


[ROCm/clr commit: d6e89ec371]
2020-09-03 11:14:37 -04:00
Sarbojit Sarkar a5c2a7ff84 Fix for HIP_VISIBLE_DEVICE [SWDEV-247751]
Change-Id: Iff0ca6646f9d97b1ffa378c3cdc44159b6bf8ad0


[ROCm/clr commit: 8ac8384aea]
2020-09-02 02:08:56 -04:00
Alex Xie e0cb881d91 SWDEV-249516 - [Lnx][Navi][rocm]conformance image read write tests data error
Change-Id: Ie1c4fda953198b49ed66fea9da23e62c686d9cea


[ROCm/clr commit: 7e8f7b5927]
2020-09-01 17:20:58 -04:00
Tao Sang 5f84733220 Fix OpenCL test crash on some devices
Replace constexpr with const in kernel source
codes because some kernel compiler doesn't
support constexpr.

Replace scheduler with __amd_rocclr_scheduler
due to name change.

Change-Id: I1ad4ddcdf1df5237b83e1ea2447eb39a19f7dc4a


[ROCm/clr commit: 9c5465f9e1]
2020-08-29 12:29:07 -04:00
Tao Sang f3b85497ae Replace private libelf with elfio
Change-Id: I4c630d78f7bf23dda85ec8480bb2790864405657


[ROCm/clr commit: e986f5c820]
2020-08-26 12:32:13 -04:00
Jason Tang da0a525982 SWDEV-239502 - fix interop regression
When header==0, the legitimate packet->header is wiped out, so also add an assert.

Change-Id: I6b3037d4618719262b0d7c1792bd54f768a63660


[ROCm/clr commit: 19d1497fa2]
2020-08-25 18:11:18 -04:00
Aryan Salmanpour 771a8abb90 SWDEV-248499 Fix a crash when printf is used with cooperative kernels
root cause - cooperative queue is not inserted into queuePool_ (HSA queues) of ROC device calss causing a crash when creating hostcall buffers for printf

Change-Id: I3f9aceb4e5fe6a7c7a2a549a4bb0a3511fe02799


[ROCm/clr commit: d2b9d267b2]
2020-08-25 16:51:34 -04:00
Jason Tang bbe0df36bf SWDEV-239502 - Create copyImageBuffer_ without flags
Change-Id: Ifcb5992d58f3419635d2aca2d51f2dacd7cd466d


[ROCm/clr commit: c33470ab4d]
2020-08-14 17:25:58 -04:00
agodavar 8b61666254 SWDEV-245503 - Improve hipModuleLoad performance
Change-Id: Icbcd37d9b4e6d79f296cc8693edf25689b19fa11


[ROCm/clr commit: e914f281ff]
2020-08-14 05:24:52 -04:00
Vlad Sytchenko 7395ae1366 Remove unnecessary SVM commit
Change-Id: I5cb887ead166401a59b0c980f29fd615b19745be


[ROCm/clr commit: 6780a9ac66]
2020-08-13 13:21:03 -04:00
Jason Tang 8199283c0e SWDEV-239502 - Fix image test regression
Change-Id: Iea35fb0f1964d09a35131b4a20ac8f6f82850a8e


[ROCm/clr commit: db5a2d4c2d]
2020-08-13 11:58:20 -04:00
German Andryeyev a5ca15a599 Enable prefetch async functionality
Fix a typo with the name define, when compilation wasn't enabled.
Force CPU prefetch if system was forced in runtime

Change-Id: Id4b578f9fa44a45426fdb5d8ecb1da803aa42313


[ROCm/clr commit: 6e69258b69]
2020-08-13 11:09:10 -04:00
Jason Tang 3315ef8a45 SWDEV-247463 - Fix regression: ocltst segfaults
Change-Id: Iadb55ba45d6c8ade0757fd970ac4c6cde1805de3


[ROCm/clr commit: 152a2dfb5a]
2020-08-09 11:28:09 -04:00
Jason Tang d4cbe1a339 Fix HSAIL build
Change-Id: I34209b3ae0ce0eefc30e464fd7f081a0b62449b0


[ROCm/clr commit: 7bb671fa55]
2020-08-07 17:18:38 -04:00
German Andryeyev 4a2b2e77f6 Sync the current queue for P2P staging
P2P staging uses device queues for transfer, hence the current
queue must be in sync

Change-Id: I8372a60590eed9dde62cb4c67ef4df5df82a8e8d


[ROCm/clr commit: 0dc47d55d2]
2020-08-07 14:36:50 -04:00
Jason Tang c926997eb8 Use ARCTURUS
Change-Id: Ib25d150c9314180178d5cf00835a06e47c02c2a9


[ROCm/clr commit: 6f8eaff4df]
2020-08-07 11:14:24 -04:00
Jason Tang 04054e9b60 SWDEV-246565 - Remove passing -msram-ecc to Comgr
Change-Id: I1604a0014186a5779561da3ec3eefec65aff5c37


[ROCm/clr commit: f8f6bc16a1]
2020-08-06 12:48:53 -04:00
Jatin Chaudhary ba5507f650 Adding device memory channel information
Change-Id: I47dfa3daff97b1e3f42484dde5a4aa64244ac544


[ROCm/clr commit: 2f3df8e691]
2020-08-06 06:54:35 -04:00
Saleel Kudchadker 820a456980 Add Queue profling param and toggle for HIP
Use signal timestamps if NDRange command takes forceProfile flag.

Change-Id: Ib7f187d781fd78a7346818afb3344a9378f4c104


[ROCm/clr commit: ec73340348]
2020-08-06 03:09:53 -04:00
Anusha Godavarthy Surya de10e7e1e6 SWDEV-244600 - HIP BLIT code object needs to have reserved symbol name
Change-Id: I8401fea5eab71c0f7414eec0666066d9553a6622


[ROCm/clr commit: 093f7fa3ca]
2020-08-06 01:14:06 -04:00
Jason Tang e1b0edf35c SWDEV-246687 - Do not use std::vector reference as class member cuMask_
The current implementation creates default reference in the stack and assigns it to class member cuMasks_, so whenever the content of the stack changes, cuMask_ would change.

Change-Id: Iefab63c335d504b83c4ae90bd34ae76c6afb8f3c


[ROCm/clr commit: 8ef5da00c7]
2020-08-05 16:57:36 -04:00
German Andryeyev e34eaf17b9 Process cache coherency before mem dependency tracker
Optimizaiton to remove extra syncs uncovered a bug with the cache
coherency layer, there runtime could lose the track of mem address
if coherency layer performed a sync.

Change-Id: I25647cfa4a4be9cdbd8577ff076a740bbdac79c8


[ROCm/clr commit: 91a25df04f]
2020-08-04 16:33:18 -04:00
Vlad Sytchenko 9d72bf6523 Fix typo
Change-Id: I8b659508f567afa126aeb7749b536b443935e3df


[ROCm/clr commit: 9d0b0c32a9]
2020-08-04 11:15:21 -04:00
Vlad Sytchenko c98a71dc9e Only enable HIP for Vega20 on non-ROCm platforms
SWDEV-245906

All asics will still be supported for developer builds.

Change-Id: I0eac2246162d133fe63449c200d996fe05bd51bd


[ROCm/clr commit: 24c1c48db7]
2020-07-27 13:09:58 -04:00
Tao Sang 44eb207f8d Apply constexpr on global constant varaibles
When HIP_ENABLE_DEFERRED_LOADING=0, many global variables will be
referenced but they are not initialized in that early time. The patch
will use constexpr to initialze global constant varables in compile
time.

Change-Id: I9d538b7abc6a0ce700ec3332b97fc144db5fc1ef


[ROCm/clr commit: fdef6f722f]
2020-07-22 22:14:13 -04:00
Jason Tang 11f8a869f1 SWDEV-232197 - Fix PAL build
Change-Id: Iad306077cadfd8de1491ac0a188eee4802d8ce1f


[ROCm/clr commit: 2800fc2fa3]
2020-07-22 17:10:03 -04:00
Jason Tang fdf3ebad76 SWDEV-232197 - Use TargetID for action_info_set_isa_name()
Change-Id: I6661a2bbc2e55586c1b5029694d67cb54a4f23a6


[ROCm/clr commit: 65f4230494]
2020-07-22 13:47:17 -04:00
Freddy Paul 872b0bedee Align to new hsa cmake target usage.
HIP or any ROCm component above HIP may not be calling
hsa-runtime directly. OpenCl and HIP are the two components
calling ROCclr and to bring in the transitive dependency of
thunk,ROCR,amd_comgr it is better to have the dependency
chain set correctly in the ROCclr cmake target. With this
change OpenCl or HIP should not be setting ROCR dependency
directly.

This helps to link OpenCl(libamdocl.so) link statically with
comgr,hsa,thunk.

Change-Id: I0d538b7abc6a0ce700ec3332b97fc144db5fc5ff


[ROCm/clr commit: 6b8ae3dd77]
2020-07-22 11:21:09 -04:00
Jatin Chaudhary 7dae2632b9 Adding AnyOrder Flag
Change-Id: I6baaef42b98adfbc8cf2605e175ec007e008045f


[ROCm/clr commit: 48690f29e9]
2020-07-22 00:25:04 -04:00
Tao Sang 10f1bfc765 Add numa lib detection in cmake
If numa lib is in building system, define ROCCLR_NUMA_SUPPORT to
support numa; otherwise, don't support numa.

Change-Id: I3848d7fdec5a3813ff1edad9b71ff04372dc0b9a


[ROCm/clr commit: 214827defa]
2020-07-21 14:58:56 -04:00
Rahul Garg 3398448fb0 Handle size 0 symbols
Change-Id: I1629c5027ec5f9af48c8e9e0696829b844423096


[ROCm/clr commit: 60473ae542]
2020-07-21 10:10:36 -04:00
Jason Tang cd1ee42c36 SWDEV-232197 - Use HSA_ISA_INFO_NAME as the TargetID
TargetID will be passed to LC compiler.

Change-Id: I0385634922c11d53b57ebd596047698c47bda72b


[ROCm/clr commit: 8b7e0f3cfe]
2020-07-21 09:24:03 -04:00