İşleme Grafiği

1119 İşleme

Yazar SHA1 Mesaj Tarih
Aidan Belton-Schure 451b0ce768 SWDEV-482851 - Do not release last suballocator chunk
Change-Id: Ib28dc9df68e454ee0c0c699c1ff17588fd55f802
2025-01-13 10:14:40 -05:00
Daniel Livingston 541c449ce2 SWDEV-489003 - [Ubertrace] OCL/HIP profiles are missing event instrumentation
Adds UberTrace support for pre-dispatch markers and barrier begin/end markers.

Moves shared definitions out of palgpuopen.hpp into shared header
palcapturemgr.hpp.

Change-Id: I9f464c689e7ff12c54eca043fc1ad65e1836a64f
2025-01-10 11:28:52 -05:00
Anusha GodavarthySurya 683a942364 SWDEV-480209 - Make internal callbacks non-blocking
Change-Id: Ic918d08f341abfd9a7c167d09f9c723cdc43157f
2025-01-10 02:16:11 -05:00
Saleel Kudchadker c9dd95bf6c SWDEV-504494 - Use system scope for D2H
- When using shader copy, make sure to use release scope for the AQL
  packet. This is a potential bug but is hidden as hipMemcpyAsync always
needs synchronization(which inserts a barrier with release scope). For
hipMemcpy we use a barrier packet to make sure its blocking. Eitherways
a barrier gets always used and hides in some ways a potential bug.

Change-Id: I57fb7f769c3179e76d712471c0905104c801d7ba
2025-01-10 00:34:08 -05:00
Evgenii Averin b62995ce1a SWDEV-505769 - Fix typo
Change-Id: I2d3f65ed68157718c4439a9da7d2dcdfcbb9f93d
2025-01-08 21:31:17 -05:00
Sourabh Betigeri f5b2516f5d SWDEV-505971 - Fix size mismatch of count type to uint32_t
Change-Id: Ie526f828f816e6681ef1735d5edb2db895dace57
2025-01-08 12:47:36 -05:00
Saleel Kudchadker 39801b5750 SWDEV-506251 - Disable blit copy thresold for OpenCL
Change-Id: Id0ca43b13d5792791a42da263f6aa4496382cea6
2025-01-08 02:46:01 +00:00
Saleel Kudchadker b63005d550 SWDEV-504494 - Flush to systemscope when copying non-coherent mem
- When we use blit(compute) copies, two subsequent copies may read for
  the same source buffer, the buffer may get modified by the host in
between and if the src buffer was allocated with non-coherent flag, the
device may simply use stale value from previous cacheline fetch. This is
a corner case.

Change-Id: I2ce261c6f6fa4e5bb608f116548e5cc711ae6f3c
2025-01-07 12:49:22 -05:00
Jatin Jaikishan Chaudhary 446ed661a0 Revert "SWDEV-505971 - change setArgument arg from uint32_t to uint64_t"
This reverts commit a6f2a2c2af.

Reason for revert: There needs to be memcpy size change

Change-Id: If4f51769731e54743ac705b19b4f81b2d5925d5a
2025-01-06 18:03:23 -05:00
Jatin Chaudhary a6f2a2c2af SWDEV-505971 - change setArgument arg from uint32_t to uint64_t
We are passing this arg as an address, and memcpy complains about
overreading (8 bytes instead of 4).

Change-Id: Ica9207f6c5f6056a4bfc968280c76e779ded13ae
2025-01-06 08:16:59 -05:00
Pengda Xie 8155943c5f SWDEV-505833 - Provide functionality to avoid L2 flush for CPX mode for dispatch packets
- Added DEBUG_CLR_SKIP_RELEASE_SCOPE flag to force release scope to
   SCOPE_NONE in AQL packet header

Change-Id: Ife02cddb9d5cd4749103ce585d3d5fe9024c6868
2025-01-03 17:28:21 -05:00
Amit Pandey 11cd37ce0b SWDEV-490256 - Fix uri_decode logic to handle Memory URI.
Uri decoder logic currently silently ignores processing of memory uri.
This patch enables the existing logic to handle the processing of offset
and size related to loaded code-object having memory URI.

Change-Id: If03579cefb11d91f667410464dc89404df9270a3
2024-12-25 11:07:16 -05:00
taosang2 d82d6a78cf SWDEV-479958 - Support different address mode
Support different address modes in X, Y, Z directions

Change-Id: If1db5a8af33c92dd14b48968c3e8eceb97daea6c
2024-12-23 16:39:54 -05:00
Saleel Kudchadker fa63919a63 SWDEV-504340 - Move cast of cl_mem inside the condition
Change-Id: I9c91f5d945a8d8bd2b2f55e3d11ede66afe4eef7
2024-12-17 12:58:12 -05:00
Pengda Xie 078fe7e5de SWDEV-503764 - Add wptr and rptr to ClPrint for dispatch barrier methods
- added wptr and rptr to ClPrint in dispatchBarrierPacket and dispatchBarrierValuePacket

Change-Id: I8a62289deb23c9f657a9b0ac6138bb55eafecba2
2024-12-16 16:45:30 -05:00
Ioannis Assiouras a808c4b23a SWDEV-489255 - Update stack size limit in rocvirtual
Change-Id: I2aac9d211f64b3d6c121d8b010d215dcbdeac3aa
2024-12-16 09:30:39 -05:00
Saleel Kudchadker 93f1e8ff60 SWDEV-301667 - Clear dispatch indicator signal flag
Change-Id: I9028df0bb73289791d169e7f064a1d0f615236a5
2024-12-12 21:20:05 -05:00
Sourabh Betigeri 03dbcd8ca7 SWDEV-440866 - [hip-roclr] Adds support to batch memory operations APIs
Change-Id: I5ac63a6626af8c2b4ac382c52dfe1aaf0b3716b8
2024-12-12 19:29:24 -05:00
Tao Sang 3ad8f1b811 SWDEV-496667 - Support gfx9-4-generic target
Support gfx9-4-generic target to cover mi3XX.
Support features sramecc and xnack in generic target.
Improve some code formats.
Add more log on compiler.

Change-Id: I6b3c6af55c60cffd43ce6f17b75998f751b75713
2024-12-12 14:43:39 -05:00
Michael Xie cfcc743824 SWDEV-499997 - Unify ManagedBuffer and KernelArg buffer implementation
Change-Id: I95421c87904dd62d7ee214539a57c7bda1097ff4
2024-12-12 12:56:23 -05:00
Saleel Kudchadker 23c21d5181 SWDEV-503761 - Reintroduce save-temps path for OpenCL
Change-Id: I5e111047242aed7d982b7a25c11ab52293af639d
2024-12-11 13:01:29 -05:00
German Andryeyev 14f58fc74d SWDEV-501757 - Clean-up signal creation
Use hsa_amd_signal_create() if settings.system_scope_signal_ is true.

Change-Id: I6d440155dfbcd5bf03658583a93827cb1c56537c
2024-12-11 09:57:50 -05:00
Gerardo Hernandez 03e4057fce SWDEV-496392 - Remove references to ASIC Polaris22 in pal::Settings and pal::Device (it is being retired)
Change-Id: I6318abf3e46ed250d087a3d2266d2ae3d4c8c000
2024-12-10 06:01:32 -05:00
German Andryeyev f4b9d3b7bd SWDEV-501757 - Use signals without interrupts
In active wait mode use signals without interrupts by default and switch
to the interrupts only if a callback is required.

Change-Id: Ibcde8f7d44c70f8fb8fa5e0a7fdd8b08a2982a8e
2024-12-09 15:16:15 -05:00
Ajay 7d763fb803 SWDEV-498474 - APU: when total allocated is greater than 75% of invisible
Only when memory type is Local and the invisible memory is +ve
Should also fix SWDEV-490991

Change-Id: I78a4925a234ba90c63909bde5b7dc217568b4de3
2024-12-09 12:06:57 -05:00
Saleel Kudchadker 7863eb92dc SWDEV-497145 - Use rocr copyOnEngine API for staged copies
- Refactor blit code and clean ASAN instrumentation
- Use unified function for rocr copy
- Enable shader copy path for unpinned writeBuffer/readBuffer paths
- Set GPU_FORCE_BLIT_COPY_SIZE=16 which means we will use BLIT copy for
  pinned copies or unpinned H2D/D2H copies < 16KB

Change-Id: I42045cca79234b340dbf53dafb93044199736ae4
2024-12-04 13:38:13 -05:00
Jimbo Xie 6c755a4116 SWDEV-485672 - LOG_INFO corrected to LOG_ERROR for errors
Change-Id: I8ab5f2117dfd7725bd4ed8b178e370096aa31018
2024-12-04 01:18:01 -05:00
Sourabh Betigeri 2ca644cf22 Revert "SWDEV-440866 - [hip-roclr] Adds support to batch memory operations APIs"
This reverts commit bd5d8e9baf.

Reason for revert: hipInfo fails on windows. Updating llvm amd-mainline-closed

Change-Id: I57e1fa1945188b0bc0a799c4f3d540f2b7713003
2024-12-02 16:46:12 -05:00
Aidan Belton-Schure f0063ba8da SWDEV-485827 release hostcall listener memory regardless of thread status
The early return if the thread is not alive causes memory leaks.
Neither doorbell_ or urilocator are released if the thread is not alive.

This change alters the logic so regardless of the thread status the
HostcallListener releases its memory.

Change-Id: Ie912360ec0e2ee257de9937b1a8d7375e6aebd83
2024-12-02 04:42:56 -05:00
Sourabh Betigeri bd5d8e9baf SWDEV-440866 - [hip-roclr] Adds support to batch memory operations APIs
Change-Id: I449ffca44bbb04d13348d112e896d603c70fd485
2024-11-30 17:54:32 -05:00
taosang2 f1f4f40c5b SWDEV-447973 - Support generic targets
Change-Id: I32db83843e45e0f013591493aafd7a532c881e16
2024-11-29 10:12:10 -05:00
Anusha GodavarthySurya 06e6561eb5 SWDEV-489084 - Avoid using queue colliding with the graph launch stream
Change-Id: I3ecaf8836c8e0883441275139041c702aba0937e
2024-11-29 08:15:58 -05:00
Aidan Belton-Schure f42a87dc2f SWDEV-485827 release initial_heap_buffer_
This PR adds the initialization and release of initial_heap_buffer_
to prevent memory leaks.

Change-Id: I4ab8721b439a1a3a6f6e53d63d870e572f7c984a
2024-11-28 10:31:26 -05:00
Anusha GodavarthySurya 9820480cbd SWDEV-491643 - AQL packets are captured for kernels disable sdma profiling
hsa_amd_profiling_async_copy_enable is taking 45us for the first call. Disable sdma profiling for enqueuing captured kernel packets and for accumulate command.
Change-Id: I80b51a58c46bccc9c1025e9331515f57c97b5a2a
2024-11-26 08:37:31 -05:00
Jaydeep Patel 3f3f3d0f1c SWDEV-498816 - Detached thread might exit and pthread_t is invalid access to check if it is valid or not.
Hence, It is not required to check it if thread is already finished processing packets.

Change-Id: If1b43a169a06203f3e1ab0529cf592879496d7c4
2024-11-24 01:38:47 -05:00
Ioannis Assiouras 2cc9f59774 SWDEV-494409 - Fixed segfault caused by aligned_free called on unaligned memory
Change-Id: I8ddea5c309b568db25c92789bf71be341d19c3ba
2024-11-22 03:08:04 +00:00
Saleel Kudchadker 2273a1dbdc SWDEV-497886 - Fix unaligned size copy for kernel args
Change-Id: If6675b98178aeb35f376d6994555cbf941b048c3
2024-11-21 14:30:04 -05:00
German Andryeyev e2eeb20c00 SWDEV-494231 - Revert TS optimization
Runtime may use checkGpuTime() for the wait and not just for the GPU time queries. Hence, the call can't be skipped if profiling isn't enabled.
More changes are required for this optimization.

Change-Id: I79e8918312e755d75f0d26685f2fdc604a8ffb18
2024-11-19 10:17:38 -05:00
Saleel Kudchadker e4d29e228d SWDEV-495987 - Use shared mutex for MemObj maps
- Remove binning logic, although useful it doesnt work in current
  scenario as there is no upper limit on the size of allocation. If an
app or framework uses entire VRAM and then creates suballocs, binning
would result in failure.

Change-Id: Icc27c13e433bb4a1f03e82028d8718488b43bfa5
2024-11-19 04:28:20 -05:00
Saleel Kudchadker f1e98ab6e4 SWDEV-483586 - Do not take pinned path for read/write
- When GPU_FORCE_BLIT_COPY_SIZE is set do not take pinned path

Change-Id: Iaa065db63cc8fda61f82e6c9701e9fdaec5c54cb
2024-11-01 12:55:15 -04:00
Satyanvesh Dittakavi a26dc29eb9 SWDEV-491967 - Add the right VGPRs per SIMD and VGPR Granularity for gfx12
- Default values are being assigned causing occupancy calculation to go
wrong without the right values defined for gfx12 ASICs
- Also added the these values for gfx1105

Change-Id: I611cc3a8ed8c57f2def637310ce1c3a48c16a574
2024-11-01 12:47:23 -04:00
Konstantin Zhuravlyov 3387f48b56 SWDEV-428601 - Don't enforce 1 isa per device in rocm backend
- Device can have multiple isas as per HSA spec
  - First isa is most specific one, so this change is sort of a NOP

Change-Id: Ib332af21745f2e6a7c25db8986bf7717501059bc
2024-11-01 11:01:02 -04:00
Jaydeep Patel 4aa52155ee SWDEV-491149 - OCL does not need to update scratch as it can't update stack size using API unlike hipDeviceSetLimit.
for HIP, Update should be only if compiler notifies use of stack size.

Change-Id: Ic781bcac6fcf586da39ec4aafd4809da3652ede3
2024-11-01 01:05:07 -04:00
Alex Xie f8c56f6bac SWDEV-489468 - make resource cache bigger for APU
Change-Id: I065c712acd06c273a0b194fe792ec4f876fa9c46
2024-10-31 09:55:01 -04:00
Tao Sang 82dff9a67d SWDEV-492563 - Fix Ocl issues
1. Fix LDSSize type to be uint32_t.
2. Prevent clWaitForEvents running on complete events whose
   HostQueue have been destructed.

Change-Id: I829e915f56b37db2ba76bb876c9656166534f154
2024-10-30 19:15:59 -04:00
Saleel Kudchadker e23ff0520b SWDEV-491375 - Improve MemObjMap perf
- Create bins each with its own map and lock. This would help cases
where the hash of a VA is differnet than ther one which falls in
different bin, and there is no lock contention
- Use STL shared mutexes, that way we can unique_lock for map updates
vs simple reads which can use shared_lock

Change-Id: I118818be65c6373700f5e511045babb6a398938a
2024-10-30 05:37:33 +00:00
German Andryeyev 403f624bf8 SWDEV-486602 - Add tracking of HSA handlers
Add an atomic counter to track the outstanding HSA handlers.
Wait on CPU for the callbacks if the number exceeds the value
in DEBUG_HIP_BLOCK_SYNC env variable.

Change-Id: I95dc8c4bf0258c7e59411b7504220709ed6898c5
2024-10-25 15:20:50 -04:00
German Andryeyev dceb320ba7 SWDEV-440746 - Fix a typo with GPU_PINNED_XFER_SIZE
Change-Id: I8fdbfb4e1c6b1274206c28a529eee9ebeaaa26fb
2024-10-24 18:33:14 -04:00
Anusha GodavarthySurya b498103f9b SWDEV-485904 - propagate hsa_amd_vmem_address_free error to hip API
Unit_hipMemSetAccess_GrowVMM test fails with
HSA_STATUS_ERROR_RESOURCE_FREE silently

Change-Id: I7a78410e432de4a2e877062782abf8761645f392
2024-10-21 10:12:32 -04:00
German Andryeyev 364dfb0ed1 SWDEV-486602 - Optimize HSA callback performance
- Don't generate callbacks for HIP events
- Don't process profiling info in the callback for HIP events
- Wait for CPU status update of the submitted commands
every 50 calls. That will allow to drain the commands and
destroy HSA signals.

Change-Id: Ib601a350e7e7c2b6c6209a172385389baccf73a9
2024-10-11 14:50:25 -04:00