On error mmap returns value MAP_FAILED, which is (void *)-1, not NULL
pointer.
Change-Id: I81b187266c943fa0aa4fab21b529d4c2989b12ad
Signed-off-by: Philip Yang <Philip.Yang@amd.com>
[ROCm/ROCR-Runtime commit: 590fd531c0]
Prior to launch some ASICs may re-use PCI DIDs from older generations.
This can cause issues during topology initialization as hsa_gfxip_table
lookups will override sysfs-provided gfx versions, causing incorrect
gfxip selection. Since no new entries will be added to hsa_gfxip_table,
limit its search only to pre-GFX11 ASICs.
Signed-off-by: Graham Sider <Graham.Sider@amd.com>
Change-Id: I53eaefac5db2650a36a6ce9f21daf750f50cfd26
[ROCm/ROCR-Runtime commit: 79279e860f]
Fix Binary Search sample code as kernel symbol name has a .kd
extension.
Change-Id: Id21d2e432faa40bcd5cf343345502e823678fd0f
[ROCm/ROCR-Runtime commit: d9935e6fba]
IterateIsa had some leftover instructions from when the shader was
getting updated for KFDCWSRTest.BasicTest.
Signed-off-by: Graham Sider <Graham.Sider@amd.com>
Change-Id: I41ae7b7948cbe2aff8bf61b170b9a7d498b836a3
[ROCm/ROCR-Runtime commit: 82a41c7e4d]
fork process copy-on-write MMU nitifier on CWSR range will evict user
queues, and then update GPU mapping and resume queues, use MADV_DONTFORK
to avoid COW MMU notifier callback on CWSR SVM range.
Use mmap to alloc SVM range for CWSR because posix_memalign don't alloc
new range in child process, this fails to register svm range as range is
invalid address in forked child process.
Change-Id: Ibaea56a691dd6f577ed2e1f2d43f4a3500b8316f
Signed-off-by: Philip Yang <Philip.Yang@amd.com>
[ROCm/ROCR-Runtime commit: 093cf898fb]
mmap alloc larger address range with align padding page plus guard
pages, then unmap the padding and guard pages at beginning and end
of the range, return aligned address range.
Change-Id: Iaf3c711a079c744289efbafee9b5e63aaf724765
Signed-off-by: Philip Yang <Philip.Yang@amd.com>
[ROCm/ROCR-Runtime commit: b7710a1dda]
GFX1036(ISA version) is not included in the previous range.
This patch can really include all gfx10 series ASICs.
Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Change-Id: I0e28dbfc031c216166b306b9fb39f644f75a330f
[ROCm/ROCR-Runtime commit: 06a90612e9]
Avoiding the segfault, runtime debugger enable is not supported
if the firmware of gpu doesn't support debug exceptions.
Signed-off-by: jie1zhan <jesse.zhang@amd.com>
Change-Id: Ifad57a6e78cb1c92b1f8927355ece8c64e89c51b
[ROCm/ROCR-Runtime commit: d98c729ff9]
Remove potential double free condition when free_queue() is called
after hsaKmtDestroyQueue() if mapping doorbell fails during queue
creation.
Signed-off-by: Mukul Joshi <mukul.joshi@amd.com>
Change-Id: If2aa19c455b30d2940b232dbafb9cc1eaad721a5
[ROCm/ROCR-Runtime commit: 57a1c6f3ff]
When running kfdtest test case, because the filter node of the new chip is
missing in libhsakmt, the test case is not supported, so a new test node
is added in order to spporting kfdtest case.
Signed-off-by: shikaguo <shikai.guo@amd.com>
Change-Id: I0cd9ffd7d4387129cfb0f8de6b669f431949ab49
[ROCm/ROCR-Runtime commit: 4951495fca]
Disable automatic dependency detection when generating rocrtst RPMs.
This was adding unnecessary dependency on libhwloc, which is now
provided with the rocrtst package.
This matches behavior for DEB packages where there is no dependency
list for rocrtst.
Change-Id: If4a93f5b4c039b2f45e9445f60f65eefe84e32eb
[ROCm/ROCR-Runtime commit: e2388f242a]
Queue ctx_save_restore memory is allocated with size
ctx_save_restore_size + debug_memory_size, use the same size
in free_queue to free ctx_save_restore memory.
Change-Id: I4902ff15fb82ddea64b8342b89776a1bf5c38d13
Signed-off-by: Philip Yang <Philip.Yang@amd.com>
[ROCm/ROCR-Runtime commit: 3dbf5feffe]
Avoiding segfault when an invalid SharedMemoryHandle is passed in
when calling fmm_register_shared_memory.
Change-Id: I0e0bbed01487fc10afcbb170eb9330e70b209d14
Signed-off-by: David Yat Sin <David.YatSin@amd.com>
[ROCm/ROCR-Runtime commit: 1c385fb257]
close the file at the end of every test, instead of the whole test
Change-Id: Ia510990dad8d0bd82625bbd9b2958181e8f1dd25
[ROCm/ROCR-Runtime commit: 8941e7135c]
Now that HsaNodeProperties is passed in to
topology_get_node_props_from_drm, check that pointer instead of the
pointer for MarketingName (which throws a compiler warning)
Signed-off-by: kent.russell@amd.com <kent.russell@amd.com>
Change-Id: If76b24e1bab5a62e514ab440b6316c7b7cd264c1
[ROCm/ROCR-Runtime commit: ea4d4917c1]
Add agent info query HSA_AMD_AGENT_INFO_ASIC_FAMILY_ID.
Then we can remove the codes to parse family id.
Signed-off-by: Lang Yu <Lang.Yu@amd.com>
Change-Id: I3ac4746d3015e89b32322ebc0f8a3084f98677a4
[ROCm/ROCR-Runtime commit: d0e7c617df]
Query family id info from drm render node, then
ROCr can query this info directly from Thunk
instead of parsing the info by itself.
Signed-off-by: Lang Yu <Lang.Yu@amd.com>
Change-Id: I030bd27ab2379fbf87f3d787302c3b8613456278
[ROCm/ROCR-Runtime commit: 66e9e97e0d]
Required due to LLVM retirement of llvm::apply_tuple, instead using
std::apply which was introduced in C++17.
Signed-off-by: Graham Sider <Graham.Sider@amd.com>
Change-Id: I6646ebcca7d71d3e1bcf340ccfa3db2c15a3110a
[ROCm/ROCR-Runtime commit: 4267c4b524]
Failure with new CWSR tests reported for GFX10, for now add to blacklist.
Signed-off-by: Graham Sider <Graham.Sider@amd.com>
Change-Id: I5b2bd9ec61c64ad66e1c34ba2c192bece808f56f
[ROCm/ROCR-Runtime commit: 0055ef46c4]
This reverts commit 005a0b6979.
The change from using RUNPATH to RPATH was not approved formally.
Reverting this patch until this gets approved.
Change-Id: Ibc1a8f9d5dfa6694adacccfd9e3b0d053660e848
[ROCm/ROCR-Runtime commit: 0647960019]
This patch restructures the CWSR basic test and allows for
creating parameterized CWSR tests. This patch introduces four
parameterizations. These tests behave as follows:
This test dispatches the IterateIsa shader, which continuously
increments a vgpr for (num_witems / WAVE_SIZE) waves. While this shader
is running, dequeue/requeue requests are sent in a loop to trigger
CWSRs.
This test defines a CWSR threshold. Once the number of CWSRs triggered
reaches the threshold, a known-value is filled into the inputBuf to
signal the shader to exit.
4 parameterized tests are defined:
KFDCWSRTest.BasicTest/0
KFDCWSRTest.BasicTest/1
KFDCWSRTest.BasicTest/2
KFDCWSRTest.BasicTest/3
0: 1 work-item, CWSR threshold of 10
1: 256 work-items, CWSR threshold of 50
2: 512 work-items, CWSR threshold of 100
3: 1024 work-items, CWSR threshold of 1000
Tuple Format: (num_witems, cwsr_thresh)
num_witems: Defines the number of work-items.
cwsr_thresh: Defines the number of CWSRs to trigger.
Signed-off-by: Graham Sider <Graham.Sider@amd.com>
Change-Id: I639eb7bd75b14ee70e190b4bd19dcf34096fc7bf
[ROCm/ROCR-Runtime commit: 0dbac97b75]
The debugger can now request snapshot copies with entry size and
set/clear watchpoints by device.
v3: drop min version check to v10.0
v2: check runtime allowance from v10.3 to 13.x
Signed-off-by: Jonathan Kim <jonathan.kim@amd.com>
Change-Id: I9befefb596201a11591de218db29a9317b41e69b
[ROCm/ROCR-Runtime commit: c1d8ac8437]
The allocation logic of the SPI does not take into account compute
user thread management settings for masking CUs with the exception of
skipping fully disabled SEs. This means that occupancy limited
dispatches such as cooperative launch may over allocate onto hardware
resources that are not immediately available, resulting in a potential
barrier logic hang as occupying work groups are waiting on enqueued
work groups to reach the barrier.
Further work will have to be done to get the per-SA CU enablement count
from the KFD in order to correctly clip the cooperative CU limit based
on the CU mask, which will require breaking the current ABI.
For now, report that cooperative launch is not supported while a CU
mask has been applied to prevent potential shader hangs.
Change-Id: I8be4bb47d65ceb62d805f36ef6ef3996d756021f
[ROCm/ROCR-Runtime commit: 2b75a73ce7]
Change default behavior for library search to use RPATH instead of
RUNPATH.
Change-Id: I328766006d02c2a8c76a3b1e0780ae5ca678ed86
[ROCm/ROCR-Runtime commit: c904cc5856]
New environment variable HSA_OVERRIDE_CPU_AFFINITY_DEBUG to
enable/disable overriding CPU affinity.
Default value is enabled(1).
This is a temporary variable and may be removed in the future.
Change-Id: Id6a7c611730471ddc276ca333fde1e57046bf32a
[ROCm/ROCR-Runtime commit: df3fe8c2fb]
Add support to expose executable bit.
Change-Id: I054f5c3173822c369dd9908eec5c449459600ce1
Signed-off-by: David Yat Sin <David.YatSin@amd.com>
[ROCm/ROCR-Runtime commit: a7db31c5d1]
Fix for regression in commit:
da0ca94219
When running rocrtstNeg.Queue_Validation_InvalidWorkGroupSize, each
time rocrtst::LoadKernelFromObjFile is called, a new CodeObject is
created and not deleted until end of the whole test. Each CodeObject
keeps an open file descriptor of the kernel file and this can exceed
maximum allowed open files on some systems. Deleting the CodeObjects
after each iteration in the test.
Change-Id: I388e56f95f7b671ecc29d5ecb4eb8ac2d0ddc412
[ROCm/ROCR-Runtime commit: 50b636d1d8]
Add new test for GPU agents memory available
Change-Id: Ib07e2003a21659b99732b535cd004081635d6aa1
Signed-off-by: David Yat Sin <david.yatsin@amd.com>
[ROCm/ROCR-Runtime commit: ec759c7995]
Add max enum value to force size of enum and avoid clang compile
warnings.
Change-Id: I9cdf529517cc605a5039c3a924fd718ece16029d
[ROCm/ROCR-Runtime commit: 86e4cb1ddd]
For gfx11 the image type table has some different values compared to
previous asic families (e.g TYPE_SRGB). Creating a new LUT class to
use these new values.
Change-Id: Ifdfc6cd29bfd5f4ec2643c848fcb9986eb874f9e
[ROCm/ROCR-Runtime commit: 117495fe88]
Update image table enums and format tables for gfx11.
Remove some entries that are not needed.
Change-Id: I060c1e285925a6d428ef1c5498f5dd89f5d79d97
[ROCm/ROCR-Runtime commit: f971834d7a]
This library was taken from public MESA library:
https://gitlab.freedesktop.org/mesa/mesa/-/tree/main/src/amd/addrlib
with top commit:
2866ae32da0348caf71ad2d11c353321df626ff4
Removing macros.h as it is no longer used by addrlib
Change-Id: I0fdabfe48b74c259b4d29d81beae89604bbc141a
[ROCm/ROCR-Runtime commit: a742b7e830]
Non-paged allocation for queue memory necessary for binding wptr to
GART. Required to support usermode queue oversubscription with MES for
GFX11.
Adds AllocateNonPaged entry to MemoryRegion::AllocateEnum for clarity;
aliases AllocateIPC.
Signed-off-by: Graham Sider <Graham.Sider@amd.com>
Change-Id: I1a97a1820da26cf2433d9c237b2e6d2b0b8628b4
[ROCm/ROCR-Runtime commit: 061aa04147]
Adding new ImageManager class for GFX11 GPUs
ImageManagerGfx11 functions copied from ImageManagerNv.
Register descriptions in resource_gfx11.h updated for gfx11.
Signed-off-by: David Yat Sin <david.yatsin@amd.com>
Change-Id: I48b39f6a633aef14aa829f7240a43fe0feb1c290
[ROCm/ROCR-Runtime commit: 907e05c1b3]
Philip Yang
Graham Sider
Daniel Phillips
David Yat Sin
Aaron Liu
jie1zhan
Mukul Joshi
Shikai Guo
kent.russell@amd.com
Lang Yu
Jonathan Kim
Yifan Zhang
Jay Cornwall