47322942b3
aqlprofile block list, explicit numbers assigned, IA removed
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Change-Id: I9f9358f8e03e13eb81845de2e33dd5f3da27811a
2017-08-03 11:39:21 -04:00
c66f68041c
aql-profile api: reducing blocks list to compute only and new gfx9 blocks
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Change-Id: Ib506b82ea407afec4f5d4bcad755d4d57b92e34b
2017-08-02 12:21:24 -04:00
ab2248132a
Clearer/more concise variable names
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Change-Id: Ib92211977066b728f19b2a7fe40639160a8262b3
2017-08-01 10:38:26 -05:00
cf24f7bb78
Added max. single mem. allocation test.
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Change-Id: Ie81c6af0502fde56225b1e197801cf04b474feb2
2017-07-31 12:04:55 -05:00
bddc89e703
Reorganize tests
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Change-Id: I45f92d61070b325bcb57bd72e4a68e7d6495463c
2017-07-28 11:32:20 -04:00
9ee0108e58
Fix compilation issue reported with GLIBC 2.12 (RHEL 6.9)
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Change-Id: I770b72ba1d61475a76aa72d0c52ebfb380db6019
2017-07-28 11:11:01 -04:00
a055531eb4
Update tests to use rocm-smi
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Change-Id: Ia4692019460f4ba42a12ecba1f9e59576561c73e
2017-07-28 08:34:27 -04:00
8424fd6f23
Add rocm-smi c++ utility classes
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Change-Id: I4362151abf84f89942bf2895b45fca498a28dfc9
2017-07-25 00:42:34 -04:00
a12c5628ea
Added dispatch time, async copy and test template rocrtst tests
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Change-Id: I57a844ee65c36bd61616ee6d60d358303f51db56
2017-07-17 10:30:26 -05:00
08d5efe29d
moving hsa-amd-aqlprofile to ssh://gerritgit/hsa/ec/aqlprofile
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Change-Id: Ic42752ca41f877db02aa5a5d8d617cd67cce8956
2017-07-14 14:59:42 -05:00
ab67b8511b
hsa_ven_amd_aqlprofile.h: include <hsa.h> fix
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Change-Id: Idfd2fdde112d502d4b4a3365512ec601f7e56a5b
2017-07-12 15:43:58 -05:00
a0a3587345
Remove use of anonymous member in C builds.
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Tools/CodeXL will retain older versions of structs if them need them.
Change-Id: I568d7b445778dd575ef71000b4b839300572288e
2017-07-12 16:40:00 -04:00
bc0bd00746
Fix queue interception in tools.
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1. Correct amd::AqlQueue::ExecutePM4 to support interception.
2. Minor fixes to AqlPacket and SoftCP.
3. Minimal change to disable interception of runtime internal queues.
Change-Id: I103fece2ebf9a188d27f01e61221c737405d7253
2017-07-12 16:39:43 -04:00
29b5b5c029
Correct handling of slow clocks under linux.
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Change-Id: I9a1b08d5457caa6739220603bbd37b00febc64d7
2017-07-12 12:49:49 -04:00
3e50adc7ce
Properly order signal copy agent tagging with copy operation.
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Change-Id: Ic428c958551279fbea1b2449afba930b82804ede
2017-07-11 13:10:00 -04:00
c9f0427cb0
Decrement hsa_init ref counter when init fails.
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Change-Id: If9376344d4b559e601932d070731132c8450104e
2017-07-07 21:21:03 -05:00
4174f07fd1
hsa-runtime integration
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Change-Id: I48968966ffe164218ebff88d0e3a1268e96bf1dd
2017-07-05 10:55:30 -04:00
c533229bc1
Block list extending
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Change-Id: Id17efde25fce287296e80f2b37c77b15aa59b561
2017-06-23 16:37:02 -04:00
8618bf7e2c
minor fixes, debug output, comments, using env vars, dead code
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Change-Id: I08ad73b561709c1818d78a9191c96d6ad141a609
2017-06-22 18:04:26 -04:00
08e0bca567
Support Perf Cntrs (PMC) and Thread Trace (SQTT) over AQL queues
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Change-Id: I716b722895d90b46914c31377e791ad602acecc1
2017-06-15 12:58:31 -04:00
5b4df54b10
Revert "Implement memory fault analysis through context save area"
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This reverts commit 75c9506f9d
2017-06-14 14:21:53 -04:00
35b376e2ee
GFX8 API
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Change-Id: I9d0c430e4199f043226c8897f3320a7973cbdeda
2017-06-14 12:24:28 -04:00
75c9506f9d
Implement memory fault analysis through context save area
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When a fatal memory fault occurs the scheduler context-saves all queues
in the process and notifies the runtime through the memory event. The
saved state contains all GPR/LDS data at the moment of the fault.
Retrieve this state and present it to the user if HSA_DEBUG_FAULT is set
to "analyze" and the wavefront caused the fault. If amdgcn-capable objdump
is in the PATH invoke this to disassemble code around the PC.
Queue lifetime is now managed by the runtime to allow querying the
context save state for all active queues.
Change-Id: I6fee662fad1c4f9aa125bf5c53d7d0ea1ab32f95
2017-06-13 23:12:28 -04:00
25035b8d09
Adding HSA extension AMD AQL profile library, see Readme.txt
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Change-Id: Icbc1e0fb0185642eabbab411a2138ea030d22be8
2017-06-13 16:18:06 -04:00
da831502ab
Adding GFXIP and kernel code object
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Change-Id: Ieb2dfea8d9e909efac583f541730d77b7d0c9679
2017-06-13 14:58:29 -05:00
d98e99949a
Update hsa_isa_t entries
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- Add 7.0.2 (consumer hawaii)
- Add 9.0.1 (gfx900 with xnack)
- Add 9.0.2
- Add 9.0.3
Change-Id: I6a07797027c4eaf47038837c5ae51e05b2aba0e4
2017-06-12 14:34:11 -04:00
a0957bc679
The fallback path covers not just ARM64, need this for Power as well.
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Change-Id: I7bbf76f77bd3ac47a0a0987c1e880e23834588e2
2017-06-07 14:45:29 -05:00
cd35fb280a
Patch target name in code object for future-proof
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Change-Id: I6f12b5e5791bd1745ec3ab76d382fad50282e733
2017-06-05 19:08:27 -04:00
801bf4398c
Added async. mem. copy sample.
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Change-Id: I4fbb009181056c5f293d17720214b70588d44bdf
2017-06-05 17:20:51 -04:00
5db53ceda1
Enable SDMA on gfx9, disable on gfx8
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gfx9 has passed qualification. gfx8 stability is under investigation.
Change-Id: Ia72211d47756399ecdfceafeb67c2ab34ebda834
2017-06-02 15:14:14 -05:00
1170244ae2
Added IPC sample
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Change-Id: I980c430d6e091eb1abbc0df89ca74c96348bcd37
2017-05-31 09:47:16 -04:00
adf201d6a5
Added rocrinfo sample
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Corrected a few formatting issues with binary_search.cpp
Change-Id: I9dcc0a231c6b8c424b44f4ab17032ff51b81a1ba
2017-05-31 09:46:06 -04:00
c3e2a88ade
Add preferred agent info to pointer info struct.
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Lookup blit agent via pointer info in memory_fill.
Change-Id: I02feaf68bb9726858e8cb0ede6bc5f2b3707f5af
2017-05-31 05:16:05 -04:00
77e5b30c41
remove finalizer usage from image ext
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Change-Id: I282f02cedce790bf42f07c588fd50e346b9ba665
2017-05-29 20:44:52 -04:00
e38ff18990
Unmap GPUs when allow_access removes them from system pools.
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Change-Id: Ib9eb88622fded43ebd9eddbf78ad6771a5b91e77
2017-05-17 20:58:05 -04:00
8161ebb915
Refactored performance test code
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Commented and flattened binary search sample.
Change-Id: Ib783292207c956d16003195924a3bcfbbde5039f
2017-05-11 14:45:45 -04:00
a777413400
Purge warning in amd_hsa_code.cpp
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Change-Id: Iaa5d7af183af5e8c069365a1f0410365b46d53d5
2017-05-08 19:39:49 -04:00
001d43ce56
Change rpm preinstall script to post install
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Change-Id: Iccc04902699bf0ba8b5269e1129b72cf69ef7f00
2017-05-07 14:02:54 -05:00
8aa19388a9
On GFX9+ amd_queue_t.scratch_backing_memory_location must store the queue's scratch backing store VA, not the offset.
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Also fix permission in couple files.
Change-Id: I4203f8e5a36406b20562d8943ea5c341847f039a
2017-04-18 22:37:56 -05:00
617b6fa987
Separate gfx700 and AI architectures
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Registers are different and it's cleaner to do as such
Change-Id: I36eee4c9c74deb43ca4666baa87894765a5f27b8
2017-04-07 00:14:22 -04:00
f0a1c7c4c6
Fix gfx9 trap handler to retrieve correct return address
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The trap protocol changed between gfx8 and gfx9. The return address
is in trap temporaries [0,1] on gfx9 rather than [4,5] on gfx8.
Unfortunately SP3 changes the meaning of the ttmp register aliases
in gfx9, further confusing the issue.
Clean up later when LLVM assembly build is introduced to the runtime.
Change-Id: I84ea9bf3736f060dd95d0361f9d5a0f9a3576178
2017-04-05 17:33:49 -05:00
8a5ff78be6
Remove comments, no functional change.
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Change-Id: I923c037803a847352c2c50d9d47460cb0f01f22c
2017-03-28 18:22:49 -05:00
7dfeee5074
Support async. queue errors and dynamic scratch without KFD events.
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Change-Id: I4e9e7a37aa7b9c96b28ce79f562760283e02b1e0
2017-03-28 19:18:18 -04:00
c4544906b9
Refactor signal_wait timing code and respect small timeouts.
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Optimized for Gromacs and SHOC.
Change-Id: Ib674710268b41003259711a0e42d3e770a82018d
2017-03-23 23:55:48 -05:00
ba3f1cb476
We should be using the "used" gcc attribute.
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Change-Id: I1589273740ae66e8d7d8186a88e2c411a2e0425c
See: https://gcc.gnu.org/onlinedocs/gcc/Common-Variable-Attributes.html#Common-Variable-Attributes
2017-03-20 11:57:39 -04:00
6c750f479d
Fix the comment to specify the right type of allocation required.
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Change-Id: I8bda8d64010d466d6ca5e779d2042cca3f494ecf
2017-03-20 11:56:54 -04:00
7c6cde1871
Disable SDMA only on gfx900 until it is validated.
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Change-Id: Ib960be3ca6d3fc4b664ba047243964b8c7a33f24
2017-03-20 11:55:22 -04:00
a08d760c70
[Loader] Fix memory allocations for code objects that
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are larger than swap space available
Change-Id: I321487f96fe0a18998301a9058430c19427e5a94
2017-03-11 00:57:25 -05:00
5f50e97d18
Support async error code 256, invalid vendor specific packet.
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Change-Id: I491f34def4c3d54403864fa42670f7847a6141cc
2017-03-10 16:20:27 -05:00
2824786b3b
Relax signal assertion.
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Informs, in debug mode only, that a signal wait violated the HSA
spec with regard to the consuming agents list. This list is used
for optimized signal type selection.
Change-Id: I5879f8f822d01af504ab913482b2532feb00be98
2017-03-10 16:05:34 -05:00
Evgeny
Chris Freehill
hthangir
Sean Keely
Ramesh Errabolu
Kenny Ho
Jay Cornwall
Konstantin Zhuravlyov
Qingchuan Shi
James Edwards
Christophe Paquot