Commit Graph

454 Commits

Author SHA1 Message Date
German Andryeyev 6f2e7c3199 SWDEV-313126 - Use data() method for the base array address
Reference for the first element can trigger an assert with
_GLIBCXX_ASSERTIONS build

Change-Id: I59c63c052831307edfe5dcc6384798a43e9596dd
2021-11-26 09:51:57 -05:00
Julia Jiang f5c9ad5b1d SWDEV-308644 - merge roc blit kernels
Change-Id: I378e511959fe17c03fa45066022e9670a4d181f0
2021-11-25 10:07:51 -05:00
kjayapra-amd 8307886644 SWDEV-310187 - Change flag to keep track of aligned sizes instead of expanded patterns.
Change-Id: I763feda8688bb1b7b11033a2a8cba0f69f07167d
2021-11-19 10:32:40 -05:00
Saleel Kudchadker b192beea52 SWDEV-299893 - Set preferred node affinity
Set affinity to the closest node of the current GPU. This reduces
the latency to fetch kernel args since device would query the CPU cache
of core which did the dispatch. This behavior is controlled with
AMD_CPU_AFFINITY env var(disabled by default)

Change-Id: I65afba62cb818ea25a311b88d1c0dd5c51330292
2021-11-19 04:42:42 -05:00
German Andryeyev 8e4101b4fd SWDEV-294669 - Avoid queue drain
Use slot wait logic for direct dispatch

Change-Id: I431ba1418eb4aa066b9881934f4055b3d338ce3a
2021-11-18 13:06:12 -05:00
pghafari e38a200bf7 SWDEV-297142 - HIP-Vulkan - linux interop buffer
Change-Id: I0278e56bba632024c214beb9e1758587ccba0927
2021-11-17 06:06:58 -05:00
German Andryeyev 9877fc9dbf SWDEV-305016 - Correct timeout logic
Timeout logic should be applied always even if the wait is active.

Change-Id: I2e5db7ac8a0f9a0355ad7b40e4227d76fb002aa0
2021-11-16 23:04:34 -05:00
Julia Jiang ef3d6f7b28 SWDEV-308644 - update blit kernel setup in rocm
Change-Id: Iaa9ff97b3ed7d379189c359696be932a83cf203c
2021-11-15 13:28:07 -05:00
kjayapra-amd 7e32d6d909 SWDEV-309657 - Align Virtual queue size to sizeof(uint64_t).
Change-Id: Ia55d7316693bd13938875ce53f7849d5eb658e8c
2021-11-12 10:35:36 -05:00
German Andryeyev bbb635bc32 SWDEV-305016 - Add a timeout wait into IsHwEventReady()
Just signal check will still submit the marker and then later
runtime will have a timeout, but the barrier packet is still
generated. Hence early timeout will allow to skip the marker.

Change-Id: Ieb7d89becbcff43a4f4c46715354ca65ab4a80b9
2021-11-02 11:37:23 -04:00
German Andryeyev 7e12cf6318 SWDEV-257789 - Initial change to skip kernel arg copy
The optimization is controlled with ROCR_SKIP_KERNEL_ARG_COPY.
This is initial check-in for experiments. Extra changes are
necessary for full support:
- handle graph capture with the original sysmem alloc
- avoid memobject references, otherwise there is a race condition with
reusage of the arg buffer
- Remove arg setup from hip

Change-Id: Ib0af710f93e79834711fa4049a7c66093711e68b
2021-10-28 20:35:35 -04:00
German Andryeyev 30bba18a06 SWDEV-303567 - reset kernel arg buffer to chunk 0
Change-Id: I2974e31af9700705554b0f274ede6f8b9a9d6e7b
2021-10-27 22:15:55 -04:00
German Andryeyev f78b3a8919 SWDEV-303567 - Add chunks for the pool of kernel arguments
The kernel arg pool will be divided into 8 chunks to avoid long stalls,
when the pool will be reused.

Change-Id: I228e6ca1c09e428c1775f1e5b685220a9a5d71af
2021-10-26 16:31:37 -04:00
Bing Ma 02f939a40d SWDEV-306602 - [SANITIZER_AMDGPU] Force copyBuffer to use ROCr functions when ASAN is ON
Change-Id: I04a4cdd5ab8c5543f2a0f08c139c45ac7aebe64a
2021-10-14 12:55:27 -04:00
kjayapra-amd 88ed58735d SWDEV-232903 - Move hipmemset Dword optimization to ROCclr.
Change-Id: I3eae61720cbc6364f1aaac4865bfd8b6ded08097
2021-10-13 11:32:15 -04:00
Jason Tang 55a0cf0b0c SWDEV-306697 - Fix OCLGlobalOffset segfaults
If we don't create the __amd_rocclr_gwsInit kernel, we still want
to create the rest of the image related blit kernels.

Change-Id: I8bc4645f9f9116eeecbb8b22e981ac4d520f3121
2021-10-12 15:13:28 -04:00
Sarbojit Sarkar c06c9f7b93 SWDEV-306302 - Fix for OCLCreateImage test failure
Change-Id: I781504bd1ff599ed75c5ea730be03b71f69761b2
2021-10-07 19:52:58 +00:00
jujiang 90b0e8430a SWDEV-306207 - clean up CL definition in ROCclr
Change-Id: I92e2c7c63ebddd119df390784e372ab2f42f3b0d
2021-10-07 11:45:43 -04:00
German Andryeyev 7fe696b6ef SWDEV-303567 - Increase the size of AQL queue
ROC_AQL_QUEUE_SIZE will control the size of AQL queue.
The current sefault value is 4096.

Change-Id: Icd2a4ee3ba554c06aa05b08defd922d2c63e43fd
2021-10-06 08:27:36 -04:00
kjayapra-amd 7413b7f79b SWDEV-294420 - Ignore Image blit kernels if image instructions are not supported.
Change-Id: I145172672b0b032aa722649b0c4ca9267e3e5c85
2021-10-05 18:12:44 -04:00
German Andryeyev d17108e8d0 SWDEV-303560 - Remove coarse grain setup by default
The original logic was left after initial testing when HMM
couldn't handle xnack properly

Change-Id: I0abf01805704171e931dfba8b6d95bfe87d5fab1
2021-10-05 17:20:59 -04:00
kjayapra-amd 3081f7ca53 SWDEV-295277 - Report max waves per cu from ROCr backend.
Change-Id: Ie170b26b53f1cc2da851034c96b21de38ce7b563
2021-10-05 12:38:44 -04:00
Tao Sang 10abe8ab37 SWDEV-305884 - Clear up codes
Fix a log typo error
Change-Id: I887ecbdcfe414c2119247228bdd1255b8308da1d
2021-10-04 18:11:32 -04:00
Sarbojit Sarkar 22a847f3ce SWDEV-301823 - Optimize hipMemset2D/3D
Change-Id: Ibe560149a263c2ac6b08e4eb1a1d331d2aeac78c
2021-09-27 14:10:06 -04:00
Sourabh cbb8d82bdb SWDEV-292525 - [vdi] Path to streamOps shaders
Implementation to use a blit kernel to perform
a hipStreamWait/write instead of an AQL packet.

Change-Id: I462671ed5cec37144dfe97ff66439249196117c1
2021-09-27 13:59:35 -04:00
Jason Tang f212fc91ca SWDEV-1 - More 'delete' clean up
info_.extensions_ and settings_ are deleted at amd::Device()::~Device().

Change-Id: I06f240a42e5c131dbd4e61a759f905bcdf84b45a
2021-09-21 11:17:24 -04:00
German Andryeyev f116959b54 SWDEV-302383 - Get active state from device
The queue can be destroyed at the time the app will request
the event status. Hence just get the active state from the device.

Change-Id: I887ecb0cfe414c2119247228b0d1255b8308da1e
2021-09-14 19:01:44 -04:00
German Andryeyev d8a86e4870 SWDEV-282419 - Use HSA_AMD_SVM_ATTRIB_AGENT_ACCESSIBLE for unset
When unsetting runtime should use HSA_AMD_SVM_ATTRIB_AGENT_ACCESSIBLE
for the agent and not HSA_AMD_SVM_ATTRIB_AGENT_ACCESSIBLE_IN_PLACE

Change-Id: I3814802d1fb3b72c54e7566defafafed6b0d5cee
2021-09-13 15:05:20 -04:00
German Andryeyev 65ddfcc6a8 SWDEV-294669 - Keep one more slot for HW processing
The original logic left only one slot for HW processing in the queue.
For some reason there is a race condition on CPU overwrite of the slot
before the current active. The workaround is to avoid the previous to
the current active slot for possible unfinished HW processing.

Change-Id: I565495a8feeaedffc9fc8a505edbee5ff5816975
2021-09-13 13:56:05 -04:00
Jason Tang 73967c3b17 SWDEV-1 - Some 'delete' clean up
Change-Id: I02564f0f0e349375bde1471e9f82df268703367b
2021-09-09 12:12:40 -04:00
Saleel Kudchadker 21ba34d0fe SWDEV-297448 - Add 64bit and 16bit write support
For the fillBuffer shader, if there are two 32bit writes to a MMIO
register, it can get dropped. It has to be a single 64bit write.
Add optimization to fillBuffer to write 64bit and 16bit writes.

Change-Id: I3aa78e027898f8ae01e9c8f09004615673720c2b
2021-09-08 12:30:04 -04:00
Sarbojit Sarkar 42d33029dc SWDEV-300655 - Added thread ID to hip trace
Change-Id: I9234d4ec93e7687cd0a5d1bd930bd4f80936311b
2021-09-06 00:22:42 -04:00
Saleel Kudchadker e29b9c00ee SWDEV-301667 - Kern arg placement
Add a env var ROC_USE_FGS_KERNARG to toggle kernel arg placement
By default its in Fine Grain Kernel arg segment for supported asics.

Change-Id: I3d57ed69a1a4db2b392b0438ead499f3ddca4716
2021-09-02 12:36:49 -04:00
jujiang f63115cec6 SWDEV-286322 - clean up trailing white space
Change-Id: I01f3a559cbd1835aa2fdad7abe2bd685d90fc6a8
2021-09-01 11:45:47 -04:00
Jason Tang 7f83bcdb45 SWDEV-1 - Disable OpenCL support for gfx8 in ROCm path
Change-Id: Ie1e0c0d6273edf6b734909447c2a08252cba305b
2021-08-31 12:48:47 -04:00
Satyanvesh Dittakavi 169cc857fd SWDEV-298985 - hipMemPrefetchAsync should prefetch the data to the specified destination device
Pass the device agent specified by the user to the ROCr api instead of passing the device agent attached to the specified stream

Change-Id: I86c98935b9dc404eaa6d47ccdd082a8c3678fb36
2021-08-27 05:12:07 -04:00
Satyanvesh Dittakavi 48c1b895c0 SWDEV-299491 - Update data index in GetSvmAttributes appropriately
Fixes Seg fault caused when the attribute hipMemRangeAttributeAccessedBy
is queried using hipMemRangeGetAttribute

Change-Id: I2ceb2267d89bfc31a55d9eae2685610c7ad89b1f
2021-08-26 13:36:35 -04:00
Saleel Kudchadker 75fea4dca6 SWDEV-297448 - Improve logging
Print non pointer kernel args
Change-Id: Ice0dbc894aae1430ac085df319f4b91dfa21665a
2021-08-25 15:46:06 -07:00
Saleel Kudchadker 24442be35a SWDEV-297448 - Refactor streamOperations code
Reuse FillMemory function, that should fix the cache syncs from the host

Change-Id: Ieebec5fc3ed3a322b88d5187c8dca4805ec6f84b
2021-08-25 12:33:02 -04:00
Saleel Kudchadker 3a7008cf07 SWDEV-297448 - Fix typo in debug print
Change-Id: Idc94d5fcd7eabf1e9c0a9617b987c58f507813a7
2021-08-22 23:56:08 -07:00
Saleel Kudchadker 2e26ed1cbb SWDEV-297448 - Add debug log print
Change-Id: Ieba1b2e5d766e3fbe84dfc875dde8268166b3f99
2021-08-22 23:56:08 -07:00
Satyanvesh Dittakavi b46ffd5fe0 SWDEV-274145 - Fix to return correct data when queried for hipMemRangeAttributeReadMostly attribute
Change-Id: I9041c974b61e7a9c8fbdc748a407bbd04c060876
2021-08-22 23:56:08 -07:00
Vladislav Sytchenko f167136918 SWDEV-297808 - Don't update free memory counter when creating views
Current logic when creating a buffer view will end up going into the
allocation block. Even though no memory will be allocated, since
owner()->getSvmPtr() is already allocated, we'll still end up
calling updateFreeMemory().

Checking if we're creating a view, will skip the SVM allocation logic
and let us fall into the actual view creation logic. This won't end up
updating the free memory counter.

Change-Id: I1c260a9ef57895130b272ea1246e06e812b25b37
2021-08-22 23:56:08 -07:00
German Andryeyev 992830bab7 SWDEV-295555 - Add SVM mode query
The new query MemRangeAttribute::CoherencyMode can return current
coherency mode for the provided memory region. Coherency mode can
be one of the following types: FineGrain, CoarseGrain and
Indeterminate

Change-Id: Ib66feeeb14f57a8b1cc731c65bb3d0276d297ff7
2021-08-22 23:56:08 -07:00
German Andryeyev ec89348291 SWDEV-296329 - Add lock protection for Timestamp update
There is a possible race condition when signal reuse can have
access to a destroyed Timestamp object, because the callback
was running asynchronously. Use reference counter and lock
to allow asynchronous timestamp update

Change-Id: I6224f7c62cb0a03a7466fcc512e5e5afb06736fa
2021-08-22 23:56:08 -07:00
anusha GodavarthySurya 1884e4ca77 SWDEV-297215 - Set image descriptor as per the HSA specification for hsa_ext_image_descriptor_t
Change-Id: I0af0f09120f15a42349ec4de491df8aee7bfd46d
2021-08-22 23:56:08 -07:00
Rahul Garg e9c115ad78 SWDEV-293742 - Remove external refs
Change-Id: Ib9e25a6beb97cc042bb3cc50338686a8dd09e21c
2021-08-22 23:56:08 -07:00
Jason Tang f165737096 SWDEV-296911 - Enable clgl interop for both MesaGL and OrcaGL
Change-Id: Ie3ad85a8335b1fc751812c09bb0cd30aad38dcae
2021-08-22 23:56:08 -07:00
Satyanvesh Dittakavi 924695fb5e SWDEV-292021 - Fix Device Reset
- Device Reset should not purge the allocations that were not by the user
- Addresses QMCPack Test abort due to the removal of all the mem objects during reset

Change-Id: I7b7a123e72bcc985d7e51d17c2382bc618d3e041
2021-08-22 23:56:08 -07:00
German Andryeyev 2babcfbdbb SWDEV-290384 - Enable active wait on CPU if HIP requested
Change-Id: Idea5adf7a4705cb999da6785e6229fe3200dce17
2021-08-22 23:56:08 -07:00