Added global flag g_IsEmuMode and set it when running under emulator.
Adjusted delays in KFDCWSRTest for emulator.
Change-Id: Ia5c0be40816ac2219add943e306ee16438f5b852
Signed-off-by: David Belanger <david.belanger@amd.com>
[ROCm/ROCR-Runtime commit: 3dd98d075f]
The old Largest Buffer search algorithm is using Binary Search
algorithm to find last successful memory allocation. But each
successful memory allocation takes times. Since the unsuccessful
memory allocation returns very quick. Changing the search algorithm
to find first successful memory allocation starting from MAX, each
testing step with granularity interval will speed up this test.
Change-Id: I07daea05423c33e72a483f0013e8ea1b5dabf989
Signed-off-by: James Zhu <James.Zhu@amd.com>
[ROCm/ROCR-Runtime commit: f75fddb9bd]
This patch is to add APUs judgement in LargestVramBufferTest criteria.
Change-Id: Ic69093f8ebed8be0b1c58787e2a294d86fb49bb0
[ROCm/ROCR-Runtime commit: 808a4428b6]
When xnack is on shadder code in this test triggers gpu page fault that migrate
data from system ram to vram. Use svm range granularity to move all data from
system buffer to vram to reduce system ram pressure to avoid system ram oom for
systems that has less system ram.
Signed-off-by: Xiaogang Chen <Xiaogang.Chen@amd.com>
Change-Id: I219472210756be319491f7827f7209fe32726f81
[ROCm/ROCR-Runtime commit: 1a7162731e]
For "Intel Meteor lake Mobile", the cache info is not in sysfs,
That means /sys/devices/system/node/node%d/%s/cache is not exist,
but system working fine.
Change-Id: Ie7c04426791a84c2288ff21df093226828a5f629
Signed-off-by: Gang Ba <Gang.Ba@amd.com>
[ROCm/ROCR-Runtime commit: 4bf73f521b]
IOMMUv2 is removed from AMDGPU/KFD.
Change-Id: Ia00f9aa879a5f32a42bec914936d105d6845bc60
Signed-off-by: James Zhu <James.Zhu@amd.com>
[ROCm/ROCR-Runtime commit: 693e686c4d]
Debug test shaders should use camel case and suffix *Isa to match other
test shader naming convention.
Signed-off-by: Jonathan Kim <jonathan.kim@amd.com>
Change-Id: I64e14183ba1c7c9664b13a742a0e5683866e8223
[ROCm/ROCR-Runtime commit: fcec22716a]
MCPU const char * always returns true, so check the value instead.
Before: if (!MCPU) {
After: if (!*MCPU) {
Signed-off-by: Ori Messinger <Ori.Messinger@amd.com>
Change-Id: I414e091ca764095937311648c534351d6abf30e6
[ROCm/ROCR-Runtime commit: 5f117f7608]
Use memset to avoid general 0 set padding issues and ASAN compile issues
for debug tests.
Signed-off-by: Jonathan Kim <jonathan.kim@amd.com>
Change-Id: I0a5aca5b7b631083599573b47f1ae87d5d0d5d71
[ROCm/ROCR-Runtime commit: f9e20c8a93]
In ASAN builds, the compiler used is clang. The initialization of
variable sized array using assignment operator is causing compilation
failure in ASAN builds. Used memset to fix the same.
Change-Id: I02aef3b99a6cad0cce3a378210a48732e07a88fb
[ROCm/ROCR-Runtime commit: 65911e8368]
Add test to catch trap on wave start or end override event.
Signed-off-by: Jonathan Kim <jonathan.kim@amd.com>
Change-Id: Icb57af64475fbd2d8a6c0af9a2ee5db5d1a169c6
[ROCm/ROCR-Runtime commit: a3f8085025]
Address watch test will test read and write operations.
Test will also check if operation is precise if precise
address watch is available.
Signed-off-by: Jonathan Kim <jonathan.kim@amd.com>
Change-Id: I7ef835790e26bf6345682755d7dd26a35853bcd5
[ROCm/ROCR-Runtime commit: 8311ca5bfa]
For GFX11 debugger testing, waves require to start in non-priv mode for
some test cases, so allow tester to set this.
Signed-off-by: Jonathan Kim <jonathan.kim@amd.com>
Change-Id: Iee93fda926bfd336d51c79c086f1f75bc35b70e5
[ROCm/ROCR-Runtime commit: 6c5121faff]
Add queue suspend and resume test.
Signed-off-by: Jonathan Kim <jonathan.kim@amd.com>
Change-Id: I2ade721026cbb458a3597b7858a164e70fe05f4f
[ROCm/ROCR-Runtime commit: d20f0bbb90]
Add queue and devices snapshot operations.
Signed-off-by: Jonathan Kim <jonathan.kim@amd.com>
Change-Id: I836884c9f3b65dd9e5e444d554d3eb87938e1634
[ROCm/ROCR-Runtime commit: b0e84183c1]
Add base debug operations to suspend and resume queues.
Routine will return the number of queues successfully
suspended or resumed.
Signed-off-by: Jonathan Kim <jonathan.kim@amd.com>
Change-Id: I8f18317f70464b04231c5cf822e11d545ebfa02a
[ROCm/ROCR-Runtime commit: 5a675921ea]
Check that a jump to trap event can be picked up by the debugger.
Signed-off-by: Jonathan Kim <jonathan.kim@amd.com>
Change-Id: Iad5f87092f2b82d5018013bba548979122a9bd02
[ROCm/ROCR-Runtime commit: b77189cf83]
Add set exceptions enabled debug option
Signed-off-by: Jonathan Kim <jonathan.kim@amd.com>
Change-Id: I6ee1769bbbb90a74074d8100974c4bfeabaf7f2c
[ROCm/ROCR-Runtime commit: 97fc25bb8d]
Add debug attach and runtime enable test for attaching to a spawned and
running process.
Signed-off-by: Jonathan Kim <jonathan.kim@amd.com>
Change-Id: I72302ff73494d9dae0c79a299508085d7ca0552b
[ROCm/ROCR-Runtime commit: 097ee967d1]
Add base debug class and attach/detach operations.
Signed-off-by: Jonathan Kim <jonathan.kim@amd.com>
Change-Id: I60f3c166646f05838fec208ac2f59bba998c63f8
[ROCm/ROCR-Runtime commit: dd56b38c2f]
Remove all unused material from KFDDBGTest.
Signed-off-by: Jonathan Kim <jonathan.kim@amd.com>
Change-Id: I13ed68656efadef7bbaf8bb737ce5a04829eca9b
[ROCm/ROCR-Runtime commit: 98c6784cc1]
For xnack off, skip SVM evict tests if memory allocation size is larger
than 15/16 total system memory, because the test may fail to allocate
CWSR svm range to create queue after allocating test memory.
Limit eviction size from total VRAM size to 1/2 total VRAM size,
because for 192GB VRAM, evict 192GB may takes more than 120 seconds
and cause test timeout failed.
Change-Id: Ib1483b9aab580a8539187b2943cadea0fd5a7c71
Signed-off-by: Philip Yang <Philip.Yang@amd.com>
[ROCm/ROCR-Runtime commit: a395dd7306]
If asics don't need software traps within GFX11 domain,
test with COMPUTE_PGM_RSRC1.PRIV = 1 will make system hang.
Change-Id: I00cf8eb6d6b07856885c77bd343ca3c41cc3cad5
Signed-off-by: Ruili Ji <ruiliji2@amd.com>
Signed-off-by: Aaron Liu <aaron.liu@amd.com>
[ROCm/ROCR-Runtime commit: 9bf1cbe4ed]
Typo to calculate bufferSize from vramBufSizeInPages. The OOM shows up
only with HSA_XNACK=1 because HSA_XNACK=0 doesn't support VRAM
oversubscription. We changed to run SVM tests with both XNACK off and
on.
Change-Id: I3949959288fd92f4e7f4a87115a5f1547e225042
Signed-off-by: Philip Yang <Philip.Yang@amd.com>
[ROCm/ROCR-Runtime commit: 29b04c2534]
Add 5 different test scenario to cover new event age tracking features.
Change-Id: Icab43240fd127208b18abbd7542d6444127ef0c7
Signed-off-by: James Zhu <James.Zhu@amd.com>
[ROCm/ROCR-Runtime commit: 4ba8f1fe77]
The purpose of this patch is to fix a minor typo in KFDSVMRangeTest.
Before:
"Skipping test: no enough system memory."
After:
"Skipping test: Not enough system memory."
Signed-off-by: Ori Messinger <Ori.Messinger@amd.com>
Change-Id: I247cb558a177a1d25c393bf16c7386f4d79d0fba
[ROCm/ROCR-Runtime commit: 4675492852]
Compiler behavior is undefined if the right operand is negative,
or greater than or equal to the width of the promoted left operand.
For release builds with address sanitizer enabled, this compiler
optimization behavior leads to unsupported queue size value since
current method shifts till 128 bits on a 64 bit value.
Signed-off-by: Sreekant Somasekharan <sreekant.somasekharan@amd.com>
Change-Id: Iafdc82d0dfb7f79e3012fb7bb70eda80e4b7a7a6
[ROCm/ROCR-Runtime commit: 1428a7538e]
Have hsaKmtMapMemoryToGPU return same value as fmm_map_to_gpu to keep consistency.
Signed-off-by: Xiaogang Chen<Xiaogang.Chen@amd.com>
Change-Id: Ifabb72301e1d5a6c1310973bb1321714e12a1fa6
[ROCm/ROCR-Runtime commit: 7e4e57ae5f]
Alloc vram by kfd, then map by GEM api to GPU VM and map to CPU VM.
Signed-off-by: Xiaogang Chen<Xiaogang.Chen@amd.com>
Change-Id: Ib5b2f35662cd5473f622f6ffc9b62925fe57ae42
[ROCm/ROCR-Runtime commit: 108c0e5f92]
Add parameterization for KFDSVM tests so that we test with both XNACK
enabled and XNACK disabled. This will be overridden by HSA_XNACK, if set
Change-Id: Ie96eb61c03115f947e08cfa076ac459f7440f5d8
[ROCm/ROCR-Runtime commit: 478a68d49c]
Starting with GFX11, wptr BOs must be mapped to GART for MES to determine work
on unmapped queues for usermode queue oversubscription (no aggregated doorbell)
Change-Id: I10e30fdc2bec587cef9427faa4874957988c34b3
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
[ROCm/ROCR-Runtime commit: d319660838]
If MES is enabled, wptr has to be non paged memory,
Add an API to check this condition.
Change-Id: I53af1f6687d5332d102e7062c3d760e33b96e722
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
[ROCm/ROCR-Runtime commit: 53ed978c3d]
If Dev0 and Dev1 are not the same gfx, we should temporarily
set the target ASIC for compiling Shader code.
Signed-off-by: Shane Xiao <shane.xiao@amd.com>
Signed-off-by: Shikai Guo <shikai.guo@amd.com>
Change-Id: I5836beb16ade519f5a148d3d2b9c2875554f0c35
[ROCm/ROCR-Runtime commit: 5d6f900353]
Overload Assembler::RunAssembleBuf to take in an extra Gfxv parameter.
Using this overload will temporarily set the target ASIC to Gfxv before
calling RunAssemble, and copy back the original MCPU literal upon
completion. The copy to reset the original MCPU in this case is safe as
the MCPU length is always known.
This will be useful in multi-device test cases whereby the devices are
not necessarily the same gfx version. The overload is explicitly for the
RunAssembleBuf wrapper rather than RunAssemble to ensure the default
MCPU is always reset independent of errors in RunAssemble.
Signed-off-by: Graham Sider <Graham.Sider@amd.com>
Change-Id: I7fe5a962876314b6df32e4b7160174949d98f9e3
[ROCm/ROCR-Runtime commit: 54136f60a0]
LLVM MC does not seem to accept multi-line conditionals. This may be
fixable in the future with macros. The Aqua Vanjaram shader spec states
that while buffer_invl2 has been replaced by buffer_inv, the former may
still be used for compatibility. However, this does not seem to be
implemented. For now, fix conditional.
Signed-off-by: Graham Sider <Graham.Sider@amd.com>
Change-Id: I7f8b64c96055371d7e0090b758d2cfd2a37ecd3c
[ROCm/ROCR-Runtime commit: 92f3d4a458]
These tests should also pass on Aqua Vanjaram, so enable them
Signed-off-by: David Francis <David.Francis@amd.com>
Signed-off-by: Graham Sider <Graham.Sider@amd.com>
Change-Id: Ibbb9cd43d653c63b08c39efd1d7326cfac1f8411
[ROCm/ROCR-Runtime commit: eed5518e4c]
Aqua Vanjaram is intended to have fine-grained coherency
from anywhere to anywhere else using read-acquire and
write-release primitives.
Add a test that writes to memory covered by five
different cache lines, then write-releases, while
another thread read-acquires, then reads those
five locations in memory.
There are nine variations of the test to cover
CPU-GPU, same-GPU and across-GPU, vector instructions and
scalar instructions, and data local to the
acquirer or receiver.
Signed-off-by: David Francis <David.Francis@amd.com>
Change-Id: I20d2db5c53bd280e971479aad7e61df6ed5d3623
[ROCm/ROCR-Runtime commit: 30b1f23f7a]
For vector iterator loop access current node directly, don't need
gpuNodesAll.at(i), which also causes out of range access.
Change vector index loop to iterator loop to simplify the code.
Change-Id: I2627ef8d13b5d2c9cd8c51cf4dacc3e8a97fcfb0
Signed-off-by: Philip Yang <Philip.Yang@amd.com>
[ROCm/ROCR-Runtime commit: 0696f06c16]
AppAPU VRAM is part of system memory managed by Linux kernel, no
VRAM eviction and restore is needed between VRAM and system memory.
Those Evict test failed on AppAPU now, skip those tests on AppAPU.
No page migration between VRAM and system on AppAPU, HMMProfilingEvent
depends on migration event, skip it on AppAPU.
Change-Id: I4c809b97c947e809d136c1f88db2278cf74f5b47
Signed-off-by: Philip Yang <Philip.Yang@amd.com>
[ROCm/ROCR-Runtime commit: 21abaef3f8]
If there is connection between GPU and CPU with weight 13,
KFD_CRAT_INTRA_SOCKET_WEIGHT, then this is AppAPU.
This will be used to skip tests not suitable for AppAPU.
Change-Id: If6fad81528b52afd4ac4cefa508d787b0f6637ca
Signed-off-by: Philip Yang <Philip.Yang@amd.com>
[ROCm/ROCR-Runtime commit: e2df2c21af]
For GC 9.4.0, modifications were made to various shaders since certain
flat_ instructions no longer support glc/slc modifiers (replaced with
nt/sc1/sc0). Instead of repeating conditionals inside various shader
bodies, we can make use of LLVM AMDGCN macros.
This patch modularizes the shader macros into seperated defines. Prior
to the core raw-string literal, each shader now starts with the
SHADER_START literal (".text\n") plus any number of SHADER_MACRO_*
literals. This allows us to seperate the macro definitions logically and
use the pre-processor to only include the required macro groups on a
per-shader basis.
Signed-off-by: Graham Sider <Graham.Sider@amd.com>
Change-Id: I19eb3fd14252a0601bb7509249051b68e7fdb02a
[ROCm/ROCR-Runtime commit: e2435d9e93]
Previously, KFDEvictTest.QueueTest and KFDSVMEvictTest.QueueTest
would create a variable number of wavefronts, one for each 64MB
of memory under test. This ran into limits on the buffers used
by the wavefronts, and may at some point have exceeded the
wavefront limit.
Restrict the number of wavefronts to 512, and adjust the shader
to accomodate a variable buffer size
Signed-off-by: David Francis <David.Francis@amd.com>
Change-Id: I2ec292e2900e2efa62a08313bca3d2f4bdabca8b
[ROCm/ROCR-Runtime commit: 680c8ca5a9]
David Belanger
James Zhu
Yifan Zhang
Xiaogang Chen
gaba
Jonathan Kim
Ori Messinger
Ranjith Ramakrishnan
Philip Yang
Ruili Ji
Sreekant Somasekharan
Kent Russell
Shane Xiao
Graham Sider
David Francis