also validate the flag argument passed to hipIpcOpenMemHandle API and return
error if it is not equal to "hipIpcMemLazyEnablePeerAccess" (defined to 0)
and it is the only supported flag currenlty for this API.
SWDEV-253462
Change-Id: Ie1c8b79c680a29dc72bf262cf53ae5e011fb1247
[ROCm/clr commit: 89964dbbd4]
APIs: hipModuleLoad, hipModuleLoadData and hipModuleLoadDataEx,
hipModuleGetGlobal(), hipModuleGetFunction
Functional and negative tests
Repeated call to ModuleLoadXX/ModuleUnloadXX
Few tests are disabled now, will be enabled when functional
SWDEV-238517 for enhancing hip unit tests
Change-Id: I65c12027e32db80213468fdee1c5cc1aa3e60bfd
[ROCm/clr commit: 4f48154f46]
This is helpfull to do when debugging issues on lowend asics. Navi14 can be emulated as Navi10. So can Navi22 be emulated as Navi21.
Change-Id: I693ffd45a5b03657822afdc872781901bc69b65c
[ROCm/clr commit: 26d1b28b16]
Check for rocm_agent_enumerator instead of rocminfo or
.info/version.
Change-Id: I1718bd4f70b3e527ea3afe19c1a685ab7ed70808
[ROCm/clr commit: 5a46d80682]
The device side assertion calls printf to write out a message. In the
device compiler, printf is expanded into a series of hostcalls that
transmit the printf payload to the host. This expansion increases the
length of the kernel, resulting in sub-optimal compilation. The
solution is to ensure that the assert() implementation is not inlined
into the kernel.
Change-Id: Ia3a075461a755cf007218f262b0863e1926c76aa
[ROCm/clr commit: 160dfb5a1f]
With the PAL_ALWAYS_RESIDENT flag memory objects are resident at allocation time, no need to make them resident again before submit.
Also we should never evict anything with this setting, or we'll generate a VM fault.
Change-Id: Ieacc6af88ab4e09c20efd94100e148b2502e1d70
[ROCm/clr commit: fd09a7a23c]
hipStreamDestroy() by definition doesn't guarantee waiting for all stream operations.
Change-Id: Ibfd21c48d71741ebcbcb9898c8b5ac235bdc570b
[ROCm/clr commit: f2c2fd3d09]
Add extra API calls for managed memory: hipMemAdvise, hipMemPrefetchAsync,
hipMemRangeGetAttribute
Change-Id: Ifb09744acdf7582d278453707373c89c30e3ed03
[ROCm/clr commit: 4ee6d78763]
Positive and negative test cases for atomicAdd and
AtomicAddnoRet device functions
SWDEV-238517 for enhancing hip unit tests
Change-Id: Id20ba2550d20f224004f105cdcd087002cb80e56
[ROCm/clr commit: 00d46218b7]
Additional tests for following APIs
- hipOccupancyMaxActiveBlocksPerMultiprocessor
- hipOccupancyMaxPotentialBlockSize
SWDEV-238517 for enhancing hip unit tests
Change-Id: Ib9441c1366f46a082e10eb1a572bc7d8ebe1ee37
[ROCm/clr commit: 4eb65d58dd]
Currently all the logic checks if __HIP_ENABLE_PCH is set, so setting it
to OFF will still enable PCH.
Switching __HIP_ENABLE_PCH to be a CMake option will enable correct
build behaviour.
Change-Id: I77a663589ffb5f2595c6ad3d144eb9466adcf250
[ROCm/clr commit: 8034467ec3]
The change reuses HSA signals for dispatches as a wait signal.
Skipping the barrier requires to disable L2 cache for sysmem
allocations and extra tracking for HDP access with the large bar.
ROC_BARRIER_SYNC=0 activates the new logic. Barrier sync is
still used by default.
ROC_ACTIVE_WAIT=1 enables unconditional active wait in ROCr.
The change also consolidated ROCr wait logic under single function.
Change-Id: I6bd1be30aa88258da1b1f9de319ef5a45852afd8
[ROCm/clr commit: d9397590de]
Unit testing of CG threadRank api in multi-grid environment requires
some changes as grid id of particular device is not known apriori.
Change-Id: Ie7941a09337653f3ada5eedfb7c64a93a234498b
[ROCm/clr commit: 9c86cdb89d]
German Andryeyev
Rahul Garg
Aryan Salmanpour
Lakhan singh Thakur
Rupam Chetia
Julia Jiang
Vladislav Sytchenko
agodavar
Chauncey Hui
Freddy Paul
Tao Sang
Sameer Sahasrabuddhe
Yaxun (Sam) Liu
Jason Tang
Payam
sumanthtg
Sourabh Betigeri
Sarbojit Sarkar
kjayapra-amd
Jatin Chaudhary
mshivama