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kjayapra-amd cfb15c6c5d SWDEV-294420 - Ignore Image blit kernels if image instructions are not supported.
Change-Id: I145172672b0b032aa722649b0c4ca9267e3e5c85


[ROCm/clr commit: 7413b7f79b]
2021-10-05 18:12:44 -04:00
German Andryeyev 2cb7467eff SWDEV-303560 - Remove coarse grain setup by default
The original logic was left after initial testing when HMM
couldn't handle xnack properly

Change-Id: I0abf01805704171e931dfba8b6d95bfe87d5fab1


[ROCm/clr commit: d17108e8d0]
2021-10-05 17:20:59 -04:00
kjayapra-amd ead79defbe SWDEV-295277 - Report max waves per cu from ROCr backend.
Change-Id: Ie170b26b53f1cc2da851034c96b21de38ce7b563


[ROCm/clr commit: 3081f7ca53]
2021-10-05 12:38:44 -04:00
Tao Sang e425c5e79b SWDEV-305884 - Clear up codes
Fix a log typo error
Change-Id: I887ecbdcfe414c2119247228bdd1255b8308da1d


[ROCm/clr commit: 10abe8ab37]
2021-10-04 18:11:32 -04:00
German Andryeyev 4aed0e4a01 SWDEV-296301 - Avoid deadlocks in the hostcall path
Change the scope of hostcall buffer access lock during destruction.
Make sure wait() returns the signal value after timeout. That
matches ROCr behaviour for HSA signal wait.

Change-Id: I3df34207e0c2e21972ec8052777e5742bda1dca0


[ROCm/clr commit: 9a9d10a10b]
2021-10-04 15:00:44 -04:00
Julia Jiang 1778d99932 SWDEV-302493 - Comgr API backward compatible
Change-Id: I3d796d10fa1dbb7edb0510f8ed7d44e3b4993bd7


[ROCm/clr commit: 3098324ef7]
2021-09-29 11:43:43 -04:00
Sarbojit Sarkar c053c7d17c SWDEV-301823 - Optimize hipMemset2D/3D
Change-Id: Ibe560149a263c2ac6b08e4eb1a1d331d2aeac78c


[ROCm/clr commit: 22a847f3ce]
2021-09-27 14:10:06 -04:00
Sourabh 936e0836a8 SWDEV-292525 - [vdi] Path to streamOps shaders
Implementation to use a blit kernel to perform
a hipStreamWait/write instead of an AQL packet.

Change-Id: I462671ed5cec37144dfe97ff66439249196117c1


[ROCm/clr commit: cbb8d82bdb]
2021-09-27 13:59:35 -04:00
Jason Tang b47bd6138e SWDEV-1 - Only check agent-binary ISA compatibility for online device
Change-Id: I5c8395c646280b8316e2f1af9f1e624359166cba


[ROCm/clr commit: e0bd4aad63]
2021-09-23 16:03:01 -04:00
Jason Tang e1b16403b9 SWDEV-1 - More 'delete' clean up
info_.extensions_ and settings_ are deleted at amd::Device()::~Device().

Change-Id: I06f240a42e5c131dbd4e61a759f905bcdf84b45a


[ROCm/clr commit: f212fc91ca]
2021-09-21 11:17:24 -04:00
German Andryeyev c99468853f SWDEV-292408 - Don't force high clock for HIP
Change-Id: I501f4e5272124025068b1d3cb637ee8061b06467


[ROCm/clr commit: 51556711dc]
2021-09-20 18:44:11 -04:00
German Andryeyev 83d83e6166 SWDEV-302383 - Get active state from device
The queue can be destroyed at the time the app will request
the event status. Hence just get the active state from the device.

Change-Id: I887ecb0cfe414c2119247228b0d1255b8308da1e


[ROCm/clr commit: f116959b54]
2021-09-14 19:01:44 -04:00
German Andryeyev e4ae79ca4a SWDEV-282419 - Use HSA_AMD_SVM_ATTRIB_AGENT_ACCESSIBLE for unset
When unsetting runtime should use HSA_AMD_SVM_ATTRIB_AGENT_ACCESSIBLE
for the agent and not HSA_AMD_SVM_ATTRIB_AGENT_ACCESSIBLE_IN_PLACE

Change-Id: I3814802d1fb3b72c54e7566defafafed6b0d5cee


[ROCm/clr commit: d8a86e4870]
2021-09-13 15:05:20 -04:00
German Andryeyev 28c4d9c0df SWDEV-294669 - Keep one more slot for HW processing
The original logic left only one slot for HW processing in the queue.
For some reason there is a race condition on CPU overwrite of the slot
before the current active. The workaround is to avoid the previous to
the current active slot for possible unfinished HW processing.

Change-Id: I565495a8feeaedffc9fc8a505edbee5ff5816975


[ROCm/clr commit: 65ddfcc6a8]
2021-09-13 13:56:05 -04:00
Jason Tang e94aec09bd SWDEV-1 - Some 'delete' clean up
Change-Id: I02564f0f0e349375bde1471e9f82df268703367b


[ROCm/clr commit: 73967c3b17]
2021-09-09 12:12:40 -04:00
Saleel Kudchadker 36ec8c8871 SWDEV-297448 - Add 64bit and 16bit write support
For the fillBuffer shader, if there are two 32bit writes to a MMIO
register, it can get dropped. It has to be a single 64bit write.
Add optimization to fillBuffer to write 64bit and 16bit writes.

Change-Id: I3aa78e027898f8ae01e9c8f09004615673720c2b


[ROCm/clr commit: 21ba34d0fe]
2021-09-08 12:30:04 -04:00
Jatin Chaudhary f020572d6e SWDEV-299162 - Add new comgr API to demangle names
Change-Id: I84174d7e40e9afff9a8ea135abadb69d580478e0


[ROCm/clr commit: b5a57327bb]
2021-09-08 00:35:34 -04:00
Sarbojit Sarkar 45953e81dd SWDEV-300655 - Added thread ID to hip trace
Change-Id: I9234d4ec93e7687cd0a5d1bd930bd4f80936311b


[ROCm/clr commit: 42d33029dc]
2021-09-06 00:22:42 -04:00
Saleel Kudchadker 1bf9b39cf8 SWDEV-301667 - Kern arg placement
Add a env var ROC_USE_FGS_KERNARG to toggle kernel arg placement
By default its in Fine Grain Kernel arg segment for supported asics.

Change-Id: I3d57ed69a1a4db2b392b0438ead499f3ddca4716


[ROCm/clr commit: e29b9c00ee]
2021-09-02 12:36:49 -04:00
jujiang 7c7a6ee346 SWDEV-286322 - clean up trailing white space
Change-Id: I01f3a559cbd1835aa2fdad7abe2bd685d90fc6a8


[ROCm/clr commit: f63115cec6]
2021-09-01 11:45:47 -04:00
Jason Tang d623a6de19 SWDEV-294768 - Fix PCMark10 performance drop
PCMark10 counts the time spent in clCreateKernel as part of execution
time, so as workaround for the PAL path, move code object loading
back to clBuildProgram.

Change-Id: I3b9cf1879ece08ab59f447ec165b0525bc8593a4


[ROCm/clr commit: 1d0364e590]
2021-09-01 09:25:40 -04:00
Jason Tang d1a3931d68 SWDEV-1 - Disable OpenCL support for gfx8 in ROCm path
Change-Id: Ie1e0c0d6273edf6b734909447c2a08252cba305b


[ROCm/clr commit: 7f83bcdb45]
2021-08-31 12:48:47 -04:00
Satyanvesh Dittakavi c4bba2456b SWDEV-298985 - hipMemPrefetchAsync should prefetch the data to the specified destination device
Pass the device agent specified by the user to the ROCr api instead of passing the device agent attached to the specified stream

Change-Id: I86c98935b9dc404eaa6d47ccdd082a8c3678fb36


[ROCm/clr commit: 169cc857fd]
2021-08-27 05:12:07 -04:00
Satyanvesh Dittakavi 9805fb774e SWDEV-299491 - Update data index in GetSvmAttributes appropriately
Fixes Seg fault caused when the attribute hipMemRangeAttributeAccessedBy
is queried using hipMemRangeGetAttribute

Change-Id: I2ceb2267d89bfc31a55d9eae2685610c7ad89b1f


[ROCm/clr commit: 48c1b895c0]
2021-08-26 13:36:35 -04:00
Saleel Kudchadker 96f2bdd6ce SWDEV-297448 - Improve logging
Print non pointer kernel args
Change-Id: Ice0dbc894aae1430ac085df319f4b91dfa21665a


[ROCm/clr commit: 75fea4dca6]
2021-08-25 15:46:06 -07:00
Jason Tang 9dd3967661 SWDEV-1 - Correct class name
Change-Id: I20d7092e010cabae6ac1a4eb39a62112fe4c6629


[ROCm/clr commit: 75cafd85b8]
2021-08-25 16:31:46 -04:00
Saleel Kudchadker 8e13d117e4 SWDEV-297448 - Refactor streamOperations code
Reuse FillMemory function, that should fix the cache syncs from the host

Change-Id: Ieebec5fc3ed3a322b88d5187c8dca4805ec6f84b


[ROCm/clr commit: 24442be35a]
2021-08-25 12:33:02 -04:00
Jason Tang 91dc2d93f9 SWDEV-297294 - Make sure the binary ISA is compatible with the agent ISA
Change-Id: Idf86714d1a494d24faa665c9fede1e776ce253f1


[ROCm/clr commit: cb41710384]
2021-08-22 23:56:08 -07:00
Saleel Kudchadker e453f30eec SWDEV-297448 - Fix typo in debug print
Change-Id: Idc94d5fcd7eabf1e9c0a9617b987c58f507813a7


[ROCm/clr commit: 3a7008cf07]
2021-08-22 23:56:08 -07:00
vpykhtin a3b0a8aed0 SWDEV-1 - OpenCL binary substituion feature based on source program text hash matching.
This patch allows to substitute binary for the opencl program. It supposed to be used as:

1. Run the opencl program with -save-temps.

2. Open the cl temp and find the following text in the program header:
    Hash to override:
	Source: 0xd66bcfa20e69e605
	Source + clang options: 0x656a9dd8aedcbfb6

3. Create config file (ascii text) with a pair(s):

    <hash> <path_to_binary_to_substitute>

    where hash is the hex value from step 2 (without leading 0x), you can use either hash
    depending on what you're going to match:
	only the source text of the program or along with it's clang options.

4. Set the env variable AMD_OCL_SUBST_OBJFILE to the path of your config file.

5. Rerun the opencl program.

Change-Id: I977c80fe529ea14458194918c6ddfbe2de6a8857


[ROCm/clr commit: 51cc9c2f8c]
2021-08-22 23:56:08 -07:00
Saleel Kudchadker 14d8512375 SWDEV-297448 - Add debug log print
Change-Id: Ieba1b2e5d766e3fbe84dfc875dde8268166b3f99


[ROCm/clr commit: 2e26ed1cbb]
2021-08-22 23:56:08 -07:00
Jatin Chaudhary ff3101ca71 SWDEV-286257 - Check for --save-temps option for HIP. Create Temp files if its present.
Change-Id: Ie5787d03b73081bca1ad03699ed7015badc342c7


[ROCm/clr commit: 751937af14]
2021-08-22 23:56:08 -07:00
Satyanvesh Dittakavi 6c0e65ed4b SWDEV-274145 - Fix to return correct data when queried for hipMemRangeAttributeReadMostly attribute
Change-Id: I9041c974b61e7a9c8fbdc748a407bbd04c060876


[ROCm/clr commit: b46ffd5fe0]
2021-08-22 23:56:08 -07:00
Vladislav Sytchenko f34036e155 SWDEV-297808 - Don't update free memory counter when creating views
Current logic when creating a buffer view will end up going into the
allocation block. Even though no memory will be allocated, since
owner()->getSvmPtr() is already allocated, we'll still end up
calling updateFreeMemory().

Checking if we're creating a view, will skip the SVM allocation logic
and let us fall into the actual view creation logic. This won't end up
updating the free memory counter.

Change-Id: I1c260a9ef57895130b272ea1246e06e812b25b37


[ROCm/clr commit: f167136918]
2021-08-22 23:56:08 -07:00
German Andryeyev ee69220fb9 SWDEV-295555 - Add SVM mode query
The new query MemRangeAttribute::CoherencyMode can return current
coherency mode for the provided memory region. Coherency mode can
be one of the following types: FineGrain, CoarseGrain and
Indeterminate

Change-Id: Ib66feeeb14f57a8b1cc731c65bb3d0276d297ff7


[ROCm/clr commit: 992830bab7]
2021-08-22 23:56:08 -07:00
Todd tiantuo Li 9458b7ea4d SWDEV-1 - Rembrandt support
Change-Id: Id5c37e130fb2c0bdc01b84997c85324121ec4df9


[ROCm/clr commit: ec411737aa]
2021-08-22 23:56:08 -07:00
Jason Tang 4e818587a2 SWDEV-297294 - Fix TargetID typo
Change-Id: I351e38cbcaaf926f0561c96cf6e455e7167fd4be


[ROCm/clr commit: f42103c6a8]
2021-08-22 23:56:08 -07:00
Vladislav Sytchenko 48cbefdacf SWDEV-292408 - [PAL] Always force high clocks for HIP
Redshift sees around a 3x performance uplift this change.

Turning this on for OpenCL might cause unwanted behaviour, due to
apps like RSX running in the background all the time.

Change-Id: I9f32d5f2e05b6697a8aaa9ddf74474b5531bb7e1


[ROCm/clr commit: 2f00782829]
2021-08-22 23:56:08 -07:00
German Andryeyev b26c568a90 SWDEV-296329 - Add lock protection for Timestamp update
There is a possible race condition when signal reuse can have
access to a destroyed Timestamp object, because the callback
was running asynchronously. Use reference counter and lock
to allow asynchronous timestamp update

Change-Id: I6224f7c62cb0a03a7466fcc512e5e5afb06736fa


[ROCm/clr commit: ec89348291]
2021-08-22 23:56:08 -07:00
anusha GodavarthySurya 8af8d5bdc1 SWDEV-297215 - Set image descriptor as per the HSA specification for hsa_ext_image_descriptor_t
Change-Id: I0af0f09120f15a42349ec4de491df8aee7bfd46d


[ROCm/clr commit: 1884e4ca77]
2021-08-22 23:56:08 -07:00
Vladislav Sytchenko a4306451fe SWDEV-283981 - [PAL] Support hostcall SQ interrupt
Note that this requires base driver CL#2340320+ to have SQ interrupt
functionality enabled by default.

Change-Id: I04b936819ebe1eb7cf5de1db4fafe83af3a1b5f6


[ROCm/clr commit: 4171e9e0a3]
2021-08-22 23:56:08 -07:00
Rahul Garg 7f97db9c71 SWDEV-293742 - Remove external refs
Change-Id: Ib9e25a6beb97cc042bb3cc50338686a8dd09e21c


[ROCm/clr commit: e9c115ad78]
2021-08-22 23:56:08 -07:00
Jason Tang 8235cb4462 SWDEV-296911 - Enable clgl interop for both MesaGL and OrcaGL
Change-Id: Ie3ad85a8335b1fc751812c09bb0cd30aad38dcae


[ROCm/clr commit: f165737096]
2021-08-22 23:56:08 -07:00
Alex Xie 1ca153409c SWDEV-288853 - [OpenCL]: ASIC 1013 Bringup
This a cherry pick from the ASIC's branch.

Change-Id: Ic6e888f8fa96103d1e79432dd75e68faabd8cf6c


[ROCm/clr commit: ce5cc020af]
2021-08-22 23:56:08 -07:00
Vladislav Sytchenko 4a2da6ea45 SWDEV-293519 - [PAL] Limit mgpu SVM logic only to mgpu cases
Below logic allocates the host buffer whenever a subbuffer is created
from a SVM allocation. This is only needed for multi-device contexts.

HIP does not support multi-device contexts, hence this logic just ends
up performing unnecessary system allocations.

Change-Id: I8eae635f7c5289c52ef73434218c1658b788a456


[ROCm/clr commit: ffbf368f4c]
2021-08-22 23:56:08 -07:00
Aaron Liu 8979836575 SWDEV-294027 - [Lnx][YC] Add Yellow Carp support
Only add Roc path and don't use Pal path.

Signed-off-by: Aaron Liu <aaron.liu@amd.com>
Change-Id: I7117e2dc3c3ad4c8d563e9bbdc721f70ddba51fd


[ROCm/clr commit: c6574cb906]
2021-08-22 23:56:08 -07:00
Satyanvesh Dittakavi 04e5354d88 SWDEV-292021 - Fix Device Reset
- Device Reset should not purge the allocations that were not by the user
- Addresses QMCPack Test abort due to the removal of all the mem objects during reset

Change-Id: I7b7a123e72bcc985d7e51d17c2382bc618d3e041


[ROCm/clr commit: 924695fb5e]
2021-08-22 23:56:08 -07:00
Vladislav Sytchenko 9b02e5baa4 SWDEV-283981 - Revert "SWDEV-283981 - [PAL] Support hostcall SQ interrupt"
This reverts commit 9df70fa03ce60d47247eb0e8f278e1f8dbd33d6e.

Reason for revert: need SWDEV-294782 to be resolved before we can enable SQ interrupt support.

Change-Id: I328170b60f1a3aab28c0b1fd3191297a1a51ecb7


[ROCm/clr commit: 6566361144]
2021-08-22 23:56:08 -07:00
Vladislav Sytchenko b67329da52 SWDEV-291787 - Fix Windows build
Change-Id: I1b97a1100e4c498f53aaad7157f21d0c5f8a130d


[ROCm/clr commit: 0a59c9c4c3]
2021-08-22 23:56:08 -07:00
jujiang f0ec01f657 SWDEV-291787 - Fix persistent direct map
Change-Id: Ic1507cc6d63e9ed574e8e169bce7bf56f4792c19


[ROCm/clr commit: 84b971c7c1]
2021-08-22 23:56:08 -07:00