The updated sp3 compiler does not support GFX10 temperaly.
Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Change-Id: Idd9336663814b7925d9742eee0bd310d00945d3e
Fixes assembler error. The SP3 backend if already set to FamilyId.
Change-Id: I7721a555b05688b16993a03242a765694594825a
Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Increasing the timeout will avoid some test failures. This shouldn't
mask any issues as any incomplete shaders should still hang and would
just time out at 180 sec instead of 120 sec.
Signed-off-by: Kent Russell <kent.russell@amd.com>
Change-Id: If4e893ab80d9d159bd0b8b112aa7574abc5e4f44
amdgpu_cs_submit can fail intermittently if another process has too much
memory reserved at the time. Allow a small percental of command
submissions to fail to make the test more robust.
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Change-Id: If9f62b2b6f67be71420016d4e38d4dd6b6bca9a5
Delayed page faults from a terminated process can be attributed to the
next process with the same PASID. Work around that by adding a delay
after the Exception tests to allow the kernel to clean up any fault
storms before the next test.
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Change-Id: Id310c13ea9eb92b04d37b95d91a0dd60bd9954e5
If the signal arrives too late, it interrupts waitpid. Handle this
situation gracefully.
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Change-Id: If4925c352c81ba7fef8a940460b91f5e720b451e
It is gfx90a VF device ID, for virtualization support.
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Change-Id: I9e51d6b58c702d185e6758a9c511e9b8bc72c2f5
After unregistered memory is added, now default access attribute
is returned based on xnack configuration.
Change-Id: I8ef44fe1e165ba009622e8112436c1f7a683f6cb
Signed-off-by: Alex Sierra <alex.sierra@amd.com>
It is to address gfx90a HW memory model changes.
Signed-off-by: Eric Huang <jinhuieric.huang@amd.com>
Change-Id: Ie5c5c5ee5ddfb75c0b4f625baf59ce37b4cc7c31
KFDSVMEvictTest.QueueTest shader asm code need update to support gfx10
and gfx9, skip the test to unblock CI test.
Change-Id: Id2842127cf5fc98a652afa82035a4b3603bf5c33
Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Fixes assembler error. The SP3 backend if already set to FamilyId
Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Change-Id: If127a71693b293e2748b06efb668a359b939cd14
gfx10 GPUs such as gfx1030 need new assembly code to test
the GWS. Removed scalar stores and added proper usage of DLC and
VSCNT waits. Removed gfx9-specific assembler meta-values.
Change-Id: I2bbdb77692ace2dba10997f721ba9decaa9be82a
KFD changes are ready, all SVM tests should pass now. Skip SVM tests if
the SVM API is not supported.
Change-Id: I5e358565a0458eea45eae0aaf4969ce3a36574a7
Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Signed-off-by: Alex Sierra <Alex.Sierra@amd.com>
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
New properties SVMAPISupported added in Thunk spec HSA_CAPABILITY, read
from sysfs from KFD topology.
New local memory property flag CoherentHostAccess added to Thunk
HSA_MEMORYPROPERTY, read from sysfs from KFD topology.
Change-Id: I83933f0e5a61508508168873209dba4af0b77295
Signed-off-by: Philip Yang <Philip.Yang@amd.com>
XNACK API for GPUs that support this mode. This API
makes calls to amdgpu driver to configure xnack mode.
It supports set xnack mode and query the current mode used.
Change-Id: If865fd0e3f900f008243dc49504e1a0694e1791a
Signed-off-by: Alex Sierra <alex.sierra@amd.com>
Add function definitions to support SVM (shared virtual memory)
and xnack set.
Change-Id: Ia97ad9d0c449d8d500d799f702e1a58e87d65a56
Signed-off-by: Alex Sierra <alex.sierra@amd.com>
Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Add svm (shared virtual memory) range and xnack mode
APIs.
Change-Id: Ibd8d7fe566dc200730da0c892caa71aad7589ebd
Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Signed-off-by: Alex Sierra <alex.sierra@amd.com>
Query the KFD interface version once and store it in a global variable.
This makes it more efficient for KFD APIs to query the API version
later.
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Change-Id: I267f3465f754e78fb21a7c42c5877cd68eaa9d05
This can be overwritten by changing BUILD_SHARED_LIBS=true, but we
default it to static to allow for merging into ROCr
Change-Id: Ic286ef7903a5bc788fe3b84bb13b15bdd3a6f60b
These are failing as well, due to the SP3 shader merge. Blacklist them
as well to avoid more segfaults
Signed-off-by: Kent Russell <kent.russell@amd.com>
Change-Id: I07e142a1aad9b2a5304230f333eeaf4392bea4b7
The old bit was deprecated, because old buggy user mode depends on it
being always 0. The correct value is now reported in a new bit. New user
mode handles the reported EDC setting correctly, so we can report the
correct value in a new bit.
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Change-Id: Ib5d5ed2519810e650458c6b69c97670dab435ddb
This reverts commit 5ae49f2321.
SVM is not ready yet. This was merged by accident.
Change-Id: I8901594a72e785ba5d25a6448718a570e76fe117
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
This reverts commit a352639df5.
SVM is not ready yet. This was merged by accident.
Change-Id: I1bee102823e7e612be8e8f2e0f50580e8692cc80
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
This reverts commit 75e8fe383f.
SVM is not ready yet. This was merged by accident.
Change-Id: I372f7d293fd38429ec570bc0e0add7e612871594
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
This reverts commit 3f45f602d4.
SVM is not ready yet. This was merged by accident.
Change-Id: I7c0d835a0d3a448f2ac1094f818601e5d6363045
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
BLACKLIST_ALL_ASICS has to the first in the list otherwise "-" negative
flag won't be inserted
Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Change-Id: I9ee150d7f793809641b16012929c4e157595d37f
Possibly because of moving to gart table for vram access from Kernel.
This test failure shouldn't be a blocker. Temporarily blacklist till a
solution is found.
Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Change-Id: I99725f368aced863188e30f619288ad4d033b9a6
Set the KFD_IOC_ALLOC_MEM_FLAGS_COHERENT flag and
KFD_IOC_ALLOC_MEM_FLAGS_UNCACHED flag to allocate
uncached coherent memory when HSA_DISABLE_CACHE
environment variable is set. At KFD driver,
Single KFD_IOC_ALLOC_MEM_FLAGS_UNCACHED flag is
not sufficient to allocate uncached memory. We
have to use both two flags to allocate uncached
memory.
Change-Id: Ie490f37b2e696314e60048f5b1b57442431696e9
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
Three kfd subtests are added to verify new XGMI connection with
cache coherence HW link on A+A.
Signed-off-by: Eric Huang <JinhuiEric.Huang@amd.com>
Change-Id: I6960ec91cbfb696c4e6acb3b79fd83107003acdd
In A+A all system memory is mapped as NC. So add a new function
gfx9_PollNCMemory which will support NC memory.
Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Change-Id: I097b95fb156f73d6f480cd4fd262cc6fa5933f69
destBuf is mapped as cached, the intruction flat_atomic_add
operates on cache that cause test failed. Adding scc modifier
in the instruction will fix the issue.
Signed-off-by: Eric Huang <jinhuieric.huang@amd.com>
Change-Id: I8e138f93ae4f5e23020e3ac1549ef924968a74c5
The three kfdtests have been fixed, so remove them from
filter list.
Signed-off-by: Eric Huang <jinhuieric.huang@amd.com>
Change-Id: I101a72476970a9d105e8c0b5c022847757fdd316
Before gfx90a, coherent memory is uncached. So it was reasonable
when environment variable HSA_DISABLE_CACHE is set, memory is mapped
as coherent. On gfx90a, coherent memory can be cached, so mapping
memory as coherent can't guarantee memory is uncached. When
HSA_DISABLE_CACHE is set, we have to map memory as uncached.
Change-Id: Ia5ed4cf0ad6aef5644dc8c9e6632b52d606f06f4
Signed-off-by: Oak Zeng <Oak.Zeng@amd.com>
Refer to commit "Mark buffers accessed by CP as UC"
A+A buffers are mapped as NC. CP (PM4Writes) need ReleaseMem function to
ensure the write go through to the memory
Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Change-Id: I4ee55a6e40fba078f5950d95c8fee7ee076260bf
Refer to commit: " Mark buffers accessed by CP as UC"
Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Change-Id: I1816e035dbb3178f28f5e34b050c20ecca282060
This change might be redundant if ROCr takes care of it
Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Change-Id: I7b67143a8ad21baa61b7eda7b8e5fe0ac1e33830
This change is for the A+A bring-up branch as it needs to made more
generic to handle all ASICs.
For A+A all the system buffers are mapped as NC (non coherent) unless
explicitly marked as UC (uncached). The coherency is then expected to be
handled by shader by explicitly using acquire/release instructions.
However, CP doesn't have same feature. The buffers used by CP thus have
to UC. For now queue buffer and Signal handler memory is marked as UC.
This change shouldn't affect other ASICs since Uncached flag is not used
in those. However, this change still need to be made more generic.
Signed-off-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com>
Change-Id: I56c37a809913f7f08c94d01b0572d0f4864939aa
On gfx9, the maximum number of wavefronts per queue is the minimum of
40 waves per compute units, or 512 waves per shader engine. On gfx10,
there can only be 32 waves per compute units.
Signed-off-by: Laurent Morichetti <laurent.morichetti@amd.com>
Change-Id: I148d1a4fe6c07cdbfaa1f77939eb29311c81c008
Chengming Gui
Philip Yang
Kent Russell
Mike Li
Felix Kuehling
Alex Sierra
Harish Kasiviswanathan
Eric Huang
Joseph Greathouse
Roberto Di Remigio
Cole Nelson
Oak Zeng
Laurent Morichetti